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Presented By : Kiran Prajapati Pradeep Santdasani Internal Guide : Dhara Shah Lecturer (EC Dept.) L C Institute of Tech. External Guide : E P Balasubramanian Group Director SPSG Space Application Center (ISRO)
Agenda
y Overview of Satellite Communication y Overview of Digital Modulation y Description of QPSK Modulator y Steps of Project Implementation y Matlab Simulation of QPSK Modulator y Hardware Implementation of QPSK Modulator y Results y Conclusion y Future Scope
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y Digital
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QPSK Modulator
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Data
BPSK
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Constellation
Q - Signal
0 bit = 90 o
01 bit =135 o
00 bit = 45 o
+
Q data
I - Signal
Cos
6
ct
10 bit = 315 o
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Phasor Diagram
Q - Signal
+cos
ct
cos
ct
sin
ct
+ cos
ct
45
sin (
ct
+ 135 )
sin (
ct
+ 45 )
-cos
ct
sin
ct
- cos
ct
ct
135 I - Signal
= sin ( 1 0 - sin
ct
+ 135)
ct
cos
ct
- sin = sin (
ct
+ cos
ct
315
-sin
ct
+sin
ct
- 45 )
- sin
ct
-cos
ct
- sin = sin (
ct
- cos
ct
225
sin (
ct
ct
- 135 )
- 135 ) -cos
ct
sin (
ct
- 45 )
QPSK Modulator
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QPSK Modulator
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y Matlab Simulation y Simulation on Xilinx FPGA y Implementation on Virtex 4 y Testing and Debugging
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Upsampling
Multiplier
90o
Carrier
10 QPSK Modulator 22 June 2011
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So that receiver samples at intervals of Tb , where Tb is the bit period . y At the sampling instant , the tails from all preceding pulses have zero values
y
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Upsampling
Shaping
Multiplier Adder
Q data
Unipolar to Bipolar
Upsampling
Shaping
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Bandwidth
Carrier Frequency c = 25 MHz Data Frequency d = 25 MHz Roll off Factor = 0.3
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y ?n A ! bk x?n k A
k !0
multiplications and additions. y FPGAs can be used to implement DSP system as they provide tremendous computational power by using highly parallel architecture for high performance. y FPGAs dedicated for DSP has Embedded multipliers and distributed RAM for storage of coefficients.
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of configuration logic blocks and programmable interconnect structures. y Programming of the interconnect structure is accomplished by RAM cells whose o/p terminals are connected to the gates of MOS pass transistor
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family applications
is
focused
for
DSP
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y The Integrated Software Environment (ISE) is the Xilinx design software suite
that allows taking design from design entry through Xilinx device programming.
Design Entry
Synthesis
Implementation
Verification
Device Configuration
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Q data
Unipolar to bipolar
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Results
QPSK Spectrum :
Simulated Implemented
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Results
Hardware Setup :
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Conclusion
QPSK modulator has been successfully implemented on the Xilinx Virtex 4 Development kit. QPSK Modulator is simulated in Matlab Software to verify and compare its functionality taking into account the limitations imposed by the hardware The modulator algorithm has been implemented on FPGA using the VHSIC hardware description language (VHDL) on Xilinx ISE 8.2i. Simulated waveform is compared with actual output on the digital oscilloscope and spectrum analyzer. The designed modulator may be used as a test bed for the functional verification of various RF subsystems which requires to be parameterized under modulated signal conditions
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Future Scope
The hardware module can be functionally extended to the following to support a variety of applications:
y QPSK Demodulator y Multi Carrier QPSK Modulator y Higher Order Digital Modulator and Demodulator
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References
y Modern Digital and Analog Communication Systems By B.P. LATHI y Satellite Communication ByWilliam Pratt y Contemporary Communication Systems using Matlab By John G. Proakis y VHDL Primer By J.Bhasker y Digital Systems Design withVHDL and Synthesis By K.C.Chang y User Guide of Xilinx ISE y Datasheet ofVirtex - 4 y Datasheet of P240 Prototype Module
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Thanks