Transaction Level Modeling Definitions and Approximations

Trevor Meyerowitz EE290A Presentation May 12, 2005

Outline
Motivation Recent Definitions

SystemC

Definitions SpecC Definitions Other Defintions

Classifying Models of Microprocessor Microarchitectures

Motivating Trends

Greg Spirakis 2003 EMSOFT Keynote

Software is 80% of embedded system development cost more advanced research needed

Moores Law (Source: Intel)

Increase simulation speed of HLM for architectural exploration and HW/SW codesign

Gartner Dataquest forecasts 20% growth in Semiconductor IP Market in 2004 (~$1 Billion)

The Design Productivity Gap (Source: 1999 ITRS Roadmap)

Motivations for Higher Level Models

Architecture Exploration Speed of Development Simulation and Verification Speed Early Software Development Reusability

Basic Levels of Abstraction

Communication: Shared Variables Method Calls to Channels Wires and Registers Languages:

Algorithmic Models Transaction-Level Models Register Transfer Level Models Logic Gates Actual Gates Layout

C/C++, Matlab

SystemC, SpecC, Metropolis Verilog, VHDL

SystemC Definitions
Communicating Processes Programmers View Cycle-Accurate Models RTL Models

Adam Donlin, Transaction Level Modeling: Flows and Use Models, CODES04

Concurrent Processes
VLD
FIFO

Explicit Concurrency

Easier to handle than extracting from a sequential source Well suited for hardware modeling

Communicating via channels

DCT
FIFO

Point to Point Communication Method calls instead of signals Abstracts away the protocols

Untimed or Timed

IQNT

Programmers View
CPU
Master

ASIC
Master

Resembles the architecture

Bus Arb
Slave

Register Accurate Useful for SW Development and Prototyping

Bus
Slave

Shared Communication

Potential Arbitration Blocking vs. Non-blocking

Periph.

Mem

Timed or Untimed

SpecC Transaction Level Modeling

Its higher than RTL-level, but Cai and Gajski define it as:
Explicit Separation of Communication and Computation Three levels: Untimed, Approximate, Cycle-Accurate Its a start, but is still vague

We expand upon this in the domain of microprocessors and their use in system level environments

(Copyright 2003 Dan Gajski and Lukai Cai)

System Modeling Graph

Cai, L. and Gajski, D. "Transaction Level Modeling: An Overview," Proceedings of the International Conference on Hardware/Software Codesign & System Synthesis, Newport Beach, CA, October 2003.

Other Definitions

OCP-TLM Levels of Abstraction Calypto Sequential Equivalence UC Irvine CCATB

Clock

Cycle Accurate at Transaction Boundaries

Metropolis

Levels of Processor Modeling

Speed
Native Execution (Untimed) ISS (Instruction Set Simulator)

What about approximate models?

CAS (Cycle-Accurate Simulator) RTL (Signal Level)

Accuracy

Levels of Processor Modeling

Speed
1x native execution (untimed) ISS (instruction set simulator) faster, but still accurate timing annotation

1/20x

1/100x

CAS (cycle accurate simulator) RTL (signal level)

1/10000x

Accuracy

The Problem Space

Performance Exploration and Estimation of Processor Microarchitectures in System-Level Environment AppS - Application Space input data and instruction execution trace CompS - Microarchitectural Computation and State CommS - Microarchitectural Communication and State Execution Trace Definition
ExecTrace : AppS CommS CompS AppTrace AppTrace = { (fetch(i), commit(i), i) | instructions i AppS }

Means of Exploration
Approximation Abstraction Microarchitectural Features

Metrics
Quantitative: Speed, Accuracy, Power, etc. Qualititative: Flexibility, Ease of Use, etc.

Communication

Application

Computation

Microarchitectural Communication Space

Ideal Channels Pipelined Channels Non-Pipelined Channels Pipelined Bus Non-Pipelined Bus Ideal Memory

Performance

Caches + Buffers Caches Buffers

Cost

Non-Ideal Memory (no Caches or Buffers)

Bus/Channels Hierarchy

Memory Hierarchy
Communication

Application

Computation

Microarchitectural Computation Space

Elements
Resources
Latencies, Throughput, etc.
Can Increase or Decrease Performance Based on the Communication System

Speculation Buffers

Abstractions and Approximations

Instruction Level Models Simplified Microarchitectural Models
Communication

Application

Computation

Our Flow
Application
Potential Use: (for a given application)
1. Determine a processors instruction set 2. Explore the processors microarchitecture 3. Annotate performance back to the original application Compiler

Instruction Set Simulator

Instruction Trace

Timing Annotated Application

Produces Timing Numbers Fast & Accurate!

o f my ocus F Work

Microarchitecture Model
Execution Results

Performance Characterization

Final Words

Transaction-Level Modeling is an important idea in that its higher than RTL, but the term means different things to different people (still) Many Open Questions Remain
How

can the different levels of abstraction be related to one another? IP interchange standards and methodologies Can we go from algorithms to rtl and still get good results?

References
[CCATB] S. Pasricha, N. Dutt, and M. Ben-Romdhane, Extending the Transaction Level Modeling Approach for Fast Communication Architecture Exploration., DAC, June 2004. [OCP] Open Core Protocol Web Site: www.ocpip.org [SPECC] Cai, L. and Gajski, D. "Transaction Level Modeling: An Overview,, ISSSCODES03. [SYSTEMC] Grotker, T., Liao, S., Martin, G., Swan, S. System Design with SystemC, Kluwer Academic, 2002. [SYSC-TLM] Donlin, A. Transaction Level Modeling: Flows and Use Models, ISSSCODES04