M-RAM

Ashutosh Ranjan Roll No - 010

Memory Category

Volatile Memory Comparison

The primary difference between different memory types is the bit cell.

SRAM Cell
Larger cell lower density, higher cost/bit Read non-destructive No refresh required Simple read faster access

word lin

bit line

bit line

DRAM Cell
Smaller cell higher density, lower cost/bit Needs periodic refresh, and refresh after read Complex read longer access time

word line

bit line

Limitation of Flash Memory

The main weakness of flash memory is the number of times that data can be written to it. Data can be read from flash as many times as desired, but after a certain number of "write" operations, it will fail. Most flash devices are designed for about 100,000 - 1,000,000 write operations (or "write cycles"). The erase command takes much longer than the write process; and, for manufacturing reasons, flash memory chips are not made with the ability to erase individual bits or bytes. Only large sections of memory (usually 512 bytes or more) can be erased at a time.

MRAM Introduction
It is a non-volatile, random access memory technology that is designed to initially replace flash memory and, potentially, DRAM memory. MRAM uses magnetic, thin film elements on a silicon substrate that can be built on the same chip with the logic circuits.

The MRAM product, called MR2A16A .

MRAM - The Universal Memory

MRAM is a revolutionary, non-volatile memory chip with potential to replace all other forms of semiconductor memories Allows single memory solution for multiple memory options within one chip - enabling faster, lower power, less expensive solutions for nextgeneration wireless and portable products MRAM offers solution to technology shortcomings such as slow computer or cell phone startup, data loss, long waits for data to load and short battery life

Information flux.
Information Input Information transmission Information Processing Information storage

Outside

word

Output

DRAM, MRAM

Magnetic (HDD) Optical (CD, DVD)

MRAM Advantages
Nonvolatile Fast Unlimited Cycles Viable Data Retention 10 years Symmetrical Read/Write
25-35ns for 4Mb at 0.18um technology node

Endurance (>1016 )
Data stored by magnetic polarization

Integrated with Existing CMOS Baseline Compatible with Embedded Designs 4Mb Memory Device sampled

History and development...

M-RAM based on:

M-RAM quick view. Magnetoresistivity. GMR effect - 1980th.

TMR effect 1995 year.

 1989 - IBM scientists made a string of key discoveries about the "giant magnetoresistive effect" in thin-film structures. 2000 - IBM and Infineon established a joint MRAM development program. 2003 - A 128 kbit MRAM chip was introduced 2004 -Renesas Technology Develops High-Speed, HighReliability MRAM Technology. 2005 - Renesas Technology and Grandis to Collaborate on Development of 65 nm MRAM Employing Spin Torque Transfer.

Behavior of a ferromagnet in a magnetic field

H

Ms M
N S

H M

Ms
N S

H
S N S N

Linear response Sensor !!

Hysteresis Memory !!

Magnetic LEGO and Magnetoresistance

Stack of ferromagnetic thin layers separated by non-magnetic layers

Resistance can be used to determine the magnetic state of stack

FM FM

Normal metal (Cu, Au)

Insulator (Al2O3)

Giant magnetoresistance (GMR)

Ferromagnetic thin films (Co, NiFe) separated by thin nonmagnetic metal spacers (Cu, Au)

Resistance depends on magnetic field RAP >> RP

spin-valve multilayer granular system

Two current model of GMR

Parallel state Low resistance Anti-parallel state High resistance

Spin-down Spin-up

x
Co Cu

Spin-down

x x
Co
a RMj

x
Co

Spin-up

Cu

Co

Spin-down Spin-up

Mj a

Mj a

Rmin

Spin-down Spin-up

Rmin

Rmin

Rmin

a RMj

( -1)2 GMR = 4

a = Rmin /RMj

Tunnel magnetoresistance (TMR)

Ferromagnet 1 Ferromagnet 2 AFM

Large effects at RT first observed by Moodera et al. PRL 74, 3273 (1995)

Ultrathin insulator Al2O3 ~ 1.0 nm

State-of-theart: TMR of up to 70% at 300 K

Storage and states of a bit.

Storage state:
MRAM: charge and spin.
Soft ferromagnet

[%] TMR

Insulator DRAM: charge of capacitor. 1 Flash, EEPROM: charge on floating gate. Hard ferromagnet FeRAM: charge of a ferroelectric capacitor.

0
Field [Oe]

Magnetic Random Access Memory (MRAM)

Cross point architecture

Magnetic memory element High resistance Low resistance

Integration of MRAM (pizza style)

toppin g

integration
Si circuitry

crust

Writing a bit in MRAM

Send current through metal word and bit lines. This creates a local magnetic field to switch a memory cell at the cross point

Reading a bit in MRAM

- Send current through element - Measure its resistance (high or low) But many parallel current paths diode or transistor needed

Reading a bit in MRAM

Select one element in array using isolation transistor

p.s. Resistance matching needed !

- Send current through a single element - Measure its resistance (high or low)

How MRAM Works

Information is stored as magnetic polarization, not charge The state of the bit is detected as a change in resistance
S S N N

Magnetic layer 1 (free layer) barrier Tunnel

N S

S N

Magnetic layer 2 (fixed layer) Magnetic vectors are Magnetic vectors are antiparallel parallel high resistance. 1 low resistance. 0

 MRAM normally functions by constructing minuscule magnetic fields at intersections in a grid of nanoscopic power rails. When current attempts to travel through a power rail which is opposing the polarization of one of the magnetic field bits, its current flow is mitigated and the bit value stored by the field is detected by this weakened current flow.

MRAM Cell
Magnetoresistive random access memory (MRAM) uses the magnetic tunnel junction (MTJ) to store information MRAM cell composed of a diode and an Bit Line MTJ stack MTJ stack consists of two ferromagnetic layers separated by a thin dielectric barrier Polarization of one layer fixed, other used Read/Write Current for information storage

Diode

MTJ Stack

Pt Co/F Ni/F e Al2O e Co/F Ni/F 3 e Mn/ e Pt Fe W

Word Line

1 T-1 MTJ MRAM memory cell operation - read Read Mode ISense

To read an MRAM bit, current is passed through the bit and the resistance of the bit is sensed.

Isolation Transistor ON

1 T-1 MTJ MRAM memory cell operation - write Write Mode

Easy Axis Field

IEasy

Free Layer Tunnel Barrier Fixed Layer

Hard Axis Field

To write an MRAM bit, current is passed through the programming lines generating magnetic fields. The sum of the magnetic field from both lines is needed to program the bit. No moving parts.

Isolation Transistor OFF

IHard

Other MRAM cell architectures.

Twin cell arrays:

Circuit is faster than the 1T1TMR implementation. on a cell density and cost Less atractive basis. Diode cell: SOI diodes allow the integration of a memory with most circuits without sacrificing silicon wafer surface area. for this aplication havent been SOI diodes suitable developed yet.
Transistorless array:

Large reduce in cell area. Complex circuity required to read bit state, slow read.

4Mb Memory Cell

M5-BL TE i TJ MVia TVia i BE

Program path for Writing informationM3

M2 Thk Oxide Xtor
N+ N+

V4

M4-DL V3 V2 V1 M1
N+ P-

Pass Xtor

Pass Xtor

Group Select

Sense Path for bit cell reading

N+

N+

N+

N+

Layer Name M1-3 Via1-4

M4-DL MVia

BE

TJ

TVia

TE

M5-BL

MRAM 32Kb memory segment.

Bit line 0 Bit line 31
Digit line Word line Word line Digit line

MRAM Reference Circuit

Bit Line

Rmax

Rmin

Word Line Word Line

common source

Rmax

Rmin

Rref = 1/2 * (Rmin + Rmax) Reference Cell Reference Cell uses Parallel/Serial combination of MTJs in two memory states to generate mid resistance reference between those two states

Implementation of 1-MTJ / 1-transistor cell.

NiFe (free layer)
Al2O3 (tunneling barrier)

CoFe (fixed layer) Ru

SAF

CoFe (pinned layer) Word line

I I H clad == = 2 H clad H unclad 2 w w

Toggle Bit Technology

Full MTJ Stack for MRAM

Full MTJ Stack for MRAM

Top electrode Free AlOx Fixed Ru Pinned AF pinning layer Template Seed Base electrode

Low resistance contact Switches between two magnetic states in applied field. Stores information. Tunnel barrier. Affects resistance and MR ratio. Synthetic Antiferromagnet (SAF). AF coupling through Ru layer makes the structure stable in applied magnetic fields. Relative thickness of Fixed and Pinned used to center loop. Pins the bottom magnetic layers. Seeds growth, determines crystal structure Low resistance contact

Toggle MRAM Bit Cell

Bit Line BL Program Line Program Line 2

Free Tri-Layer Tunnel Barrier Pinned Ferromagnetic Pinning Layer

DL Program Program Line 1 Line

Ferromagnetic layer Coupling Layer Ferromagnetic layer

Elements of Toggle Bit

Balanced SAF freelayer Bit oriented 45 to lines Unipolar currents Overlapping pulse sequence Pre-read / decision write
Hard Axis Easy Axis

Write Line 1 (H1)

Write Line 2 (H2)

Toggle MRAM Switching Sequence

H2 Hard Axis Easy Axis Hard Axis H1 I1 Easy Axis Hard Axis H1 I1 I2 Easy Hard Axis Axis H2 I2 Easy Axis Hard Axis Easy Axis

Write Line 1 Write Line 2

Write Line 1 Write Line 2

Write Line 1 Write Line 2

Write Line 1 Write Line 2

Write Line 1 Write Line 2

On Off On Off

Write Line 1 Write Line 2 t0 t1 t2 t3 t4

Sample Application Battery Backed SRAM Replacement Built-in-house Components

Problems
Addr/Data Bus

SRAM

MCU
CE Control Chip Battery

System design complexity Board space and weight Battery life Manufacturing complexity Environmental concerns

Addr/Data Bus

MCU

MRAM Solutions
Single chip solution Simple, low cost system design Manufacturing simplification No battery Unlimited life Smaller profile Higher performance Environmentally friendly

Problems
MCU
Addr/Data Bus

Battery SRAM

Cost Manufacturing complexity Battery life Low performance Environmental concerns

Off-the-shelf components

Target Application Battery Backed SRAM Replacement

Primary Usage
System Design Complexity More Parts & Labor & Board Space & Weight

Data Logging Parameter Storage System Status Storage Buffers

Battery Contact Failure Out-of-Tolerance Voltage Spikes Limited Life

Manufacturing Complexity

Target Application Spaces

Data Streaming

MR2A16A Application Spaces

RAID systems and servers POS terminals Data-acquisition systems Data logging Buffers Currently not targeting high density, space-constrained applications Routers / switches Portable digital audio players Jump drives Printers / copiers Digital camera data storage

System Configuration
Black-box applications Gaming System status

MRAM parameters

Major limitations of MRAM:

Although MRAM has many advantages over virtually every existing memory type, it is still in its infancy. Many had hoped MRAM would usher in the age of instant-on computers able to replace the computer main memory and hard drives, but, due mainly to its cost, these hopes remain a dream. At $25 per 0.5 MB, MRAM has no chance of competing with existing RAM selling for $25 per 256 MB, not to mention Flash, which sells for $25 per 1 GB. The only place where MRAM might be widely utilized is in specialized markets, for example, as a Battery-Backed SRAM replacement. Only when it breaks its current high price per MB ratio will MRAM's unique qualities find widespread usage.

Roadmap to future storage technologies.

RRAM with CMR

Bio MRAM, vision for tomorrow?

MRAM array Biomolecule labeled by magnetic markers

MRAM Roadmap ?

Honeywell GMR-MRAM limited performance

4
0.256

Motorola tunnel MRAM demos

Conclusion
Non Volatile No need to refresh (potentially) High density Non destructive read Read speed = write speed; < 50ns Unlimited R/W endurance Soft error immunity

Thank you