Computer Organization and Architecture

Computer Architecture and Arithmetic -- Mr. Hulle N. B.

Syllabus
Unit I: Computer Architecture and Arithmetic (7 Hours)

Computer Architecture, Von Neumann Architecture, Functional Units, Basic Operational Concepts, Performance, Processor organization, Bus Structure, Register Organization, Instructions and Instruction Sequencing, Addressing Modes. Arithmetic: Multiplication of positive numbers, Signed Operand Multiplication, Booths Algorithm, Fast multiplication, Integer Division, Floating point Numbers and Operations, IEEE standards, Floating point arithmetic.

Syllabus
Unit II: The Central Processing Unit (7 Hours)

Basic Processing Unit: Single Bus Organization, Register Transfer, Performing an arithmetic or logic operation, Fetching and storing word from/to memory, Execution of complete instruction, branch instruction, Multi-bus Organization. Hardwired Control: Design methods State table and classical method, A complete Processor, Microprogrammed Control: Microinstructions, micro- program sequencing, wide branch addressing, microinstructions with next address field, perfecting microinstructions, emulation.

Syllabus
Unit III: Input-Output and Memory Organization (7 Hours)

I/O Organization: Accessing I/O devices, Interrupts: Interrupt Hardware, enabling and disabling interrupts, handling multiple requests, Controlling devices, exceptions, Interface circuits, Standard I/O Interfaces: PCI, SCSI, USB. The Memory System: Memory Hierarchy, Internal organization of memory chips, Cache memory, Performance Considerations, Virtual Memories

Syllabus
Unit IV: Introduction to 16 bit microprocessor (7 Hours)

The 8086 microprocessor, architecture of 8086, pin diagram, programming model of 8086. Logical to physical addressing, addressing modes, Instruction set, interrupt structure, 8086 Assembly language programming.

Syllabus
Unit V: Introduction to 32 bit microprocessor (7 Hours)

The 80386 microprocessor, Features and Architecture, Pin Description, Functional Description, Register Set. Programming model of 80386: real mode, protected mode and virtual mode, paging and segmentation, Multitasking, Interrupts, Exceptions and I/O

Syllabus
Unit VI: Parallel Architectures and ARM (7 Hours)

Parallel architectures, classification, Instruction level pipelining and Superscalar Processors, The structure of general purpose multiprocessor, Multiple Processor Organizations, Closely and loosely coupled multiprocessors systems. Advanced RISC Machines (ARM): Introduction to RISC, Instruction execution, characteristics, RISC architecture and pipelining, RISC Vs CISC.

ENIAC (Electronic Numerical Integrator and Computer)

Brief History: From ENIAC (Electronic Numerical Integrator and Computer) John Mauchly and John P Eckert, University of Pennsylvania (1943 - 1946) For war purposes, ballistic trajectory Weighted 30 tons, consumes 140 kwatts of electric power, 15,000 square feet of space, only 5000 addition per second Not a digital computer, it was a decimal computer (analog)

ENIAC

ENIAC

ENIAC - details Decimal (not binary) 20 accumulators of 10 digits Programmed manually by switches 18,000 vacuum tubes 30 tons 15,000 square feet 140 kW power consumption 5,000 additions per second

Von Neuman Architecture / EDVAC / IAS

John von Neuman proposed : EDVAC (Electronic Discrete Variable Computer) - first stored program computer -1945 1946 Von Neuman and his gang proposed IAS (Institute for Advanced Studies) The design included : main memory ALU Control Unit I/O First Stored Program, able to perform : +, -, x, / The father of all modern computer/processor

Von Neuman Architecture / EDVAC / IAS

Von Neuman Architecture / EDVAC / IAS

Structure of von Neumann machine (IAS)

von Neumann Stored Program concept Main memory storing programs and data ALU operating on binary data Control unit interpreting instructions from memory and executing Input and output equipment operated by control unit Princeton Institute for Advanced Studies
IAS

Completed 1952 Used the term organ to describe devices

View of a Computer System

COMPUTER TYPES
Classification #1:  Micro Computers  Mini Computers  Mainframes  Super Computers Classification #2:  Analog Computers  Digital Computers  Hybrid Computers More General Classification:  General Purpose Computers  Special Purpose Computers

Computer Types
Thus todays computer types and classification is based purely on their mode of usage & portability. (From the view point of an average end user)

o DeskTop PC o LapTop PC o PalmTop PC o Workstations

Interconnections
 The computer types based on their interconnection usage, sharing

of resources, multi-user, multiprocessors, remote access like operating environments - includes Distributed Computers Parallel Computers
 These two categories encompass:

Enterprise Systems or Mainframes Servers Super Computers

DeskTop PCs
 As its name suggest desktop PC contains CPU box, display unit, keyboard, including speaker and a mouse which can all be housed on an office desk or a home table in the form of 3-box structure in two models viz Table Top model and Tower model CPU cabinets. They are stand alone computer systems & found their fullest usage in homes, schools, colleges, banks, offices.

LapTop PCs
 Powerful slim mobile PCs which are compact form of personal computers and intended to replace the heavy desktop PCs  High-resolution graphics i.e. LCD display, their weighing range between 2 to 2.5Kgs., optical drive for CD-ROMs, DVDs and compact hard drives while retaining good-sized keyboard.  All its units are housed in a single thin, tiny briefcase like structure.

PalmTop PCs
 All kinds of hand held computers including Pocket PC, Tablet PCs, Mobile electronic gadgets, PDAs, e-books, Notepads, Mobile phones with internet Browsing facilities fall in this category.  Limited Battery Powered, Rechargeable, tiny toy like consumer electronic devices the palm top PC. Touch and feel are more crucial here while operating with limited storage and computational power.

Workstations
 Workstations are industry standard desktop computers with more computational power and high-resolution graphic display with variety of graphic input/output capability.  Workstation PCs are usually employed in the applications of Computer Aided Design and Drafting (CADD). Simulation & Modeling, Interactive Graphic design, Multimedia and other engineering applications.

Enterprise Systems or Mainframes

 Enterprise systems or mainframes are like a family of computers with tremendous computing power beyond workstations. Their computational activities are distributed among one main system (usually a server) and number of child nodes or intelligent PCs with or without local computing power / processor (usually client computers) called dumb terminals.  Mainframes are preferred at business data processing corporate offices. They are quite expensive with several hard disks, RAIDs and backup storage units.

Servers
 A server computer is a derivative of either Mainframe or Workstation PC. It can be a powerful desktop PC interconnected in a LAN as Server.  Many corporate offices are replacing their enterprise systems with simple and affordable Local Area Network (LAN) of Desktop PCs. Where in there is a Single Server PC and a few Client PCs, all are interconnected !  Examples of Servers: File Server, Database Server, Print Server, Message Server /mail server, Web Server,

Super Computers
 One of the fastest computers type currently available, They are problem scalable.  Computational speed of a super computer is measured interms of Floating Point Operations Per Second or FLOPS.  Examples: Cray X/MP-14 , Param 8000, Param - Padma

FUNCTIONAL UNITS
A computer in its simplest form comprises five functional units: 1) Input Unit 2) Output Unit 3) Memory Unit 4) Arithmetic & Logic Unit 5) Control Unit
Processor or CPU

I /O

Functional Units

Input Unit
 Computer accepts encoded information through input unit. The standard input device is a keyboard of a video monitor or terminal.  Whenever a key is pressed, keyboard controller sends the scanned code of that letter, digit or symbol to CPU/Memory. Examples include Mouse, Joystick, Trackerball, Lightpen, Tablet or Digitizer, Scanner etc.

Memory Unit
 Memory unit stores the program instructions, data operands on and results of computations etc. Memory unit is classified as:

1. Primary /Main Memory 2. Secondary /Auxiliary Memory 1. Primary memory is a semiconductor memory that provides access at electronic speed. Run time program instructions and operands are stored in the main memory. It contains a large number of semiconductor storage cells.

Memory Unit
 Main memory is classified again as RAM and ROM.  RAM is termed as Read/Write memory or user memory that holds run time program instruction and data.  ROM holds system programs and firmware routines such as BIOS, POST, I/O Drivers that are essential to manage the hardware of a computer.

RAM

ROM

Memory Unit
2. Secondary /Auxiliary Memory:
 While primary storage is essential, it is volatile in nature (i.e. its contents will be lost in the absence of power) and expensive too. Additional requirement of memory would be supplied as auxiliary memory at cheaper cost.  Secondary memory are magnetic memories viz Floppy disk, Hard disk, Magnetic tape, CD-ROM etc.  Secondary memories are non volatile in nature (contents will not be lost in the absence of power).

Arithmetic & Logic Unit

 ALU performs all arithmetic & logical operations of the processor. Like addition, subtraction, division, multiplication, AND, OR, etc. The operands are brought into the ALU from memory and stored in high speed storage elements called register. Then according to the instructions the operation is performed in the required sequence.

Output Unit
 Computer returns the computed results, error messages, etc., via output unit.  The standard output device is a video monitor, LCD/TFT monitor.

Other output devices are printers, plotters to take a paper copy of the results, programs, graphs called print out or a hardcopy  Printers types: Dot Matrix printer, Inkjet printer, Laser printer. . .

Control Unit
 Control unit co-ordinates activities of all units by issuing

timing control signals like MEMR, MEMW, IOR, IOW.

 Timing control signals hence issued by control unit

govern the data transfers as to when the appropriate operation must take place. Control unit interprets or decides the operation/action to be performed.

Basic Operational Concepts Main conceptual events/operations of a computer

1. A set of instructions which perform a given task, called a program must reside in the main memory of computer during its execution. 2. The CPU fetches those instructions sequentially one-by-one from the main memory, decodes them and perform the specified operation on associated data operands in ALU. 3. Processed data i.e. useful information will be displayed on an output unit. 4. All activities pertaining to processing and data movement inside the computer machine are governed by control unit.

Basic Operational Concepts

An Instruction consists of two parts: An Operation code and operand/s OPCODE OPERAND/S Instruction ADD MLOC, R0 Execution steps: To add two operands Step 1: Fetch the instruction from main memory into the processor Step 2: Fetch the operand at location MLOC from main memory into the processor Step 3: Add the memory operand (i.e. fetched contents of MLOC) to the contents of register R0 Step 4: Store the resulting sum in R0 itself.

Processor and Main Memory Interaction

The figure depicts processor and memory connection w.r.t. various components of a processor. Address Bus MAR PC IR CACHE MAIN MEMORY Data Bus MDR R0(Accum) R1 Rn-1 G P Rs Control Bus CONTROL UNIT

ALU

0 1 FLAGS 15

CPU

Operational Steps Associated with Processor & Main Memory Interaction

Consider the following figure: MAIN MEMORY MAR Address of an Instruction PC MDR O Instruction P C O D IR E Data Operand

Control

ALU

Performance
The total time required to execute an application program is the most important measure of performance for a computer.  Performance is also affected by features like the compiler design, machine language instruction set of the computer, the hardware design of that computer For a best performance, there must be co-ordination among

Compiler Design

Instruction Set

Computer Hardware.

Performance
1. To increase speed of processing, a high-speed memory called a cache memory is used to contain run time programs and frequently accessed data values. MAIN MEMORY CACHE MEMORY PROCESSOR

3. The cache memory is employed in computer systems to overcome the mismatch in operating speeds of processor and main memory (slower access time).

Processor Clock
 The performance of a processor and hence operating speed of a todays desktop PCs and workstation computers is usually specified as Clock rate viz Intel Celeraton processor @850 MHz (Mega Hertz), Intel Pentium PIV processor @ 2.4GHz (Giga Hertz) and so on.. The term cycles per second used to measure clock rate is termed as Hertz (Hz). The Clock rate R can be given as R=1/P which is similar to f=1/T where in P or T is length or duration of timing signal called clock period or simply clock cycle The duration T or length P of one clock cycle plays a key role in determining processor performance. The inverse of P or T is the clock rate R or f which is measured in cycles per second (frequency or clock frequency)

Processor Clock
In general, processor circuits in a PC are controlled by clock generator IC (say 8284) which is coupled with a crystal (Crystal Oscillator Circuit). This clock generator defines uniform time intervals called clock period or T-states. In order to execute a machine language instruction, usually 4 to 6 T-states or clock cycles are required Usually 1 T-state or clock period refers to 1 micro second duration , 1 nano second, etc. depending upon the processors clock rate.

Basic Performance Equation

 Let  T = Time required by the processor to execute a high level language program.  N = Language translator might issue the number of machine language instructions to execute the given source program.  S = Average number of basic states of actions (called micro operation / micro instructions) required to execute one machine language instruction.  R= Clock rate for a given processor in cycles per second, then total execution time for a given source program is: T=(N*S)/R  This is referred to as Basic Performance Equation. The execution time T has to be minimized for better performance. For which values of N and S must be minimized and value of R must be enhanced at the same time.

Clock Rate
 How do you enhance the clock rate R for a processor ?

Clock frequency of a processor can be improved in a straight forward manner i.e. if and only if processors semiconductor (IC) fabrication technology incorporates very high speed logic circuits. This gives a better performance ratio by reducing clock period P for completing basic steps of actions and thus increasing the clock rate R.
 The other way to improve clock rate R is to minimize the amount of work done in each and every basic step of action (micro instructions operation). This will reduce clock period P and enhances R the clock rate.

Performance Measurement
 It is the time a computer require to execute a given benchmark program. Benchmark refers to standard task used to measure how well a device or computer or processor operates. To evaluate the performance of Computers, a non-profit organization known as SPEC-System Performance Evaluation Corporation employs agreed-upon application programs of real world for benchmarks. Accordingly, it gives performance measure for a computer as

Running time on a Reference Computer SPEC Rating = Running time on a test Computer

Performance Measurement

 A benchmark program from a suite of benchmark program will be selected and compiled for test computer.  The same benchmark program will be compiled and executed on one of the typical computer which be selected as a Reference Computer  For instance, a SPEC rating 20 indicate that a test computer is 20 times faster than the chosen reference computer for a particular benchmark program.

Processor Organization

Processor Organization
IAS components are :
MDR or MBR (memory data register or memory buffer register), MAR (memory address register), IR (instruction register), IBR (instruction buffer register), PC (program counter), AC (accumulator and MQ (multiplier quotient), memory (1000 locations) 20 bit instruction : 8 bit op-code, 12 bit address (addressing one of 1000 memory locations - 0 to 999) 39 bit data (with sign bit - 1 bit) Operations : data transfer between registers and ALU, unconditional branch, conditional branch, arithmetic, address modify

Processor Organization

Consider a basic instruction of a CPU : ADD R1, R2

(Add content of register R1 and content of register R2, place result in R1)

Execution steps of

ADD R1, R2

The possible micro-execution steps are : a. b. c. d. ALU1 n [R1] ALU2 n [R2] ADD R1 n [ALU3]
{content of R1 is moved to ALU1} {content of R2 is moved to ALU2} {content of ALU1 + ALU2 = ALU3} {Result of add is moved to R1}

If each micro-step is executed in one clockcycle, then this ADD instruction needs 4 clockcycles

Processor Organization
Control Unit To/from memory

IR PC MAR MBR R1

R2 ALU1 ALU2 R3 ADDER

ALU3 BUS

First Clock cycle ALU1 [R1]

Processor Organization
Control Unit To/from memory

IR PC MAR MBR R1

R2 ALU1 ALU2 R3 ADDER

Second Clock cycle

ALU3

ALU2
BUS

[R2]

Processor Organization
Control Unit To/from memory

IR PC MAR MBR R1

R2 ALU1 ALU2 R3 ADDER

Third Clock cycle

ALU3

ADD
BUS

Processor Organization
Control Unit To/from memory

IR PC MAR MBR R1

R2 ALU1 ALU2 R3 ADDER

Clock cycle Four

ALU3

R1
BUS

[ALU3]

Analysis of Instruction Cycle

With single bus, it is slow, since in each clock only one transfer could be executed Is there any other way to improve the speed? Dual bus processor may be faster Additional processor cost

Dual processor-bus : A way to improve speed 1. ALU1 n [R1] (bus1) ALU2 n [R2] (bus2) 1 2
Other components (Control Unit, IR,PC, MAR,MBR)

2. ADD R1 3. R1 n [ALU3] (bus1) Only 3 clocks cycles needed, 25% faster

R2 ALU1 ALU2 R3 ADDER

Any other possibility

1. ALU1 n [R1] (bus1) ALU2 n [R2] (bus2) ADD 2. R1 n [ALU3] (bus1)

ALU3 DUAL BUS

Only 2 clocks cycles needed, 50% faster

What is Bus?........ A bus is a collection of wires that connects different parts of a computer in an organized manner for the purpose of communicating information such as memory address, I/O address, Data, Control bits etc.
With the bus structure, speed of operation can be achieved since collection of wires in a bus permits for transferring all bits of information at a time i.e., in parallel. One byte or one full word at a time simultaneously on different wires.

 To provide synchronization and to compensate for different speeds

of data transfer on a bus, slow speed peripheral devices are equipped with a buffer register.
 A buffer register holds data temporarily. Buffer register

compensate the timing differences among processor, memory and slow speed peripherals like Printer, Key-board, magnetic tape etc., during the transfers over a common communication path i.e., single bus.

Example Register Organization

Registers CPU must have some working space (temporary storage) Called registers Number and function vary between processor designs One of the major design decisions Top level of memory hierarchy

User Visible Registers General Purpose Data Address Condition Codes

General Purpose Registers (1)

May be true general purpose May be restricted May be used for data or addressing Data
Accumulator

Addressing
Segment

General Purpose Registers (2)

Make them general purpose
Increase flexibility and programmer options Increase instruction size & complexity

Make them specialized

Smaller (faster) instructions Less flexibility

How Many GP Registers? Between 8 - 32 Fewer = more memory references More does not reduce memory references and takes up processor real estate See also RISC

How big? Large enough to hold full address Large enough to hold full word Often possible to combine two data registers
C programming double int a; long int a;

Condition Code Registers Sets of individual bits

e.g. result of last operation was zero

Can be read (implicitly) by programs

e.g. Jump if zero

Can not (usually) be set by programs

Control & Status Registers Program Counter Instruction Decoding Register Memory Address Register Memory Buffer Register

Program Status Word A set of bits Includes Condition Codes Sign of last result Zero Carry Equal Overflow Interrupt enable/disable Supervisor

Instruction and Instruction Sequencing

 An instruction is a command to the processor to perform a given task on data operands.  A program is a set of instructions that specify operations, operands & the sequence by which processing has to occur.  Thus operation of a computer is controlled by stored program  In general a computer must support 4 categories of operations: 1. Data Movement : To conduct I/O transfers 2. Data Storage : Across Memory and processor registers. 3. Data Processing : Arithmetic and logical operations 4. Program sequencing and control : Test and Branch.

Register Transfer Notation

 Data operands & Instructions are situated in main memory locations

& processor registers.

 Like mnemonics for Op-codes, Symbolic names or label identifiers

are used to name or identify such locations.

 For instances memory location names include M, LOC, A, B, C,

SUM, N1, VAR1, VAR2, NUM1, etc.,

 Similarly processor register names include R0, R1, R2, R3, R4, R5,

etc., and registers of I/O subsystem may be designated as DATAIN, DATAOUT etc.

Register Transfer Notation

 While depicting operations, the contents of a memory location or a register are denoted by placing the corresponding name in a pair of square brackets. R0 [M] For instance : Suggests to copy contents of memory location M to register R0  The corresponding instruction is  Similarly : MOVE R1, SUM
Register

MOVE M, R0,
Register

Memory Location

Suggests : SUM
Memory Location

[R1]

 The instruction : MOVE B, LOC

Means

: LOC [B]

Register Transfer Notation

 Similar operations that involve Registers only are:

R1 [R2]


MOVE R2, R1 ADD R3, R1

R1

[R1] + [R3]

Suggest to add contents of register R1 and register R3 and rewrite the R1 contents to store the sum.
 All such notations with leftward arrow ( ) assignment operations involving register locations give rise to what is known as Register Transfer Notation

Assembly Language Notation

 An assignment statement in a High Level Language Program: S= P+ Q  Here P, Q & S are variables.  Variable name refers to symbolic address of memory location from which data operand can be read or written. S [P] + [Q]  This operation suggests contents of two memory locations P and Q are fetched from memory and transferred into processor where sum of two numbers is performed. The resulting sum is then sent back to memory and stored in memory location S.  An instruction to this effect in Assembly Language Notation: Add P, Q, S

 Consider R1 [R1] + [R3]  Equivalent Assembly Language instruction is Add R3, R1.  Here the operation Code Mnemonic is Add  Register Locations R1, R3 represent operand fields  Similarly, in the instruction

ADD R1, SUM Memory Operand Register Operand

Opcode

 i.e.

SUM

[SUM] + [R1]

Basic Instruction Types

Three Address Instruction Two Address Instruction One Address Instruction Zero Address Instruction
 Three Address Instruction Suppose we would like to use a single machine instruction to perform the following addition operation: S [P] + [Q] We will have to use a three address instruction to carry out addition and to store the sum in a third variable S.  Then three address instruction to perform addition is: Add P, Q, S

General form of three address instruction

Two Address Instruction

 Two address instruction general format:

 Example of two address instruction  To perform operation of addition as :

Destination Operand

Add P, Q Q [P] + [Q]

Source Operand/s

Two Address Instruction

 Here one of the operand i.e. destination operand Q acts as source as well as destination.

 To perform

S [P] + [Q] MOVE Q, S ADD P, S

 Use two address instructions sequence:

One Address Instruction

 One address instruction format specify a single operand along with operation code.  The requirement of second operand is fulfilled by an implicit processor register known as Accumulator (AC).  Example of one-address instruction: ADD Q  It Specify: AC [AC] + [Q]  Load P Suggest AC [P] (Fetch P into AC)  Store S Indicate S [AC] (Write AC into S)  To perform S [P] + [Q] AC [P]  Use one address instructions : Load P; Add Q; AC [AC] + [Q] Store S; S [AC]

Zero Address Instruction

 Stack organized computer make use of a special memory

structure called push down stack to store operands. In such computer machines it is possible to use instructions that contain only operation codes and no explicit operands.
 The name Zero address specifies the absence of an address field

of operands in machine instructions.

 Example of Zero address instruction:

NOP in 8085

Instruction Execution & Straight line sequencing

 To perform operation of addition as S (P + Q) [P] + [Q] as:  We shall rewrite instructions to perform S Move P, R0 ; R0 [P] Add Q, R0 ; R0 ;S Move R0, S [R0]

[R0] + [Q]

 Instructions of a given program are fetched one at a time in the increasing order of their memory addresses.  This kind of instruction fetching in sequence (one at a time for execution ) is known as straight line sequencing  Instruction execution can be carried out as two step process viz. # Instruction Fetch cycle. # Instruction Execute cycle.

Instruction Execution & Straight line sequencing

Branching
 Consider branch instruction in a program:

Branch > 0 Loop

 Program execution continues in a straight line sequence until encountering of Branch > 0 Loop instruction  Execution results in a jump to location of Loop.  That is a branch instruction loads a new value in PC - the memory location address (loop) at which program control is to be transferred to start/resume execution.  As a result processor is prohibited from fetching and executing next instruction in straight line sequence.

Condition Codes
 The data conditions or status, after an arithmetic or logical

operation are indicated by setting or clearing the flip flops called flags or condition codes.
 Each flip-flop holding a data condition code is a one bit storage

cell (logic circuit) that can be set to a 1 or reset to 0 value.

 These condition codes are set/reset as a result of arithmetic and

logical operations in the ALU.

 Condition code bits or flag bits are accommodated in a groups of

4 bit, 8 bit or 16 bit flag register or a status register in CPU.

Condition Codes
 Many of the processors include the following four flags: Z - Zero flag bit is set to 1 if the result is 0; N - Negative flag bit is set to 1 if the result is negative; C - Carry flag bit is set to 1 if result generates a carry bit V - Overflow flag bit is set to 1 if arithmetic overflow occurs  Pentium processor makes use of following condition codes:

C (carry flag) P (parity flag) A (Auxiliary carry flag) Z (zero flag) S (sign flag) O (over flow flag)

What are Addressing Modes . . . ?

OPCODE OPERAND/S
Address field

Instruction Format

 The addressing mode specifies a rule or method for interpreting or modifying the address field of the instruction before the operand is actually accessed for manipulation. It is concerned with the different ways in which the location of an operand can be specified in a given instruction. Various schemes for specifying addresses of operands in an instruction have been introduced. Such schemes are collectively known as Addressing Modes.

Addressing Modes:
 Immediate mode  Register mode Absolute (Direct) mode  Indirect mode  Indexed mode  Relative mode  Auto increment mode  Auto decrement mode

Immediate Addressing mode

 Here the operand is specified in the instruction itself. An instruction that follows immediate mode has an operand field rather than an address field.

R2 For example: Move 50immediate, R0 50 R1 R0

 A common convention say, a pound symbol # has to precede the value of an immediate operand Move #50, R0

Register Addressing Mode

 In this scheme, name of the register (address code of a specific general purpose register) appears in the address field of an instruction Example: Move R1, R2

Register Addressing Mode

Advantages of this scheme :
 No memory reference  A few bit address to indicate register location  Speedy execution since register is inside the processor

& has low access time. Disadvantages of this scheme :

 Limited address space as number of registers are less

in many of the processors.

Direct Addressing Mode /Absolute Mode

 Here operand resides in Memory and its address is given explicitly in the address field of an instruction. This scheme need only one memory reference in addition to instruction fetch cycle and no further calculation is required to compute operand address.

Direct Addressing Mode /Absolute Mode

 Direct addressing scheme is simple to use and easy to implement without the requirement for additional hardware.  Examples

Move P, R0 Move R0, S Add Add Q, R0 P, Q

Load P Store S

Indirect Addressing Mode

 Here, the address field of an instruction gives the address of

a memory word in which effective address or actual address of the operand is found.
 By referring to this address (EA), the required operand

can be fetched from memory.

 Example: Add (A), R0

i.e. EA = (A) i.e. contents of A is B

Here B is effective address of desired operand in memory

 Address of (A) address of (B) memory location is the desired

operand (say 50).

Indirect Addressing Mode

Register Indirect Addressing Mode

 Here, instruction specifies a register in the CPU whose contents give the effective address of the operand in Memory.  For example Add (R1), R0 i.e. EA = (R1) i.e. contents of R1 is B

The advantage of Register Indirect Addressing:

 It uses one less memory reference (memory read operation)  Address field of the instruction uses a fewer bits to specify a register  Register indirect addressing can be specified with Effective Address EA = (R) i.e. B Advantages of Indirect addressing: a wider address range to refer to a large number of memory locations. Disadvantage of Indirect addressing: 3 or more memory references (memory read operations) required to fetch the desired operand in memory.

Indexed Addressing Mode

 Here, effective address of the operand is generated by adding a constant value to the contents of a register.  This constant value may be either an offset value called displacement or beginning address of data/operand array in main memory (Base).  Indexed addressing mode is symbolically represented as X(R) &Here X denote a constant and R is name of the register involved in Indexing.  Effective address EA of the operand is given as EA = X + [R] &Contents of index register are not changed during the process of address generation.

Indexed Addressing Mode

A = 1040 = X; constant X corresponds to a memory location i.e. Index or offset value (R) = 20 EA = A + (R) = 1040 + 20 EA = 1060 at which you will find desired operand 50

Indexed Addressing Mode

You can use indexed addressing mode in two ways I) A constant value X defines here beginning address of operand in memory and index register Ri contains offset value (Displacement)

& For example 1040 in the following instruction:

Add 1040 (R1), R2 X=1040 R1=20 offset II) A constant value X defines an offset and index register Ri contains beginning address of operand in memory.

& For example 20 in the following instruction:

Add 20(R1), R2 X=20 R1=1040

Indexed Addressing Mode

Advantages of Index mode is the flexibility it offers to access relative memory locations Disadvantages of Index mode * Is the complexity of computing effective address. * The instruction requires to have two address fields at least one of which is an explicit number.

Relative Addressing Mode

 This scheme supplies the relative position of the memory

operand to be located.
 Its like index mode only but program counter register PC

substitutes for base address contents

 Relative Mode specify Effective Address by a notation:

X(PC)
 Effective address is 

EA = [ PC ] + X

Branch > 0 loop Here jump value / displacement X

Auto Increment Mode

 Here contents of a register specified in the instruction are incremented to denote effective address of next operand in successive memory location.  After accessing the operand, the contents of this register are incremented again automatically to point to the next operand in contiguous memory locations.  Notation for Auto Increment Mode: (Ri) +  For example: Add (R2) +, R0  Use of Auto Increment mode instruction eliminates the use of explicit increment instruction

Auto Decrement Mode

 Here, content of a register specified in the instruction is

decremented to denote effective address of next operand in successive memory location.

 Notation for Auto Decrement Mode: - (Ri)  For instance

Add (R2), R0
 It allows accessing of operands in decreasing order of

memory address..

Addressing Modes
Advantages of Addressing modes :
To be able to reference large number of memory location in main memory or for some system in virtual memory. To reduce number of bits in the address field of an instruction To extend programming convenience to the user / programmer by providing such facilities as indexing of set of data values, counters for loop control, pointers to memory locations

End of first half part of Unit No. 1