Lecture 21

REMINDERS
Review session: Fri. 11/9, 3-5PM in 306 Soda (HP Auditorium) Midterm #2 (Thursday 11/15, 3:30-5PM in Sibley Auditorium)

OUTLINE
Frequency Response

EE105 Fall 2007

Review of basic concepts high-frequency MOSFET model CS stage CG stage Source follower Cascode stage

Reading: Chapter 11
Lecture 21, Slide 1 Prof. Liu, UC Berkeley

Av Roll-Off due to CL
The impedance of CL decreases at high frequencies, so that it shunts some of the output current to ground.
P !0
1 [p ! RD C L
1 RD || Av !  g m j[C L

In general, if node j in the signal path has a smallsignal resistance of Rj to ground and a capacitance Cj to ground, then it contributes a pole at frequency (RjCj)-1
EE105 Fall 2007 Lecture 21, Slide 2 Prof. Liu, UC Berkeley

Pole Identification Example 1

P !0

[ p1
EE105 Fall 2007

1 ! RG Cin
Lecture 21, Slide 3

[ p2

1 ! RD C L
Prof. Liu, UC Berkeley

Pole Identification Example 2

!0

[ p1

1 gm

[ p2
in

1 ! RD C L

EE105 Fall 2007

Lecture 21, Slide 4

Prof. Liu, UC Berkeley

Dealing with a Floating Capacitance

Recall that a pole is computed by finding the resistance and capacitance between a node and (AC) GROUND. It is not straightforward to compute the pole due to CF in the circuit below, because neither of its terminals is grounded.

EE105 Fall 2007

Lecture 21, Slide 5

Prof. Liu, UC Berkeley

Miller s Theorem
If Av is the voltage gain from node 1 to 2, then a floating impedance ZF can be converted to two grounded impedances Z1 and Z2:
V1  V2 V1 V1 1 ! Z1 ! Z F ! ZF ZF Z1 V1  V2 1  Av

!

2 2

!
1

!
2

1 1 1
v Prof. Liu, UC Berkeley

EE105 Fall 2007

Lecture 21, Slide 6

Miller Multiplication
Applying Miller s theorem, we can convert a floating capacitance between the input and output nodes of an amplifier into two grounded capacitances. The capacitance at the input node is larger than the original floating capacitance.
ZF Z2 ! 1 1 1 j [C F ! ! 1 1 j[ 1  1 C F Av Av Av 1

Z1 !

ZF 1 j[C F ! ! 1  Av 1  Av j[   Av C F 1
Lecture 21, Slide 7 Prof. Liu, UC Berkeley

EE105 Fall 2007

Application of Miller s Theorem

!0

1 [in ! R   g m RD C F 1

[ out !

1 1 R D 1  g R C F m D
Prof. Liu, UC Berkeley

EE105 Fall 2007

Lecture 21, Slide 8

MOSFET Intrinsic Capacitances

The MOSFET has intrinsic capacitances which affect its performance at high frequencies:
1. gate oxide capacitance between the gate and channel, 2. overlap and fringing capacitances between the gate and the source/drain regions, and 3. source-bulk & drain-bulk junction capacitances (CSB & CDB).

EE105 Fall 2007

Lecture 21, Slide 9

Prof. Liu, UC Berkeley

High-Frequency MOSFET Model

The gate oxide capacitance can be decomposed into a capacitance between the gate and the source (C1) and a capacitance between the gate and the drain (C2).
In saturation, C1 $ (2/3)Cgate, and C2 $ 0. C1 in parallel with the source overlap/fringing capacitance CGS C2 in parallel with the drain overlap/fringing capacitance CGD

EE105 Fall 2007

Lecture 21, Slide 10

Prof. Liu, UC Berkeley

Example
CS stage with MOSFET capacitances explicitly shown Simplified circuit for high-frequency analysis

EE105 Fall 2007

Lecture 21, Slide 11

Prof. Liu, UC Berkeley

Transit Frequency
The transit or cut-off frequency, fT, is a measure of the intrinsic speed of a transistor, and is defined as the frequency where the current gain falls to 1.
Conceptual set-up to measure fT

I out ! g mVin Vin I in ! Zin

1 I out ! g m Zin ! g m j[ C ! 1 I in T in g [T ! m Cin

gm 2Tf T ! CGS
EE105 Fall 2007 Lecture 21, Slide 12 Prof. Liu, UC Berkeley

Small-Signal Model for CS Stage

P !0

EE105 Fall 2007

Lecture 21, Slide 13

Prof. Liu, UC Berkeley

Applying Miller s Theorem

[ p ,in

1 ! RThev Cin    g m RD GD 1 C 1

[ p ,out !

1 RD Cout  1  g R CGD m D
Prof. Liu, UC Berkeley

Note that [p,out > [p,in

EE105 Fall 2007 Lecture 21, Slide 14

Direct Analysis of CS Stage

Direct analysis yields slightly different pole locations and an extra zero:

gm [z ! C XY 1 [ p1 ! 1  g m RD C XY RThev  RThev Cin  RD C XY  Cout

1  g m RD C XY RThev  RThev Cin  RD C XY  Cout [ p2 ! RThev RD Cin C XY  Cout C XY  Cin Cout

EE105 Fall 2007 Lecture 21, Slide 15 Prof. Liu, UC Berkeley

I/O Impedances of CS Stage

P !0

Z in }

1 j[? GS C

g m RD GD A C

Z out !

j[? GD  CDB A C

|| RD

EE105 Fall 2007

Lecture 21, Slide 16

Prof. Liu, UC Berkeley

CG Stage: Pole Frequencies

CG stage with MOSFET capacitances shown

[ p, X

P !0

1 ! 1 C X RS || gm

C X ! CGS  CSB

[ p ,Y

1 ! RDCY
CY ! CGD  C DB

EE105 Fall 2007

Lecture 21, Slide 17

Prof. Liu, UC Berkeley

AC Analysis of Source Follower

P !0
The transfer function of a source follower can be obtained by direct AC analysis, similarly as for the emitter follower (ref. Lecture 14, Slide 6)

vout vin

CGS 1   j[ gm ! 2 a j[  b j[  1

a!

RS CGD CGS  CGD C SB  CGS C SB gm CGD  C SB gm

Prof. Liu, UC Berkeley

b ! RS CGD 
Lecture 21, Slide 18

EE105 Fall 2007

Example
vout vin CGS gm ! 2 a j[  b j[  1 1   j[

RS a! ?C GD 1C GS 1  (C GD 1  C GS 1 )( C SB 1  C GD 2  C DB 2 ) A g m1 C GD 1  C SB 1  C GD 2  C DB 2 b ! R S C GD 1  g m1
EE105 Fall 2007 Lecture 21, Slide 19 Prof. Liu, UC Berkeley

Source Follower: Input Capacitance

Recall that the voltage gain of a source follower is Av !
Follower stage with MOSFET capacitances shown

RS 1  RS gm

!0

CXY can be decomposed into CX and CY at the input and output nodes, respectively:
C X !   Av GS 1 C CGS ! 1  g m RS

CGS Cin ! CGD  1  g m RS

EE105 Fall 2007 Lecture 21, Slide 20 Prof. Liu, UC Berkeley

Example

P{0

1 Cin ! CGD1  CGS 1 1  g m1 rO1 || rO 2

EE105 Fall 2007 Lecture 21, Slide 21 Prof. Liu, UC Berkeley

Source Follower: Output Impedance

P !0
The output impedance of a source follower can be obtained by direct AC analysis, similarly as for the emitter follower (ref. Lecture 14, Slide 9)

vX j[RG CGS  1 ! iX j[CGS  g m

EE105 Fall 2007 Lecture 21, Slide 22 Prof. Liu, UC Berkeley

Source Follower as Active Inductor

Z out
CASE 1: RG < 1/gm

j[RG CGS  1 ! j[CGS  g m

CASE 2: RG > 1/gm

A follower is typically used to lower the driving impedance, i.e. RG is large compared to 1/gm, so that the active inductor characteristic on the right is usually observed.
EE105 Fall 2007 Lecture 21, Slide 23 Prof. Liu, UC Berkeley

Example
P3 ! 0

Z out

j[ r 1 r 2 CGS 3  1 ! j[CGS 3  g m 3
Lecture 21, Slide 24 Prof. Liu, UC Berkeley

EE105 Fall 2007

MOS Cascode Stage

For a cascode stage, Miller multiplication is smaller than in the CS stage.

Av , XY

1 vX } 1 | !  g m1 g vY m2

C X } 2C XY

EE105 Fall 2007

Lecture 21, Slide 25

Prof. Liu, UC Berkeley

Cascode Stage: Pole Frequencies

P !0
Cascode stage with MOSFET capacitances shown (Miller approximation applied)

[ p ,out !

1 R D C DB 2  C GD 2

[ p ,Y !

1 1 gm2 g C DB 1  C GS 2  1  m 2 g m1 C GD 1  C SB 2

[ p,X !

1 g RG C GS 1  1  m 1 gm2 C GD 1

EE105 Fall 2007

Lecture 21, Slide 26

Prof. Liu, UC Berkeley

Cascode Stage: I/O Impedances

P !0

Z in !

1 g m1 j[ CGS 1  1  g CGD1 m2

Z out ! RD

1 j[ CGD 2  C DB 2

EE105 Fall 2007

Lecture 21, Slide 27

Prof. Liu, UC Berkeley