Fault models

Stuck-at-0 Transition /0 Reset coupling Inversion coupling AND bridging Neighborhood pattern sensitive faults (active)

1 0 0 1 0

1 1

0 1 1

1 0

0 0

Address decoder faults

ADR ADR

ADR ADR

ADR ADR

ADR ADR

0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0
0

0 0 0 0

0 0 0 0 0 0 0 0
1 1 0 1 1 1

1 Stuck-at-1 1 1 1 0 1 0 0 1 1
Transition /1 Set coupling Inversion coupling OR bridging Neighborhood pattern sensitive faults (passive)

ADR ADR

Elements of march test

(w0) 7 6 5 4 3 2 1 0 (w1) (r1,w0) (r0,w1)

x x x x x x x x

0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1

1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1

1 1 1 1 1 1 1 1

1 0 1 0 0 1 0 1 1 0 1 0 1 0 0 1

0 0 0 0 0 0 0 0

C - algorithm
(w0) (r0,w1) (r1,w0) (r0,w1) (r1,w0) (r0)

0 0 0 0 0 0 0 0

1 0 1 0 0 1 0 1 1 0 1 0 1 0 0 1

0 0 0 0 0 0 0 0

1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1

1 1 1 1 1 1 1 1

1 0 1 0 0 1 0 1 1 0 1 0 1 0 0 1

0 0 0 0 0 0 0 0

1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1

1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

Number of steps: 10n Fault coverage: AFs, SAFs, TFs, CFins , CFids

Checkerboard test and data retention

1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1
Designed to test refresh operations of DRAMs Maximizes leakage current and detects leakage faults Used as data retention test To be effective it must consider address scrambling and layout

Data backgrounds for word memories

2 (log 2w + 1) backgrounds 2 (log w + 1) backgrounds 16
2

Multiple data backgrounds to detect coupling and bridging faults between cells of the same word Multiple data backgrounds to detect coupling and bridging faults between cells of the same word For every pair of cells all four combinations are checked For every pair of cells all four combinations are checked 16backgrounds for backgrounds for 128-bitwide memory wide memory

128-bit

Normal and inverse Normal and inverse

D0 D1 D2 D3 D4 D5 D6 D7 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 1 1 0 0 1 0 1 0 1 1 0 1 0 0 1 1 0 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 1 0 0 1 0 1 1 0 1 0 1 0

Data in word-oriented memory

(w0) (r0,w1) (r1,w0) (r0,w1)

Parallel memory BIST

Clock Hold

System logic

F F S S M M

Data generator Data generator Address generator Address generator Control generator Control generator

Fail

Start

Done

BIST mode

Memory

Serial memory BIST

System logic
Data output Serial input Serial output

Memory

Minimal logic and routing Longer test time

r0 w1 r0 w1 r0 w1 r0 w1 r1

Address M 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1

Serial-parallel data interface trade-offs

Memory Memory

Memory

Memory

Memory BIST collar

Functional logic
Memory BIST Memory BIST controller controller Memory controller at the top level
To / From TAP controller

TAP controller as test engine

Embedded memory BIST collar

mux address / control bus and data lines local comparator with single pass/fail local data generator to reduce routing area and timing problems local address validation

Memory array

Shared controller and parallel test

Functional logic
Memory BIST Memory BIST controller controller

To / From TAP controller

Insert collars Connect them through memory test bus

to memory BIST controller to TAP

Memory array

Memory array

Parallel memory BIST collar

Functional control BIST control

BIST address Functional address

BIST data Functional data Pass / Fail

Sin

MBIST mode

=?

Sout
Address Ctrl Data in Data out

Memory array
Clock

Full-Speed test application

Runs at system clock speeds with single cycle read/write operations Uncovers speed-related defects Reduce test application time.
Clock Cycle 1 Clock Cycle 2 Clock Cycle 3 Clock Cycle 4 Clock Cycle 5

Clock Addr/Cntrl/ Data Memory Output Compare Circuitry Circuit Output Write
Setup Setup Read 1 Read 1 Setup Write 1 Read 1 Compare Read 1 Pass/Fail Read 1 Write 1 Setup Read 2 Setup Read 3 Read 2 Compare Read 2 Setup Write 2 Read 3 Compare Read 3 Pass/Fail Read 2

Diagnostics

Detect failing location/data during test Should diagnose speed related defects Two types - Hold and resume, Hold and restart How it works?

BIST controller stops after 1 (or 2) failures Fail data is scanned out BIST session resumes from where it stops (Hold and resume) BIST session restarts after fail data is scanned out (Hold and restart)

Full-speed diagnostics

MBIST controller

+
Restart

Diagnostic monitor

ATE

Memory Memory array array

Yield improvement with memory redundancy

Memory percentage, defect rate, and redundancy amount affect yield

Redundancy Yield Improvement
100 90 80 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 90 100

Optimal Level 3 Redundancy Level 2 Redundancy Level 1 Redundancy No Redundancy

Memory Yield

Chip Memory Percentage

Source: Zorian, Rodgers, DATE 2002

Redundancy and repair

Memory BIST Memory BIST controller controller

Memory Memory Array Array

Extra columns, rows, or rows and columns At the end of test - good, repairable, or non-repairable Repair data scanned out at the end of test

Full-Chip memory BIST integration

Read in SOC netlist Identify memories

BIST GENERATION
Assign memories to controller (BIST Scheduling)

Memory BIST Generation (Generate Controller/Collars)

BIST INSERTION
Insert controllers in the design Stitch controllers to top-level

Full Chip Memory BIST Control

SOC
TM S TCK TRST Block TAP Controller BIST Block Memory 1 BIST Controller test_done fail_h test_h MBIST Data Register TDI Boundary Scan Register

rst_l CLK

BIST Block Memory 2

TDO

Programmable algorithms

Selection of algorithms

March1, March2, March3, Unique Address, Checkerboard, address jumping user defined prior to synthesis simple language number of sequences, backgrounds, sequence elements etc., defect mechanisms may not be known before fabrication memory BIST controller implements a class of algorithms field programmable parameters define active elements of test sequences

Synthesizable algorithms

Programmable algorithms

Summary
Key

components of a BIST controller

algorithm controller data background generator address generator comparator

Very

high quality test of embedded arrays BIST controller shared across a number of memory arrays to reduce area BIST diagnostics helps in gathering failure information Built-in repair results in yield improvement