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Exceptions
System Design
Memory Interface
Synchronization
Input / Output
Condition Field
The software interrupt instruction (SWI) is used for entering Supervisor mode,
usually to request a particular supervisor function.
R14_svc = Address of next instruction after the SWI instruction
SPSR_svc = CPSR
CPSR[4:0] = 0b10011
CPSR[T,IRQ] = 0b01 (ARM State, and Disable IRQs)
Forces the PC to fetch the next instruction from address 0x08 or
0xFFFF0008
Upon Exiting SWI
CPSR = SPSR_svc
MOVS PC,R14_svc (This restores the PC and CPSR, and returns to
the instruction following the SWI)
If a data abort occurs, the action taken depends on the instruction type:
Single data transfer instructions (LDR, STR) write back modified
base registers: the Abort handler must be aware of this.
The swap instruction (SWP) is aborted as though it had not been
executed.
Block data transfer instructions (LDM, STM) complete.
If write-back is set, the base is updated.
If the instruction would have overwritten the base with data (ie it
has the base in the transfer list), the overwriting is prevented.
All register overwriting is prevented after an abort is indicated,
which means in particular that R15 (always the last register to be
transferred) is preserved in an aborted LDM instruction.
The abort mechanism allows the implementation of a demand
paged virtual memory system. In such a system the processor is
allowed to generate arbitrary addresses. When the data at an
address is unavailable, the Memory Management Unit (MMU)
signals an abort.
The abort handler must then work out the cause of the abort, make the
requested data available, and retry the aborted instruction. The application
program needs no knowledge of the amount of memory available to it, nor is
its state in any way affected by the abort
Entering Data Abort
R14_abt = Address of aborted instruction + 8
SPSR_abt = CPSR
CPSR[4:0] = 0b10111
CPSR[T,IRQ] = 0b01 (ARM State, and Disable IRQs)
Forces the PC to fetch the next instruction from address 0x10 or
0xFFFF0010
Upon Exiting Data Abort
CPSR = SPSR_abt
SUBS PC,R14, #8 (This restores the PC and CPSR, and re-executes the
aborted instruction)
SUBS PC,R14, #4 (This restores the PC and CPSR, and returns to the
instruction following the data abort instruction)
SPSR_fiq = CPSR
CPSR[4:0] = 0b10001
0xFFFF001C
Exiting FIQ
CPSR = SPSR_fiq
SUBS PC,R14_fiq, #4 (This restores the PC and CPSR, and returns to the
instruction)
39v10 The ARM Architecture TM
12 12
Return Address Calculation
Return Instruction Previous State Cycles
Highest priority:
1. Reset
2. Data abort
3. FIQ
4. IRQ
5. Pre-fetch abort
Lowest priority:
6. Undefined Instruction and Software interrupt.
Exceptions
System Design
Memory Interface
Synchronization
Input / Output
Interrupt
Controller
Peripherals I/O
nIRQ nFIQ
ARM
Core
8 bit ROM
ARM
TIC
Remap/
External Bus Interface Timer
Pause
ROM External
Bridge
Bus
Interface
External
RAM Onchip Interrupt
Decoder RAM Controller
AHB or ASB APB
System Bus Peripheral Bus
AMBA
Advanced Microcontroller Bus Architecture
Open specification framework for System-on-Chip (SoC) Designs
Exceptions
System Design
Memory Interface
Synchronization
Input / Output
Memory Hierarchy
Memory Size and Speed
ARM MMU
Memory Interfacing
SRAM access times are 2 - 25ns at cost of $100 to $250 per Mbyte.
1997
DRAM access times are 60-120ns at cost of $5 to $10 per Mbyte.
Disk access times are 10 to 20 million ns at cost of $.10 to $.20 per Mbyte.
CPU
Level n
If an item is referenced,
Two issues:
How do we know if a data item is in the cache?
If it is, how do we find it?
Our first example:
block size is one word of data
"direct mapped"
e.g., lots of items at the lower level share locations in the upper level
Memory Hierarchy
Memory Size and Speed
ARM MMU
Memory Interfacing
tRC
Address and chip select tAA
signals are provided tAA Address
before data is available A11-A0 old address new address
CS
Outputs reflect new data
WE
high undef
Address Bus Dout
impedance
Data Valid
tHz
2147H High-Speed 4096x1-bit static RAM tACS
2147H
Dout
A11-A0
tRC = Read cycle time
tAA = Address access time
DinWE CS
tACS = Chip select access time
tHZ = Chip deselections to high-Z out
WE
Address Bus
2147H High-Speed 4096X1-bit static RAM Din old data new data
tHz
2147H tACS
Din
A11-A0
DinWE CS
tS = Signal setup time
tRC = Read cycle time
tAA = Address access time
tACS = Chip select access time
tHZ = Chip deselections to high-Z out
Memory Hierarchy
Memory Size and Speed
ARM MMU
Memory Interfacing
x
220 y
entries page 212
data entries
table page
frame
8 bits
Size of page table
= 220 * 32 bits = 4 Mbytes Size of page
= 212 * 8 bits = 4 Kbytes
Assumptions
32-bit virtual addresses
4 Kbyte page size = 212 bytes
32-bit address space
x
210 y 210
entries entries
page z
directory 212
page data
32 bits table
entries
page
32 bits frame
Size of page directory
8 bits
= 210 * 32 bits = 4 Kbytes
Size of page table
= 210 * 32 bits = 4 Kbytes
Size of page
= 212 * 8 bits = 4 Kbytes
Assumptions
210 entries in page directory (= max number of page tables)
210 entries in page table
32 bits allocated for each page directory entry
32 bits allocated for each page table entry
Memory Hierarchy
Memory Size and Speed
ARM MMU
Memory Interfacing
Extra Signals
BE – Bank Enable
Exceptions
System Design
Memory Interface
Synchronization
Input / Output
What to do ?????
That’s Synchronization
Semaphores
Mutual Exclusion
Message Ques
Pipes … etc
Exceptions
System Design
Memory Interface
Synchronization
Input / Output
Protocol refers to the set of rules agreed upon by both the bus
master and bus slave
Synchronous bus - transfers occur in relation to successive edges of a
clock
Asynchronous bus - transfers bear no particular timing relationship
Semi-synchronous bus - Operations/control initiate asynchronously,
but data transfer occurs synchronously
Bus
Clock
stable stable
Address Instruction Addr Data Addr
decoding delay
Master (CPU) RD
Master (CPU) CS
unstable stable unstable stable
Data I-fetch data
access time
Any
Questions?