The Necessity of Digital Signal Processors

computers

are extremely capable in two broad areas, (1) data manipulation, such as word processing and database management, and (2) mathematical calculation, used in science, engineering, and Digital Signal Processing All microprocessors can perform both tasks; however, it is difficult (expensive) to make a device that is optimized for both.

The Necessity of Digital Signal Processors

DSPs

are designed to perform the mathematical calculations needed in Digital Signal Processing motion control, scientific and engineering simulations, etc. A Digital signal processor can be simply said as, a device which can compute sum of products at blinding speed such as Convolution, Correlation, DFT & Filtering

History of Digital Signal Processors

1978, Intel released the 2920 as an "analog signal processor". It had an on-chip ADC/DAC with an internal signal processor, but it didn't have a hardware multiplier and was not successful in the market. In 1979, AMI released the S2811. It was designed as a microprocessor peripheral, and it had to be initialized by the host. The S2811 was likewise not successful in the market.
In

History of Digital Signal Processors

The First Generation (1979 to 1987) A multiplyaccumulate (MAC) took 390 ns

MAC-4 by Bell Labs in 1979

Harvard architecture came into existence TMS32010 by Texas Instruments in 1982

NEC PD7720 by NEC in 1980

History of Digital Signal Processors

Second Generation (1988 to 1995):

A lti lya lat (MAC) too 21 ns

AT&T DSP16A

C20xx and C30xx by TI

Motorola DSP56001

History of Digital Signal Processors

The Third Generation (1996 to 2002)

Other DSPs from 1995 are the TI TMS320C541 or the TMS 320C80.

The main improvement in the third generation was the appearance of application-specific units and instructions in the data path, or sometimes as coprocessors.

Some chips, like the Motorola MC68356, even included more than one processor cores to work in parallel.

These units allowed direct hardware acceleration of very specific but complex mathematical problems, like the Fourier-transform or matrix operations.

History of Digital Signal Processors

The Fourth Generation (2002 onwards)

increased, a 3ns MAC became now possible.

The fourth generation is best characterized by the changes in the instruction

VLIW and the superscalar architecture appeared. As always, the clockspeeds have

set and the instruction encoding/decoding. SIMD and MMX extensions were added;

Todays signal processors yield much greater performance. This is due in part to both technological and architectural advancements like lower design rules, fastaccess two-level cache, (E) DMA circuit and a wider bus system. A Texas Instruments C6000 series DSP clocks at 1Ghz and implementsseparate instruction and data caches as well as a 8Mbyte 2nd level cache, and its I/O speed is rapid thanks to its 64 EDMA channels. The top models are capable of even 8000 MIPS (million instructions per second), use VLIW encoding, perform eight operations per clock-cycle and are compatible with a broad range of external peripherals and various buses (PCI/serial/etc).

Processor Architectures
One

of the biggest bottlenecks in executing DSP algorithms is transferring information to and from memory. This includes data, such as samples from the input signal and the filter coefficients, as well as program instructions, the binary codes that go into the program sequencer.

Von Neumann Architectu re

Harvard

Archit ecture

VLIW Archit ecture

The

VelociTI
Architecture

Von Neumann Architecture

Von

Neumann architecture contains a single memory and a single bus for transferring data into and out of the central processing unit (CPU). The Von Neumann design is quite satisfactory when you are content to execute all of the required tasks in serial.

Von Neumann Architecture

Harvard Architecture
This is named for the work done at Harvard University in the 1940s under the leadership of Howard Aiken (1900-1973). Aiken insisted on separate memories for data and program instructions, with separate uses for each Since the buses operate independently, program instructions and data can be fetched at the same time, improving the speed over the single bus design A handicap of the basic Harvard design is that the data memory bus is busier than the program memory bus

Harvard Architecture

VLIW Architecture
VLIW

stands for Very Long Instruction Word. This architecture was introduced by Texas Instruments. As the name itself denotes, we fetch a long instruction. Meaning, in the C6000, eight instructions (this is definitely long!) are always fetched in every clock cycle. This constitutes a fetch packet.

VLIW Architecture

A traditional VLIW architecture consists of multiple execution units running in parallel, performing multiple instructions during a single clock cycle.

The VelociTI Architecture

The

VelociTI architecture of the C6000 platform of devices makes them the first offthe-shelf DSPs to use advanced VLIW to achieve high performance through increased instruction-level parallelism. VelociTI is a highly deterministic architecture, having few restrictions on how or when instructions are fetched, executed, or stored.

o Instruction packing: reduced code size

Other on-board peripherals include:
(a) Enhanced Direct Memory Access (EDMA) controller

o All instructions can operate conditionally: flexibility of code o Variable-width instructions: flexibility of data types o Fully pipelined branches: zerooverhead branching.

(e) PhaseLocked Loop (PLL) controller

(d) Power-down logic (c) Interrupt selector

(b) External Memory Interface (EMIF)

The VelociTI Architecture

The VelociTI Architecture

VelociTI

capitalizes on VLIW strengths while addressing its shortcomings with: High silicon densities to improve speed paths through functional units Architectural innovations: flexible addressing modes, intelligent memory and peripheral support, flexible instruction packing and critical-path pipelining schemes Compiler-friendly: orthogonal, deterministic, 100% conditional RISC-like instruction set Advanced compiler and optimization technologies

The C6000 DSP Core

The

DSP core consists of registers and the functional units which can be programmed by the user. The functions of the various components which make-up the C6000 core are explained next.

The C6000 DSP Core

The C6000 DSP Core

The CPU contains
Control registers Program fetch unit

32 32-bit registers, 64 32-bit registers (C64 only)

Instruction dispatch unit, advanced instruction packing (C64 only)

Two data paths, each with four functional units

Instruction decode unit

The eri her ls f

The functions of various peripherals supported by the C6000 are:

McBSP (Multichannel Buffered Serial Port)

DMA (Direct Memory Access) Controller

HPI (Host Port Interface)

EDMA (Enhanced DMA) Controller

The DaVinci Technology

A typical multimedia system such as a digital video recorder or digital camera can be split roughly into two pieces: control and media. The control portion handles tasks such as memory card or hard disk access, user interface, and networking, while the media portion covers tasks such as encoding and decoding of audio and video. The idea behind DaVinci is that by using both a general-purpose processor and a DSP, the control and media portions can both be executed by processors that excel at their respective tasks. The integration of these two components into one chip simplifies the system design and allows for more efficient communication between the two components.

The DaVinci Technology

Existing Systems
DaVinci Technology has grown to support DSP only processors including TMS320DM6431, TMS320DM6433, TMS320DM6435 and TMS320DM6437. Models DM6443 = ARM9 + Texas Instruments TMS320C64x+ DSP + DaVinci Video (Decode) Video Accelerator and Networking for display DM6446 = ARM9 + Texas Instruments TMS320C64x+ DSP + DaVinci Video (Encode and Decode) Video Accelerator and Networking for capture and display

Peripherals and Operating System

The DaVinci includes a number of on-chip peripherals. These include:

Enhanced DMA

Support for memory cards such as CompactFlash, SD Card and MMC

FPGA, Wireless LAN, PCI), EMAC (Ethernet MAC) with MDIO

ATA interface

Connectivity, including USB 2.0 Host and Client modes, VLYNQ (interface for

CCD Controller for digital camera/camcorder applications

A number of operating systems support DaVinci and the

DSP/BIOS Link drivers: Green Hills Software INTEGRITY RTOS Montavista Linux

QNX Neutrino Windows CE

Applications
Applications High-end

applications include: Stream live-video on to a portable, handheld device An on-board intelligence system in your car can record obstructions in front of the windscreen. Surveillance videos directly captured by a TV and transferred to a computer/controller

Applications
Other

everyday applications which have a potential to exploit DaVinci are: 1200- to 56Kbps modems Digital Subscriber Loop X.25 packet switching Image Compression Homomorphic Processing Robotic Vision Pattern Recognition

Conclusions
Necessity is the mother of all inventions. Hence the origin and four generations of DSPs were first considered. The failure of Von Neumann architecture led to the Harvard architecture, which was further developed into VLIW architecture. The data path and control registers are a dominating feature of the C6000s architecture. Each instruction is mapped uniquely to every functional unit. The DaVinci is a state-of-the-art technology that is designed with. video and multimedia applications in mind.