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Chapter Goals
Understand the magic of negative feedback and the characteristics of ideal op amps. Understand the conditions for non-ideal op amp behavior so they can be avoided in circuit design. Demonstrate circuit analysis techniques for ideal op amps. Characterize inverting, non-inverting, summing and instrumentation amplifiers, voltage follower and first order filters. Learn the factors involved in circuit design using op amps. Find the gain characteristics of cascaded amplifiers. Special Applications: The inverted ladder DAC and successive approximation ADC
and
lim vid ! 0 Ap g
If A is infinite, vid is zero for any finite output voltage. Infinite input resistance Rid forces input currents i+ and i- to be zero. The ideal op amp operates with the following assumptions: It has infinite common-mode rejection, power supply rejection, openloop bandwidth, output voltage range, output current capability and slew rate It also has zero output resistance, input-bias currents, input-offset current, and input-offset voltage.
The positive input is grounded. A feedback network composed of resistors R1 and R2 is connected between the inverting input, signal source and amplifier output node, respectively.
But i1=i2
@vx ! i ( R R ) 1 2 1
R ! ! R since v ! 0 in i 1 s
vs
The input signal is applied to the non-inverting input terminal. A portion of the output signal is fed back to the negative input terminal. Analysis is done by relating the voltage at v1 to input voltage vs and output voltage vo .
and
vs v ! v id 1
@vs ! v 1 R R v o ! vs 1 2 R 1 R v o R1 R2 @ Av ! ! ! 1 2 R vs R 1 1 vs R ! !g Since i+=0 in i Rout is found by applying a test current source to the amplifier output after setting vs = 0. It is identical to the output resistance of the inverting amplifier i.e. Rout = 0.
For AF >>1, R 1 Av $ !1 2 F R 1 This is the ideal voltage gain of the amplifier. If AF is not >>1, there will be Gain Error.
Gain Error
Gain Error is given by GE = (ideal gain) - (actual gain) For the non-inverting amplifier,
GE ! 1 A 1 ! F 1 AF F (1 AF )
io ! i i ! L F
vo
vo
R R R R L 2 1 EQ R ! R (R R ) L 1 2 EQ
vo
This is a special case of the non-inverting amplifier, which is also called a voltage follower, with infinite R1 and zero R2. Hence Av = 1. It provides an excellent impedance-level transformation while maintaining the signal voltage level. The ideal buffer does not require any input current and can drive any desired load resistance without loss of signal voltage. Such a buffer is used in many sensor and data acquisition system applications.
Here Adm is called the differential mode voltage gain of the difference amplifier.
An ideal amplifier has Acm = 0, but for a real amplifier, Acm v v ic ! A v ic vo ! A v dm id dm id CMRR A dm A CMRR ! dm Acm
and CMRR(dB) ! 20log (CMRR) 10
! 89.9 d
Instrumentation Amplifier
R vo ! 4 (va v ) b R 3 va iR i(2 R ) iR ! v 2 1 2 b v v i! 1 2 2R 1 R R @vo ! 4 1 2 (v v ) R R 1 2 3 1
NOTE
Combines 2 non-inverting amplifiers with the difference amplifier to provide higher gain and higher input resistance.
Ideal input resistance is infinite because input current to both op amps is zero. The CMRR is determined only by Op Amp 3.
Cascaded Amplifiers
Connecting several amplifiers in cascade (output of one stage connected to the input of the next) can meet design specifications not met by a single amplifier. Each amplifer stage is built using an op amp with parameters A, Rid, Ro, called open loop parameters, that describe the op amp with no external elements. Av, Rin, Rout are closed loop parameters that can be used to describe each closed-loop op amp stage with its feedback network, as well as the overall composite (cascaded) amplifier.
Each amplifier in the 3-stage cascaded amplifier is replaced by its 2-port model. R R in inC A A vo ! A vs v vC vA R R R R outA out in inC v Av ! o ! A A A Since Rout= 0 vA v vC vs Rin= RinA and Rout= RoutC = 0
A Problem: Voltage Follower Closed Loop Gain Error due to A and CMRR
The ideal gain for the voltage follower is unity. The gain error here is: A 1 CMRR GE ! 1 Av ! 1 1 A 1 2(CMRR)
v ! vs vo id
v ! ic
vs v o 2
vo ! A vs vo
2(CMRR)
vs vo
1 A 1 vo 2(CMRR) Av ! ! vs 1 1 A 1 2(CMRR)
Since, both A and CMRR are normally >>1, 1 1 $ A Since A ~ 106 and ~ 104 at low to moderate frequency, the gain error is quite small and is, in fact, usually negligible.
A very common DAC circuit architecture with good precision. Currents in the ladder and the reference source are independent of digital input. This contributes to good conversion precision. Complementary currents are available at the output of inverted ladder. The bit switches need to have very low on-resistance to minimize conversion errors.
To avoid this frequency limitation, a high speed sample-and-hold circuit is used ahead of the successive approximation ADC. This is a very popular ADC with fast conversion times, used in 8- to 16- bit converters.