PROGRAMMABLE LOGIC DEVICES

Overview
Why programmable logic? Programmable logic technologies Read-Only Memory (ROM) Programmable Logic Array (PLA) Programmable Array Logic (PAL) VLSI Programmable Logic Devices CPLD, FPGA

Why Programmable Logic?

Facts:

It is most economical to produce an IC in large volumes Many designs required only small volumes of ICs

Need an IC that can be:

Produced in large volumes Handle many designs required in small volumes

A programmable logic part can be:

made in large volumes programmed to implement large numbers of different low-volume designs

Programmable Logic - Additional Advantages

Many programmable logic devices are field- programmable, i. e.,

can be programmed outside of the manufacturing environment Most programmable logic devices are erasable and reprogrammable.

Allows updating a device or correction of errors Allows reuse the device for a different design - the ultimate in reusability! Ideal for course laboratories

Programmable logic devices can be used to prototype design that

will be implemented for sale in regular ICs.

Complete Intel Pentium designs were actually prototype with specialized systems based on large numbers of VLSI programmable devices!

Programmable Logic Technologies

Fuse and anti-fuse

Fuse makes or breaks link between two wires Typical connections are 50-300 ohm One-time programmable (testing before programming?) Very high density High power consumption Typical connections are 2K-4K ohm Fairly high density Memory bit controls a switch that connects/disconnects two wires Typical connections are .5K-1K ohm Can be programmed and re-programmed in the circuit Low density

EPROM and EEPROM

RAM-based

Programmable Configurations
Read Only Memory (ROM) - a fixed array of AND gates and

a programmable array of OR gates Programmable Array Logic (PAL) - a programmable array of AND gates feeding a fixed array of OR gates. Programmable Logic Array (PLA) - a programmable array of AND gates feeding a programmable array of OR gates. Complex Programmable Logic Device (CPLD) /FieldProgrammable Gate Array (FPGA) - complex enough to be called architectures - See VLSI Programmable Logic Devices
reading supplement

Programmable Logic
Program a connection

Connect two wires Set a bit to 0 or 1 All rely on two-level logic minimization PROM connections - permanent EPROM connections - erase with UV light EEPROM connections - erase electrically PROMs

Regular structures for two-level logic (1960s-70s)

Program connections in the _____________ plane Program the connections in the ____________ plane Program the connections in the ____________ plane

PLAs

PALs

ROM, PAL and PLA Configurations

8
Inputs Fixed AND array (decoder )

Programmable Connections

Programmable OR array

Outputs

(a) Programmable read-only memory (PROM)

Inputs

Programmable Connections

Programmable AND array

Fixed OR array

Outputs

(b) Programmable array logic (PAL) device

Inputs

Programmable Connections

Programmable AND array

Programmable Connections

Programmable OR array

Outputs

(c) Programmable logic array (PLA) device

Read Only Memory

Read Only Memories (ROM) or Programmable Read Only Memories

(PROM) have:

N input lines, M output lines, and 2N decoded minterms.

Fixed AND array with 2Noutputs implementing all N-literal minterms. ProgrammableOR Array with M outputs lines to form up to M sum of

minterm expressions. A program for a ROM or PROM is simply a multiple-output truth table

If a 1 entry, a connection is made to the corresponding minterm for the corresponding output If a 0, no connection is made

Can be viewed as a memory with the inputs as addresses of data (output

values), hence ROM or PROM names

Read Only Memory Example

Example: A 8 X 4 ROM (N = 3 input lines, M= 4 output
10

lines) The fixed "AND" array is a X X X D7 decoder with 3 inputs and 8 D6 outputs implementing minterms. D5 X X X D4 The programmable "OR A2 D3 array uses a single line to A X D2 X X A1 D1 represent all inputs to an B X A0 D0 OR gate. An X in the C array corresponds to attaching the minterm to the OR Read Example: For input (A2,A1,A0) = 011, output is (F3,F2,F1,F0 ) = 0011. F3 F2 F1 F0 What are functions F3, F2 , F1 and F0 in terms of (A2, A1, A0)?

Programmable Array Logic (PAL)

The PAL is the opposite of the ROM, having a
11

programmable set of ANDs combined with fixed ORs. Disadvantage

ROM guaranteed to implement any M functions of N inputs. PAL may have too few inputs to the OR gates.

Advantages For given internal complexity, a PAL can have larger N and M Some PALs have outputs that can be complemented, adding POS functions No multilevel circuit implementations in ROM (without external connections from output to input). PAL has outputs from OR terms as internal inputs to all AND terms, making implementation of multi-level circuits easier.

Programmable Array Logic Example

4-input, 3-output PAL
12
Product 1 term 2 3 AND gates inputs 0 1 2 3 4 5 6 7 8 9

with fixed, 3-input OR terms What are the equations I 5 A for F1 through F4? F1=AB+C F2=ABC+AC+AB I 5B F3=? F4=?
1 2

X X X
F1

4 5 6

X X X X X X

X
F2

7 8 9

X X

X X X
F3

I3 5 C
10 11 12

X X X X
F4

I4
0 1 2 3 4 5 6 7 8 9

Programmable Logic Array (PLA)

Compared to a ROM and a PAL, a PLA is the most
13

flexible having a programmable set of ANDs combined with a programmableset of ORs. Advantages

A PLA can have large N and M permitting implementation of equations that are impractical for a ROM (because of the number of inputs, N, required A PLA has all of its product terms connectable to all outputs, overcoming the problem of the limited inputs to the PAL Ors Some PLAs have outputs that can be complemented, adding POS functions

Disadvantage Often, the product term count limits the application of a PLA. Two-level multiple-output optimization reduces the number of product terms in an implementation, helping to fit it into a PLA.

Programmable Logic Array Example

A B C
X X 1

What are the equations for F1 and F2?

14

Could the PLA implement the

X X

functions without the XOR gates? AB BC AC AB

X X Fuse intact X Fuse blown

C C B B A A

3-input, 3-output PLA

0 1 F1 F2

with 4 product terms

Making Large Programmable Logic Circuits

Alternative 1 : CPLD Put a lot of PLDS on a chip Add wires between them whose connections can be programmed Use fuse/EEPROM technology Alternative 2: FPGA Emulate gate array technology Hence Field Programmable Gate Array You need:
A way to implement logic gates A way to connect them together

Field-Programmable Gate Arrays

PALs, PLAs = 10 - 100 Gate Equivalents Field Programmable Gate Arrays = FPGAs Altera MAX Family Actel Programmable Gate Array Xilinx Logical Cell Array 100 - 1000(s) of Gate Equivalents!

CPLD Architecture (1)

Dedicated inputs

I/Os

PAL Block

Central Switch Matrix

PAL Block

I/Os

I/Os

PAL Block

PAL Block

I/Os

Clock/ Inputs
The CPLD is an array of PAL-like devices, interconnected by a switch matrix.

CPLD Architecture (2)

The CPLD architecture is more complex than typical

PAL in order to fully utilize the increased logic capacity and additional routing matrices of the device. The CPLD Macro cell although relatively similar to the PAL macro cell and has greater flexibility in routing its output to both I/O cells and switching matrix. The I/O cell controls both the input and output to and from the device.

CPLD Architecture (2)

Clock/Input
Central Switch Matrix
Clock Generator

Logic Array &Allocator

Output Switch Matrix

Output Macrocell

I/O Cells

The CPLD architecture is more complex than the typical PAL in order to fully utilize the increase I/O logic capacity and additional routing matrices of the device.

Input Switch Matrix

From Logic Allocator From Clock Generator

To Output/Input Switch Matrix

Product Term Enable From Output Switch Matrix To Input Switch Matrix

I/O Q D From Clock Generator

Field-Programmable Gate Arrays

Logic blocks To implement combinational and sequential logic Interconnect Wires to connect inputs and outputs to logic blocks I/O blocks Special logic blocks at periphery of device for external connections

Xilinx FPGAs -

FPGA
There are three FPGA models basically available 1. Altera

2. Actel 3. Xilinx

CLB

CLB
D Q

Slew Rate Control

Passive Pull-Up, Pull-Down

Vcc

Switch Matrix

Output Buffer

Pad

Input Buffer

CLB

CLB

Delay

Programmable Interconnect
C1 C2 C3 C4 H1 DIN S/R EC
S /R C ontrol

I/O Blocks (IOBs)

G4 G3 G2 G1

G Func. Gen. H Func. Gen. F Func. Gen.

DIN F' G' H'

SD D Q

1 G' H' S/R Control

EC RD

F4 F3 F2 F1

DIN F' G' H'

SD D Q

H'

EC RD

F'

Configurable Logic Blocks (CLBs)

The Xilinx 4000 CLB

Xilinx FPGAs -

Xilinx 4000 Interconnect

Xilinx FPGAs -

Switch Matrix

Xilinx FPGAs -

Global Signals - Clock, Reset, Control

Xilinx FPGAs -

Xilinx 4000 IOB

Xilinx FPGAs -

Xilinx FPGA Combinational Logic Examples

Key: General functions are limited to 5 inputs (4 even better - 1/2 CLB) No limitation on function complexity Example 2-bit comparator: A B = C D and A B > C D implemented with 1 CLB (GT) F = A C' + A B D' + B C' D' (EQ) G = A'B'C'D'+ A'B C'D + A B'C D'+ A B C D Can implement some functions of > 5 input

Xilinx FPGAs -

Xilinx FPGA Combinational Logic

Examples N-input majority function: 1 whenever n/2 or more inputs are 1 N-input parity functions: 5 input/1 CLB; 2 levels yield 25 5-input Majority inputs! Circuit
9 Input Parity Logic CL B CLB 7-input Majority Circuit CL B CL
Xilinx FPGAs - B

CLB

CL B

Xilinx FPGA Adder Example

Example 2-bit binary adder - inputs: A1, A0, B1, B0, CIN outputs: S0, S1, Cout A3 B3 A2 B2 A1 B1 A0 B0 Cin
CLB CLB CLB CLB

Full Adder, 4 CLB delays to final carry out

S0

Cout

S3

C2

S2

C1

S1

C0

A3 B3 A2 B2

A1 B1 A0 B0 Cin

CLB S3 Cout

S2

CLB S1 C2

S0

2 x Two-bit Adders (3 CLBs each) yields 2 CLBs to final carry out

Xilinx FPGAs -

Applications of FPGAs
Implementation of random logic

Prototyping

Easier changes at system-level (one device is modified) Can eliminate need for full-custom chips Ensemble of gate arrays used to emulate a circuit to be manufactured Get more/better/faster debugging done than with simulation One hardware block used to implement more than one function Functions must be mutually-exclusive in time Can greatly reduce cost while enhancing flexibility RAM-based only option Hardware dedicated to solving one problem (or class of problems) Accelerators attached to general-purpose computers

Reconfigurable hardware

Special-purpose computation engines

Xilinx FPGAs -