CPRE 583 Reconfigurable Computing Lecture 2: 8/26/2011 (VHDL Overview 1 )

Instructor: Dr. Phillip Jones

(phjones@iastate.edu) Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA http://class.ece.iastate.edu/cpre583/

1 - CPRE 583 (Reconfigurable Computing): VHDL overview 1

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Overview
VHDL review 1
Highly recommend VHDL tutorial
120 pages with a LOT of examples
http://courseware.ee.calpoly.edu/~bmealy/shock_awe_vhdl_adobe.pdf

Quick reference
http://hapssupportnet.synplicity.com/download/VHDL-Handbook.pdf (quick ref)

Some links other VHDL tutorials

http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html http://www.vhdl-online.de/tutorial/

HW 1 overview

2 - CPRE 583 (Reconfigurable Computing): VHDL overview 1

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VHDL basics
VHDL: (V)HSIC (H)ardware (D)escription (L)anguage VHSIC: (V)ery (H)igh (S)peed (I)ntegrated (C)ircuit It is NOT a programming language!!!

It is a Hardware Description Language (HDL)

Conceptually VERY different form C,C++

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Some Key Differences from C

C is inherently sequential (serial), one statement executed at a time VHDL is inherently concurrent (parallel), many statements executed at a time

4 - CPRE 583 (Reconfigurable Computing): VHDL overview 1

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Some Key Differences from C

C example
Initially: A,B,C,X,Y,Z,Ans =1 A=B+C X=Y+Z Ans = A + X A <= B + C X <= Y + Z Ans <= A + X

VHDL example

Current Values: A=1 B=1 C=1 X=1 Y=1 Z=1 Ans = 1

5 - CPRE 583 (Reconfigurable Computing): VHDL overview 1

Current Values: A=1 B=1 C=1 X=1 Y=1 Z=1 Ans = 1

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Some Key Differences from C

C example
Initially: A,B,C,X,Y,Z,Ans =1 A=B+C X=Y+Z Ans = A + X A <= B + C X <= Y + Z Ans <= A + X

VHDL example

Current Values: A=2 B=1 C=1 X=1 Y=1 Z=1 Ans = 1

6 - CPRE 583 (Reconfigurable Computing): VHDL overview 1

Current Values: A=1 B=1 C=1 X=1 Y=1 Z=1 Ans = 1

Iowa State University (Ames)

Some Key Differences from C

C example
Initially: A,B,C,X,Y,Z,Ans =1 A=B+C X=Y+Z Ans = A + X A <= B + C X <= Y + Z Ans <= A + X

VHDL example

Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 1

7 - CPRE 583 (Reconfigurable Computing): VHDL overview 1

Current Values: A=1 B=1 C=1 X=1 Y=1 Z=1 Ans = 1

Iowa State University (Ames)

Some Key Differences from C

C example
Initially: A,B,C,X,Y,Z,Ans =1 A=B+C X=Y+Z Ans = A + X A <= B + C X <= Y + Z Ans <= A + X

VHDL example

Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 4

8 - CPRE 583 (Reconfigurable Computing): VHDL overview 1

Current Values: A=1 B=1 C=1 X=1 Y=1 Z=1 Ans = 1

Iowa State University (Ames)

Some Key Differences from C

C example
Initially: A,B,C,X,Y,Z,Ans =1 A=B+C X=Y+Z Ans = A + X A <= B + C X <= Y + Z Ans <= A + X Simulates in parallel ever delta time step

VHDL example

Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 4

9 - CPRE 583 (Reconfigurable Computing): VHDL overview 1

Current Values: A=1 B=1 C=1 X=1 Y=1 Z=1 Ans = 1

Iowa State University (Ames)

Some Key Differences from C

C example
Initially: A,B,C,X,Y,Z,Ans =1 A=B+C X=Y+Z Ans = A + X

VHDL example
Snap shot after input change A <= B + C X <= Y + Z Ans <= A + X Simulates in parallel ever delta time step

Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 4

10 - CPRE 583 (Reconfigurable Computing): VHDL overview 1

Current Values: A=1 B=1 C=1 X=1 Y=1 Z=1 Ans = 1

Iowa State University (Ames)

Some Key Differences from C

C example
Initially: A,B,C,X,Y,Z,Ans =1 A=B+C X=Y+Z Ans = A + X A <= B + C X <= Y + Z Ans <= A + X Simulates in parallel ever delta time step

VHDL example

Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 4

11 - CPRE 583 (Reconfigurable Computing): VHDL overview 1

Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 2

Iowa State University (Ames)

Some Key Differences from C

C example
Initially: A,B,C,X,Y,Z,Ans =1 A=B+C X=Y+Z Ans = A + X A <= B + C X <= Y + Z Ans <= A + X Simulates in parallel ever delta time step

VHDL example

Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 4

Different

Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 2

Iowa State University (Ames)

12 - CPRE 583 (Reconfigurable Computing): VHDL overview 1

Some Key Differences from C

C example
Initially: A,B,C,X,Y,Z,Ans =1 A=B+C X=Y+Z Ans = A + X

VHDL example
Snap shot after input change A <= B + C X <= Y + Z Ans <= A + X Simulates in parallel ever delta time step

Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 4

13 - CPRE 583 (Reconfigurable Computing): VHDL overview 1

Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 2

Iowa State University (Ames)

Some Key Differences from C

C example
Initially: A,B,C,X,Y,Z,Ans =1 A=B+C X=Y+Z Ans = A + X A <= B + C X <= Y + Z Ans <= A + X Simulates in parallel ever delta time step

VHDL example

Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 4

14 - CPRE 583 (Reconfigurable Computing): VHDL overview 1

Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 2

Iowa State University (Ames)

Some Key Differences from C

C example
Initially: A,B,C,X,Y,Z,Ans =1 A=B+C X=Y+Z Ans = A + X A <= B + C X <= Y + Z Ans <= A + X Simulates in parallel ever delta time step

VHDL example

Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 4

15 - CPRE 583 (Reconfigurable Computing): VHDL overview 1

Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 4

Iowa State University (Ames)

Some Key Differences from C

C example
Initially: A,B,C,X,Y,Z,Ans =1 Ans = A + X A=B+C X=Y+Z Change order of statements Ans <= A + X A <= B + C X <= Y + Z

VHDL example

Current Values: A=1 B=1 C=1 X=1 Y=1 Z=1 Ans = 1

16 - CPRE 583 (Reconfigurable Computing): VHDL overview 1

Current Values: A=1 B=1 C=1 X=1 Y=1 Z=1 Ans = 1

Iowa State University (Ames)

Corresponding circuit
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Simulates in parallel ever delta time step

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Corresponding circuit
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Simulates in parallel ever delta time step

B(1)

C(1)
Y(1) Z(1)

+ +

A(1)

+
X(1)

Ans(1)

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Corresponding circuit
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Simulates in parallel ever delta time step

B(1)

C(1)
Y(1) Z(1)

+ +

A(2)

+
X(2)

Ans(2)

19 - CPRE 583 (Reconfigurable Computing): VHDL overview 1

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Corresponding circuit
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Simulates in parallel ever delta time step

B(1)

C(1)
Y(1) Z(1)

+ +

A(2)

+
X(2)

Ans(4)

20 - CPRE 583 (Reconfigurable Computing): VHDL overview 1

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Corresponding circuit (More realistic)

VHDL example
Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C after 2ns X <= Y + Z after 2ns Ans <= A + X after 2ns Simulates in parallel ever delta time step

B(1)

C(1)
Y(1) Z(1)

+
2ns

A(1)

+
X(1) 2ns

Ans(1)

+
2ns

21 - CPRE 583 (Reconfigurable Computing): VHDL overview 1

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Corresponding circuit (More realistic)

VHDL example
Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C after 2ns X <= Y + Z after 2ns Ans <= A + X after 2ns Simulates in parallel ever delta time step

B(1)

C(1)
Y(1) Z(1)

+
2ns

A(2)

+
X(2) 2ns

Ans(2)

+
2ns

22 - CPRE 583 (Reconfigurable Computing): VHDL overview 1

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Corresponding circuit (More realistic)

VHDL example
Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C after 2ns X <= Y + Z after 2ns Ans <= A + X after 2ns Simulates in parallel ever delta time step

B(1)

C(1)
Y(1) Z(1)

+
2ns

A(2)

+
X(2) 2ns

Ans(4)

+
2ns

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Typical Structure of a VHDL File

LIBRARY ieee; ENTITY test_circuit IS PORT(B,C,Y,Z,Ans); END test_circuit; Include Libraries Define component name and Input/output ports

Declare internal ARCHITECTURE structure OF test_circuit IS signal A : std_logic_vector(7 downto 0); signals, signal X : std_logic_vector(7 downto 0); components BEGIN

A <= B + C; X <= Y + Z; Ans <= A + X;

END
24 - CPRE 583 (Reconfigurable Computing): VHDL overview 1

Implement components functionality

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Process
Process provide a level serialization in VHDL (e.g. variables, clocked processes) Help separate and add structure to VHDL design

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Process Example
BEGIN My_process_1 : process (A,B,C,X,Y,Z) Begin Sensitivity list: specify inputs to the A <= B + C; process. Process is updated when X <= Y + Z; a specified input changes Ans <= A + X; End My_process_1; My_process_2 : process (B,X,Y,Ans1) Begin A <= B + 1; X <= B + Y; Ans2 <= Ans1 + X; End My_process_2; END;
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Process Example (Multiple Drivers)

BEGIN My_process_1 : process (A,B,C,X,Y,Z) Begin A <= B + C; X <= Y + Z; Ans <= A + X; End My_process_1; My_process_2 : process (B,X,Y,Ans1) Begin A <= B + 1; X <= B + Y; Ans2 <= Ans1 + X; End My_process_2; END;
27 - CPRE 583 (Reconfigurable Computing): VHDL overview 1

A signal can only be Driven (written) by one process. But can be read by many Compile or simulator may give a multiple driver Error or Warning message

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Process Example (Multiple Drivers)

BEGIN My_process_1 : process (A,B,C,X,Y,Z) Begin A <= B + C; X <= Y + Z; Ans <= A + X; End My_process_1; My_process_2 : process (B,X,Y,Ans1) Begin Maybe A,X were suppose to be A1,X1. Cut A1 <= B + 1; and paste error. Or may need to rethink X1 <= B + Y; Hardware structure to remove multiple driver Ans2 <= Ans1 + X; issue. End My_process_2; END;
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Process Example (if-statement)

BEGIN My_process_1 : process (A,B,C,X,Y,Z) Begin if (B = 0) then C <= A + B; Z <= X + Y; Ans1 <= A + X; else C <= 1; Z <= 0; Ans1 <= 1; end if; End My_process_1; END;

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Clock Process Example

BEGIN My_process_1 : process (clk) Begin IF (clkevent and clk = 1) THEN C <= A or B; Z <= X or Y; Ans <= C and Z; END IF; circuit not clocked End My_process_1; A() B() X() Y() END;
30 - CPRE 583 (Reconfigurable Computing): VHDL overview 1

or

C()

and or
Z()

Ans()

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Clock Process Example

BEGIN My_process_1 : process (clk) Begin IF (clkevent and clk = 1) THEN C <= A or B; Z <= X or Y; Ans <= C and Z; END IF; circuit with clock End My_process_1; A() B() X() Y() END; clk
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31 - CPRE 583 (Reconfigurable Computing): VHDL overview 1

D Flip-Flop DFF Register

or

C()

and or
Z()

Ans()

Clock Process Example

BEGIN My_process_1 : process (clk) Begin IF (clkevent and clk = 1) THEN C <= A or B; Z <= X or Y; Ans <= C and Z; END IF; End My_process_1; clk END; circuit with clock A() B() X() Y()

or

C()

and or
Z()

Ans()

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Clock Process Example 2

BEGIN My_process_1 : process (clk) Begin IF (clkevent and clk = 1) THEN C <= A xor B; Z <= X or Y; Ans <= C xor Z; END IF; End My_process_1; clk END; circuit with clock A() B() X() Y()

xor

C()

xor or
Z()

Ans()

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Clock Process Example 2 (Answer)

BEGIN My_process_1 : process (clk) Begin IF (clkevent and clk = 1) THEN C <= A xor B; Z <= X or Y; Ans <= C xor Z; END IF; End My_process_1; clk END; circuit with clock A() B() X() Y()

xor

C()

xor or
Z()

Ans()

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VHDL Constructs
Entity Process Signal, Variable, Constants, Integers Array, Record

VHDL on-line tutorials: http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html http://www.vhdl-online.de/tutorial/

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Signals and Variables

Signals Updated at the end of a process Have file scope Variables Updated instantaneously Have process scope

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std_logic, std_logic_vector
Very common data types std_logic Single bit value Values: U, X, 0, 1, Z, W, H, L, Example: signal A : std_logic;
A <= 1;

Std_logic_vector: is an array of std_logic Example: signal A : std_logic_vector (4 downto 0); A <= x00Z001

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Std_logic values Std_logic values

U : Uninitialized (signal has not been assigned a value yet) X : Unknow (2 drivers one 0 one 1) H : weak 1 (example: model pull-up resister)
I have never used this value

L : weak 0

Time step 0
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Std_logic values Std_logic values

U : Uninitialized (signal has not been assigned a value yet) X : Unknow (2 drivers one 0 one 1) H : weak 1 (example: model pull-up resister)
I have never used this value

L : weak 0

Time step 0
39 - CPRE 583 (Reconfigurable Computing): VHDL overview 1

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Std_logic values Std_logic values

U : Uninitialized (signal has not been assigned a value yet) X : Unknow (2 drivers one 0 one 1) H : weak 1 (example: model pull-up resister)
I have never used this value

L : weak 0

Time step 1
40 - CPRE 583 (Reconfigurable Computing): VHDL overview 1

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Std_logic values Std_logic values

U : Uninitialized (signal has not been assigned a value yet) X : Unknow (2 drivers one 0 one 1) H : weak 1 (example: model pull-up resister)
I have never used this value

L : weak 0

Time step 2
41 - CPRE 583 (Reconfigurable Computing): VHDL overview 1

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Std_logic values Std_logic values

U : Uninitialized (signal has not been assigned a value yet) X : Unknow (2 drivers one 0 one 1) H : weak 1 (example: model pull-up resister)
I have never used this value

L : weak 0

Time step 3
42 - CPRE 583 (Reconfigurable Computing): VHDL overview 1

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Std_logic values Std_logic values

U : Uninitialized (signal has not been assigned a value yet) X : Unknow (2 drivers one 0 one 1) H : weak 1 (example: model pull-up resister)
I have never used this value

L : weak 0
0
1

Time step 3
43 - CPRE 583 (Reconfigurable Computing): VHDL overview 1

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Std_logic values Std_logic values

U : Uninitialized (signal has not been assigned a value yet) X : Unknow (2 drivers one 0 one 1) H : weak 1 (example: model pull-up resister)
I have never used this value

L : weak 0
0
1

Time step 3
44 - CPRE 583 (Reconfigurable Computing): VHDL overview 1

1
Iowa State University (Ames)

Std_logic values Std_logic values

U : Uninitialized (signal has not been assigned a value yet) X : Unknow (2 drivers one 0 one 1) H : weak 1 (example: model pull-up resister)
I have never used this value

L : weak 0
0
0

Time step 3
45 - CPRE 583 (Reconfigurable Computing): VHDL overview 1

1
Iowa State University (Ames)

Std_logic values Std_logic values

U : Uninitialized (signal has not been assigned a value yet) X : Unknow (2 drivers one 0 one 1) H : weak 1 (example: model pull-up resister)
I have never used this value

L : weak 0
1 Pull-up resistor

Time step 0
46 - CPRE 583 (Reconfigurable Computing): VHDL overview 1

Iowa State University (Ames)

Std_logic values Std_logic values

U : Uninitialized (signal has not been assigned a value yet) X : Unknow (2 drivers one 0 one 1) H : weak 1 (example: model pull-up resister)
I have never used this value

L : weak 0
1 Pull-up resistor

Time step 0
47 - CPRE 583 (Reconfigurable Computing): VHDL overview 1

Iowa State University (Ames)

Std_logic values Std_logic values

U : Uninitialized (signal has not been assigned a value yet) X : Unknow (2 drivers one 0 one 1) H : weak 1 (example: model pull-up resister)
I have never used this value

L : weak 0
1 Pull-up resistor

Time step 1
48 - CPRE 583 (Reconfigurable Computing): VHDL overview 1

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Std_logic values Std_logic values

U : Uninitialized (signal has not been assigned a value yet) X : Unknow (2 drivers one 0 one 1) H : weak 1 (example: model pull-up resister)
I have never used this value

L : weak 0
1 Pull-up resistor

Resolution(H,0) = 0
0 1

Time step 2
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Pre-defined VHDL attributes

mysignalevent (mysignal changed value) mysignalhigh (highest value of mysignals type) mysignallow Many other attributes
http://www.cs.umbc.edu/help/VHDL/summary.html

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Singal vs Varible scope

Signal: global to file Variable: local to process
My_process_1 : process (B,C,Y) Begin A <= B + C; Z <= Y + C; End My_process_1; My_process_2 : process (B,X,Y,Ans1) Begin X <= Z + 1; Ans <= B + Y; End My_process_2;

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Singal vs Varible scope

Signal: global to file Variable: local to process
My_process_1 : process (B,C,Y) Begin A <= B + C; varZ <= Y + C; End My_process_1; My_process_2 : process (B,X,Y,Ans1) Begin X <= varZ + 1; Ans <= B + Y; End My_process_2;

Each varZ are local to their process. Completely independent

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Arrays and Records

Arrays: Group signals of the same type together Records: Group signal of different types together

VHDL on-line tutorials: http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html http://www.vhdl-online.de/tutorial/

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Array Example (Delay Shift Register)

flag_in flag_1 flag_2 flag_3 flag_out

BEGIN My_process_1 : process (clk) Begin IF (clkevent and clk = 1) THEN flag_1 <= flag_in; flag_2 <= flag_1; flag_3 <= flag_2; END IF; End My_process_1; flag_out <= flag_3 END;

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Array Example (Delay Shift Register)

flag_in flag_1 flag_20 flag_out

BEGIN My_process_1 : process (clk) Begin IF (clkevent and clk = 1) THEN flag_1 <= flag_in; flag_2 <= flag_1; flag_20 <= flag_19; END IF; End My_process_1; flag_out <= flag_20 END;

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Array Example (Delay Shift Register)

flag_in flag_1 flag_20 flag_out

type flag_reg_array is array (DELAY-1 downto 0) of std_logic; signal flag_reg : flag_reg_array; BEGIN My_process_1 : process (clk) Begin IF (clkevent and clk = 1) THEN flag_reg(flag_reg'high downto 0) <= flag_reg(flag_reg'high-1 downto 0) & flag_in; END IF; End My_process_1; flag_out <= flag_reg(flag_reg'high); END;

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Array Example (Delay Shift Register)

flag_reg(flag_reg'high downto 0)<= flag_reg(flag_reg'high-1 downto 0) & flag_in; flag_in flag(0) 0 0 flag(1) 1 flag(2) flag_out

flag_in 1 0

flag(0) 0

flag(1) 1

flag(2) flag_out

flag_in 1

flag(0) 0

flag(1) 0

flag(2) flag_out

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Detailed in class design next Friday

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HW1

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Questions/Comments/Concerns

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