Converting Binary (2’s C) to Decimal

1. If leading bit is one, take two’s complement n 2n

to get a positive number. 0 1
2. Add powers of 2 that have “1” in the 1 2
2 4
corresponding bit positions.
3 8
3. If original number was negative, 4 16
add a minus sign. 5 32
X = 01101000two 6 64
7 128
= 26+25+23 = 64+32+8
8 256
= 104ten 9 512
Assuming 8-bit 2’s complement numbers. 10 1024
 More Examples
X = 00100111two
= 25+22+21+20 = 32+4+2+1 n 2n
= 39ten 0 1
1 2
2 4
X = 11100110two
3 8
-X = 00011010 4 16
= 24+23+21 = 16+8+2 5 32
= 26ten 6 64
7 128
X = -26ten 8 256
9 512
Assuming 8-bit 2’s complement numbers. 10 1024
 Converting Decimal to Binary (2’s C)
• First Method: Division
2. Divide by two – remainder is least significant bit.
3. Keep dividing by two until answer is zero,
writing remainders from right to left.
4. Append a zero as the MS bit;
if original number negative, take two’s complement.
X = 104ten 104/2 = 52 r0 bit 0
52/2 = 26 r0 bit 1
26/2 = 13 r0 bit 2
13/2 = 6 r1 bit 3
6/2 = 3 r0 bit 4
3/2 = 1 r1 bit 5
X = 01101000two 1/2 = 0 r1 bit 6
 Converting Decimal to Binary (2’s C)
• Second Method: Subtract Powers of Two n 2n
• Change to positive decimal number. 0 1
• Subtract largest power of two 1 2
less than or equal to number. 2 4
• Put a one in the corresponding bit position. 3 8
4 16
• Keep subtracting until result is zero. 5 32
• Append a zero as MS bit; 6 64
if original was negative, take two’s complement. 7 128
8 256
X = 104ten 104 - 64 = 40 bit 6
9 512
40 - 32 = 8 bit 5
8-8 = 0 bit 3 10 1024
X = 01101000two
 Operations: Arithmetic and Logical
a data type includes representation and operations.
•We now have a good representation for signed integers,
so let’s look at some arithmetic operations:
– Addition
– Subtraction
– Sign Extension
•We’ll also look at overflow conditions for addition.
•Logical operations are also useful:
– AND
– OR
– NOT
 Addition
• 2’s comp. addition is just binary addition.
– assume all integers have the same number of bits
– ignore carry out
– for now, assume that sum fits in n-bit 2’s comp.
representation

01101000 (104) 11110110 (-10)

+ 11110000 (-16) + (-9)
01011000 (98) (-19)
Assuming 8-bit 2’s complement numbers.
 Subtraction
•Negate subtrahend (2nd no.) and add.
– assume all integers have the same number of bits
– ignore carry out
– for now, assume that difference fits in n-bit 2’s comp.
representation
01101000 (104) 11110110 (-10)
- 00010000 (16) - (-9)
01101000 (104) 11110110 (-10)
+ 11110000 (-16) + (9)
01011000 (88) (-1)
Assuming 8-bit 2’s complement numbers.
 Sign Extension

•To add two numbers, we must represent them

with the same number of bits.
•If we just pad with zeroes on the left:

4-bit 8-bit
0100 (4) 00000100 (still 4)
1100 (-4) 00001100 (12, not -4)
•Instead, replicate the MS bit -- the sign bit:

4-bit 8-bit
0100 (4) 00000100 (still 4)
1100 (-4) 11111100 (still -4)
 Overflow
•If operands are too big, then sum cannot be represented as an
n-bit 2’s comp number.
01000 (8) 11000 (-8)
+ 01001 (9) + 10111 (-9)
10001 (-15) 01111 (+15)
•We have overflow if:
– signs of both operands are the same, and
– sign of sum is different.
•Another test -- easy for hardware:
– carry into MS bit does not equal carry out
 Logical Operations

•Operations on logical TRUE or FALSE

– two states -- takes one bit to represent: TRUE=1,
FALSE=0
•View n-bit number as a collection of n logical values
– operation applied to each bit independently
A B A AND B A B A OR B A NOT A
0 0 0 0 0 0 0 1
0 1 0 0 1 1 1 0
1 0 0 1 0 1
1 1 1 1 1 1
 Examples of Logical Operations

•AND
– useful for clearing bits 11000101
• AND with zero = 0 AND 00001111
• AND with one = no change 00000101
•OR 11000101
– useful for setting bits OR 00001111
• OR with zero = no change 11001111
• OR with one = 1
•NOT NOT 11000101
– unary operation -- one argument 00111010
– flips every bit
Digital Logic
Structures
Transistor: Building Block of Computers
•Microprocessors contain millions of transistors
– Intel Pentium II: 7 million
– Compaq Alpha 21264: 15 million
– Intel Pentium III: 28 million
– Intel Pentium IV: 42 million
•Logically, each transistor acts as a switch, meaning that
we can operate it at either saturation or cutoff but nowhere
else along the load line. When saturated, a transistor is like
a closed switch. When cutoff, it’s like an open switch.
•Combined to implement logic functions
– AND, OR, NOT
•Combined to build higher-level structures
– Adder, multiplexer, decoder, register, …
 Simple Switch Circuit

•Switch open:
– No current through circuit
– Light is off
– Vout is +2.9V
•Switch closed:
– Short circuit across switch
– Current flows
– Light is on
– Vout is 0V
Switch-based circuits can easily represent two states:
on/off, open/closed, voltage/no voltage.
Basic Logic Gates
 More than 2 Inputs?
•AND/OR can take any number of inputs.
– AND = 1 if all inputs are 1.
– OR = 1 if any input is 1.
– Similar for NAND/NOR.

•Can implement with multiple two-input gates.

 Logical Completeness
•Can implement ANY truth table with AND, OR, NOT.

A B C D
0 0 0 0 1. AND combinations
that yield a "1" in the
0 0 1 0 truth table.
0 1 0 1
0 1 1 0
2. OR the results
1 0 0 0 of the AND gates.
1 0 1 1
D = A . B . C + A . B. C
1 1 0 0
1 1 1 0
 Practice
•Implement the following truth table.
A B C
0 0 0
0 1 1
1 0 1
1 1 0
• Implement the following Expression.
Y = A + AB + AB
 DeMorgan's Laws
Law I: AB = A + B

Input Intermediate Value Output

A B AB A B AB A+B
0 0 0 1 1 1 1
0 1 0 1 0 1 1
1 0 0 0 1 1 1
1 1 1 0 0 0 0
 DeMorgan's Laws
Law II: A+B=A.B

Input Intermediate Value Output

A B A+B A B A+B A.B

0 0 0 1 1 1 1
0 1 1 1 0 0 0
1 0 1 0 1 0 0
1 1 1 0 0 0 0
 Building Functions from Logic Gates
•We've already seen how to implement truth tables
using AND, OR, and NOT -- an example of
combinational logic.
•Combinational Logic Circuit
– output depends only on the current inputs
– stateless
•Sequential Logic Circuit
– output depends on the sequence of inputs (past and
present)
– stores information (state) from past inputs
•We'll first look at some useful combinational circuits,
then show how to use sequential circuits to store information.
 Decoders
• Definition:
It is a type of circuit that produces one or
more selected output signals based on the
combination of input signals it receives.
 Decoder
•n inputs, 2n outputs
– exactly one output is 1 for each possible input pattern

2-bit
decoder
 Multiplexer
• A multiplexer is a circuit with many inputs
but only one output. By applying control
signals, we can steer any input to the
output. The circuit has n input signals, m
control signals, and 1 output. Multiplex
means many into one.
 Multiplexer (MUX)
•n-bit selector and 2n inputs, one output
– output equals one of the inputs, depending on selector

4-to-1 MUX
 Adder Circuits
• A Half Adder is a circuit which adds two
binary digit at a time.
• A Half Adder has only two inputs and there
is no provision to add a carry coming from
the lower order bit when multi-bit addition
is performed.
• A Full Adder is used to perform multi-bit
addition.
 Full Adder
•Add two bits and carry-in,
produce one-bit sum and carry-out.
A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
 Combinational
•Combinational Circuit
vs. Sequential
– always gives the same output for a given set of inputs
• ex: adder always generates sum and carry,
regardless of previous inputs
•Sequential Circuit
– stores information
– output depends on stored information (state) plus input
• so a given input might produce different outputs,
depending on the stored information
– example: ticket counter
• advances when you push the button
• output depends on previous state
– useful for building “memory” elements and “state machines”
 Latch
• The latch is a electronic circuit used to store
information in asynchronous sequential
logic systems. One latch can store one bit of
information. Latches often occur in
multiples, some of which have special
names, such as the 'quad latch' (which can
store four bits) and the 'octal latch' (eight
bits).
 R-S Latch: Simple Storage Element
•R is used to “reset” or “clear” the element – set it to zero.
•S is used to “set” the element – set it to one.
1 1
0 1 1 0
1

1 0 0 1
0
1 1

•If both R and S are one, out could be either zero or one.
– “quiescent” state -- holds its previous value
– note: if a is 1, b is 0, and vice versa
 Clearing the R-S latch
•Suppose we start with output = 1, then change R to zero.
1
0 1
1

1 0
0
1 Output changes to zero.
1
1 0
1

0 1
0
0

Then set R=1 to “store” value in quiescent state.

 Setting the R-S Latch
•Suppose we start with output = 0, then change S to zero.
1
1 0

0 1

1 Output changes to one.

0
0 1

1 0

Then set S=1 to “store” value in quiescent state.

 R-S Latch Summary
•R = S = 1
– hold current value in latch
•S = 0, R=1
– set value to 1
•R = 0, S = 1
– set value to 0

•R = S = 0
– both outputs equal one
– final state determined by electrical properties of gates
– Don’t do it!
 Gated D-Latch
•Two inputs: D (data) and WE (write enable)
– when WE = 1, latch is set to value of D
• S = NOT(D), R = D
– when WE = 0, latch holds previous value
• S=R=1
 Register
•A register stores a multi-bit value.
– We use a collection of D-latches, all controlled by a common
WE.
– When WE=1, n-bit value D is written to register.