Overview of verilog as an HDL

Easy to learn and use Syntax is Similar in C language Design can be described at a very abstract level Functional verification of the design can be done early in the design cycle Results of verilog are based on the GIGO principle
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What can we do with Verilog?

Model digital circuits Simulate and verify digital logic circuits Synthesis digital logic circuits

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What can we do with Verilog?

Model Digital Logic Circuits

Behavioral

Level modeling RTL Level modeling Gate Level modeling Mixed Level modeling

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What can we do with Verilog?

Simulate and verify large digital circuits

Test

benches Bus-Functional models Observability Full Timing Simulation

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What can we do with Verilog?

Synthesize Digital Logic Circuits

Basics

of RTL coding- a subset of Verilog Combinational Circuits Sequential Circuits

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Prerequisites of High Level Design

Who should take this course:

If

you need to synthesize, model, simulate or verify a design with a high-degree of confidence If you need to use high-level practices If you have no or very little prior knowledge of the fundamentals of Verilog

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Introduction to High Level Design

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High Level Design

Top Down Methodology Ex- 4 bit parallel adder

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High Level Design

Bottom Up Methodology

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The Architecture

Verilog model
Behavioral model (The Hierarchy)

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Introduction to Verilog

Grammar Notation Placeholder for other grammatical elements

<placeholder>

Optional element
[optional]

Repeated Element
{repeated}

Brackets not part of the final Verilog

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Basic Unit

Module Syntax: Example:

module <name>; endmodule module halfadder; endmodule

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Syntax rules

Case Sensitive Reserved word in lowercase Guideline:

User-defined

identifiers that help others easily

recognize what you are doing. Make your code in such a manner as you would like to get it if you were to inherit it from someone else ha_case, ha_if_else Vs simply ha

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Syntax rules

module ha; endmodule

Cannot used as user identifiers For the list of reserved words, look in most any verilog text book
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Syntax rules
User defined identifiers
module hAder; endmodule module hader; endmodule Module haDEr; endmodule 3 different module

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Syntax rules

User identifiers
a-z, 0-9 and _ Must start with Letter Examples:
Characters A-Z,

Invalid identifiers module 8add; endmodule Module one+two; endmodule

module add8; endmodule module ATM_SWITCH; endmodule

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Syntax rules

Indentation is not significant Line break is not significant Guidelines:

Indent to show flow Break the line where convenient

module ha; endmodule module ha; endmodule

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Comments

Block Comments
Start

with /* End with */ Cannot be nested

/* * This module does * */

Line Comments
Start

with // End at end of line

module ha; ----------vellore // endmoule

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