ASIC DESIGN

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 Agenda

 Introduction
 VLSI Design methodologies
 Review of MOS Transistor Theory
 Inverter – Nucleus of Digital Integrated
Electronics
 Static CMOS Logic Circuits
 Mask Design

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 Introduction To VLSI

 Historical Perspective
 Field of Microelectronics
 Levels of Integration
 Terminology
 IC Products
 References

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 Historical Perspective

 1930 - O.Heil and Lilienfeld – FET

 1947 – Bardeen, Brattain and Shockley, AT & T
Bell Labs, - BJT
 1958 – Jack Kilby, Texas Instruments ,Hybrid
IC
 Jack Kilby was awarded the year 2000 Nobel
prize

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 Nature of the subject

 Digital ASIC back end bridges the gap

between the gate level logic and the
semiconductor physics.

 ‘Analog’ in nature.

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 Introduction To VLSI

 Historical Perspective
 Field of Microelectronics
 Levels of Integration
 Terminology
 IC Products
 References

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 Filed of Microelectronics

MICROELECTRONICS

INERT SUBSTRATE ACTIVE SUBSTRATE

Thick Film Thin Film

Circuits Circuits
Silicon Gallium
Arsenide

MOS Bipolar MESFET Bipolar

TTL

NMOS PMOS CMOS

I2 L

Bi-CMOS
ECL

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 Introduction To VLSI

 Historical Perspective
 Field of Microelectronics
 Levels of Integration
 Terminology
 IC Products
 References

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 Levels of Integration

Level of Number Typical

Integration of Gates Applications
SSI 1-10 Basic Gates
MSI 10-100
Counters,Decoder,
Encoder
LSI 100-1000 Memories,
ADC/DAC
VLSI 1000-10,000 MPU’s
ULSI 10,000-100,000
Manav Tyagi DSP, DEC 9
 Introduction To VLSI

 Historical Perspective
 Field of Microelectronics
 Levels of Integration
 Terminology
 IC Products
 References

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 Terminology/Jargons/Buzz words

 Feature Size – Approximately one half the

length of the smallest transistor used or
smallest interconnect realizable on the chip.
Ex: 0.5u process => Smallest transistor has a
length of 0.5um => Feature size of 0.25u.

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Feature Size

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 Terminology/Jargons/Buzz words

 Manufacturing Lead Time(Turnaround Time)

– The time it takes to make an IC excluding the
design time.
 Integrated Circuit – Combination of circuit
elements inseparably associated on or within a
substrate.
 Substrate – Supporting material.
 Monolithic IC – An IC whose elements are
formed on or within a substrate.
 Hybrid IC – Consists of a combination of two or
more ICs or an IC with some discrete
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 Terminology/Jargons/Buzz words

 Wafer(Slice) – Contains many ICs. Circular in

nature. Diameter – 4, 5, or 6 inches.
 Chip(die or bar) – Repeated ICs on a wafer.
 Test Plug(Process Control Bar Process
Control Monitor) - Special Chip Used to
monitor the process parameters of the
technology.Used to derive the timing models-
Wafer can be discarded.
 Test Cell (Test Lead ) - Inserted by the
designer to monitor the performance of
elementary sub circuits or subcomponents.
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Terminology/Jargons/Buzz words

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 Terminology/Jargons/Buzz words

 Defect Density - Lethal defects per cm2

 Yield - Yield = No. of Good Chips on a Wafer/Total
Number of Chips
 Seeds’s Model Y=e-√(A*D) A = Chip Area,
D=Defect Density
 Murphy’s Model Y= {[1-e-AD]/AD}2

 Utilization Factor - Utilization Factor = Used Chip

Area/Total Chip Area
 SOC- System On Chip
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 Introduction To VLSI

 Historical Perspective
 Field of Microelectronics
 Levels of Integration
 Terminology
 IC Products
 References

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 IC Products

 Standard Product
 ASIC
 ASSP

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 IC Products – Standard Product

 Multiple Vendors
 Multiple Customers
 Listed in data sheet
Ex: Memories, Microprocessors

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 IC Products – ASIC

 Specific for an application

 Single Vendor
 Single Customer
 Not listed in data book (Exceptions)

Ex: ICs for a satellite, toy application.

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 IC Products – Application
Specific Standard Product

 MODEM – Specific for an

application
 Multiple Vendors
 Multiple Customers
 Listed in a data book

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 References

 Semiconductor Devices Physics and

Technology – S.M.Sze
 VLSI Technology - S.M.Sze
 CMOS Digital Integrated Circuits – S.M.Kang
and Leblebici.
 Principles of CMOS VLSI Design – Neil.Weste
and K.Eshraghian.
 Fundamentals of MOS digital Integrated
Circuits – J.P.Uyemura.

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 References

 Low Power Digital CMOS Design - A.P.

Chandrakasan and R.W.Broderson
 Low Power Design Methodologies – J.M.Rabaey
and M.Pedram
 Digital Integrated Circuits – J.M.Rabaey
 ASICs – Sebastian Smith
 Algorithms for VLSI Physical Design Automation –
Naveed Sherwani

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 Journals

 IEEE JSSC
 IEEE Circuits and Systems
 SmartSpice User Manual
 VLSI Conference
 Custom Integrated Circuits Conference

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 Allied areas of microelectronics

 Low Power VLSI – Power Estimation and Power

Reduction
 High Speed Digital System Design
 Deep Sub-micron Issues
 Bi-CMOS VLSI

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VLSI Design
Methodologies

26
 Design Process

 Specification
 Algorithm
 Architectural Design
 RTL Design
 Gate Level Design
 Transistor Level Design
 Physical Design
 Fabrication and Testing

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 Design Flow

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 VLSI Design Styles

 Full Custom Design

 Semi-custom Design
Standard Cell Based Design
GA based
FPGA Based

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 Full Custom ASICs

 Entire Chip Designed at transistor level with

no standard cells
 Very high development cost
 Small die area, less power consumption,
high speed
 Suitable for large volume productions
 Used only if the ASIC technology is new or if
there are no existing cells

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 Full Custom Design

 Designer interfaces with the foundry and

optimizes the function and layout of practically
each transistor.
 Even non-conventional circuit shapes are
possible to save space on the chip.
 However it is a slow process.
 Growing Member of the family – Mixed signal
ASIC.

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 Full Custom Design

 Full custom design entails the complete design

of the circuit.
 All cells, circuit elements etc. are designed

by the designers right from scratch.

 Time taking approach.

 Some time Error prone.

 Expert designers can provide space efficient

designs. Can use novel techniques.

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 VLSI Design Styles

 Full Custom Design

 Semi-custom Design
Standard Cell Based Design
GA Based Design
FPGA Based Design

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 Semi-custom design

 Part of the design is already done. Other part

of the design is done by the designers.
 Results in the reuse of designs.
 Expert designers can focus their attention on
the designs that can be reused.
 Because of interfaces, certain disciplines are to
be maintained by the designers of the libraries.

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 VLSI Design Styles

 Full Custom Design

 Semi-custom Design
Standard Cell Based Design
GA based
FPGA Based

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 Standard Cell Based ASICs

 Also called POLYCELL based design.

 Specific designs for each IC can be developed and
stored in a cell library.
 Typical standard cell library contains
SSI Logic – nand, nor, xor, xnor, not, buffers,
latches
Each gate can have multiple
implementations.
MSI Logic –
Decoders,encoders,adders,comparators
Data Path Logic – ALUs, Adders, Shifters
Memories - RAM, ROMManav Tyagi 36
Standard Cell Based Design

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Standard Cell Based Design

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 Standard Cell Based Design

 The cells based black box designs are

available in the library.
 Circuits are then designed by the designers
wherein these elements are placed at various
places and appropriate terminals are
connected.
 Designers need to do only placement and
routing of the components.

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 Standard Cell Based Design

 Advantage to the designers

 Saves time. Only placement and routing is
needed.
 Cells are well tested by the cell library
provider (typically a design house within the
foundry).
 Approach is similar to the component
placement and routing on the PCB.
Certain disciplines have to be maintained.

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 Standard Cell Based Design

 In most cases, one can not place any wire over

the cell (available as a black box).
 Terminals are on the periphery. Terminal
definitions include
 Physical location, size and layer at which
available.
 Name of the terminal.

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 Standard Cell Based Design

in1 in2 out Terminals with the same name

Vdd Vdd are internally connected.
All cells are designed with
constant height. Butting two
cells together will connect their
Vdd and Vss together.
Vss
in1 in2 out
Vss Designer can provide i1 input to
either of the two in1 terminals.

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 Standard Cell Based Design

A row of standard cells

Channel for routing wires

Once placement is done, routing

problem is simplified to that of
A standard cell called channel routing.
feed-through is always Channel routing can be done using
needed in the cell two or three layers of wires.
library. Why? Manav Tyagi 43
 VLSI Design Styles

 Full Custom Design

 Semi-custom Design
Standard Cell Based Design
GA based
FPGA Based

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 Gate Array Based Design

 From the foundry viewpoint, standard cells are

similar to the custom design. In each case,
entire set of masks are to be prepared.
 In array based design, masks can be reused.
All the masks such as poly, diffusion, active
area etc. can be reused. Only the cuts and
metal masks are to be prepared.

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Gate Array Based ASICs

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 Gate Array based designs

Array cells

Routing
channel

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 Gate Arrays

 “Uncommitted Logic Arrays” or “Configurable

Logic Arrays” or “Master Slices” or “Logic
Arrays”
 Motorola 2500 cell ECL Array, AMD AM3525
 TelMOS mixed signal gate array
 Types of Gate Arrays
 Channeled Gate Array
 Channelless Gate Array
 Structured Gate Array

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 Channeled Gate
Array

 Interconnect is customised.
 Interconnect uses predefined spaces between
rows of base cells.
 Manufacturing lead time is two days to two
weeks.
 Similar to standard based semi-custom IC.
 Space for interconnect between rows of cells
are fixed in height in a channeled gate array
whereas the space between rows of cells may
be adjusted in a standard cell based IC.

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 Channelless Gate
Array

 Also called sea of gates.

 No predefined area set aside for routing
between the cells.
 Routing is done over the top of the devices.
 Logic Density is high.

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 Sea of
Gates
P+ shorting contacts
Vss

Ndiff

NW

Pdiff

Vdd
N+ shorting contacts
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 Structured Gate
Array

 Also called embedded gate array.

 Only the interconnect is customized.
 Manufacturing lead time is between two
days and two weeks.
 Custom Blocks can be embedded.
 Embedded function is fixed.

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 Gate Array Design
Steps

 Specification – Functionality, power, speed,area,

logic families
 Feasibility analysis, circuit analysis and
partitioning
 Cost, time, life cycle
 Choice of technology – CMOS,ECL,TTL
 Technology Conversion and Design for Testability
 TTL to CMOS Gate array circuit
 BIST
 Logic Coding and Verification
 What elements to be used and how they are
interconnected?
 Testability Analysis
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 Gate Array Design
Steps

 Mask Design – Manual, Interactive

 Place and Route – Auto

 3-5% routing has to be done manually

 Placement of critical blocks

 Processing, Packaging and Testing

 “Drop ins” placed in GA die for testing

 “Test Dies” are placed at strategic places on

each wafer

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 VLSI Design
Styles

 Full Custom Design

 Semi-custom Design
Standard Cell Based Design
GA based
FPGA Based

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 Programmable
ASICs

 PLDs
 FPGAs

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 P
LDs

 No custom mask layers or logic cells.

 Fast turnaround.
 A single large block of programmable
interconnect.
 Matrix of logic macrocells – programmable
array followed by flip flop or latch.

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 Programmable Logic
Devices

 ROM
 PROM
 EPROM
 EEPROM
 UVPROM
 PAL – Programmable OR, Fixed AND
 PLA – Programmable AND, Programmable OR
 Erasable PLD or Mask Programmed PLD

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 PLAs (NAND-
NAND)
4 inputs

Is a fuse.

3 outputs

Similarly NOR-NOR PLAs can be

designed.
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 Design
methodology

 Functional Specification – Truth tables, State

diagrams, schematic entry
 Generation of Boolean Equations
 Minimization of Boolean Equations
 Generation of fuse map – shows blown and
intact fuses
 Logic simulation – Function table with input
patterns and responses
 Programming the Selected device
 Testing the programmed device

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 PLD Design
Software

 Assemblers –PALASM(AMD), PLAN(NSC),

AMAZE(Signetics)
 Compilers - CUPL (Logic Devices), ABEL(Data
I/O)

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 Programmable Array
Logic

 Series 20 PAL – Monolithic Memories

 PAL10H8 – Ten inputs and 8 outputs, Active
high output
 PAL16RP8 -Registered

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 Automatic Generation of PLAs
in ICs

 PLA compilers can generate the layout of a PLA

given a combinatorial Boolean expression to
implement.
 These can then be used as a macro block in the
ICs even in standard cell based design.

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FPGA
Architecture

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Configurable Logic
Block

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 Xilinx
FPGAs

 XC2000 1.5k 16MHz

 XC3000 7.5k 50MHz
 XC4000 85k 80MHz 0.5u
 SPARTAN/SPARTAN XL 40k 100MHz+
0.35u
 XC5200 16k 50MHz 0.5u
 VIRTEX 1m 200MHz 0.25u
 SPARTAN – II 200k 200MHz 0.25u
 VIRTEX E 4m 250MHz 0.18u
 SPARTAN – IIE 200k 250+ 0.25u
 VIRTEX - II 8m 420MHz 0.15u
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 VIRTEX - II PRO 10m 420MHz
 Advantages of FPGAs over
ASICs

 Less Manufacturing Lead Time

 Less Risky
 Suitable for low volume productions

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 Design
Flow

 Front End Flow

 Back End Flow
 ASIC Flow

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 Front end flow (FPGA based
design)

 Functional Simulation – Active-HDL

 Synthesis – Synplify-Pro (EDIF)
 Place and Route – Xilinx Foundation Series
(.SDF)
 Timing Simulation – Active-HDL

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 Front end flow (FPGA based
design)

ALTERA APEX SERIES FPGA

 Functional Simulation – Active-HDL

 Synthesis – Synplify-Pro (EDIF)
 Place and route – Quartus (.vdo and
.sdo)
 Timing Simulation – Active-HDL

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 Back end
flow

 Circuit configuration and hand Calculation

 Schematic Capture – Gateway
 Functional Simulation –
SmartSpice/HarmonyAMS
 Physical Design – Expert
 Physical Verification – Guardian-DRC/LVS
 Parasitic Extraction – Hipex-NET/C/R/RC
 Back Annotation – SmartSpice/HarmonyAMS

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 Techniques to reduce
the
complexity of IC
design

 Hierarchy – Divide and conquer

 Regularity – Reusability – transistor level, gate
level
 Modularity – Debugging
 Locality – ‘Time locality’ – excessive interconnect
delays

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 Trends in VLSI

Increasing Interconnect Delay-60% of the path

delay
Increasing Interconnect Area – 30% of
microprocessor die area is meant for interconnect.
Increasing Number of Metal Layers – 12 layers of
copper -2010
Synthesis – Logic Synthesis and High Level
Synthesis

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IC Mask Design or Layout

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Silvaco Product Line

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