Chapter 6 Speed-Independent Control Circuits

Introduction Signal transition graphs The basic synthesis procedure Implementations using state-holding gates Initialization Summary of the synthesis process Petrify: A tool for synthesizing SI circuits from STGs Design examples using Petrify

Control Circuits

Many methods, tools, assumptions, frameworks Balsa generated both control and data-path We now consider one method / tool for control-only spec, verification and synthesis:

Assumption: Speed independent control for speed independent bundled data Method: Signal Transition Graph

A special type of Petri net

Tool: Petrify (mostly from Jordi Cortadella at UPC) Universitat Politecnica de Catalunya (Technical University of Catalonia, Barcelona, Spain)

Delay Models

Fixed delay: d=c Min-max delay: choose d[m,M]

Max delay: d[0,M] Low-bounded delay: d[m,)

Unbounded delay: d[0,) Pure delay (in VHDL = transport delay)

Simply shifts any signals waveform later in time Pulses shorter than the reject time are filtered out We dont assume inertial delays in async control design

Inertial delay: Glitches are filtered.

Hazards

Static-1 hazard

Desired signal: 1_1, actual signal: 1_101_1

Desired signal: 0_0, actual signal: 0_010_0 Desired signal: 1_1 0_0, actual signal: 1_1010_0 Desired signal: 0_0 1_1, actual signal: 0_0101_1

Static-0 hazard

Dynamic-10 hazard

Dynamic-01 hazard

Minimalist

A comprehensive CAD package for the automated synthesis and optimization of asynchronous controllers Principal Architects:

Book: Sequential Optimization of Asynchronous and

Robert Fuhrer Steven Nowick in Columbia Univ

Synchronous Finite-State Machines: Algorithms and Tools. Kluwer Academic Publishers, 2001.
(TK7868 .A79 F84) http://www1.cs.columbia.edu/~nowick/

Minimalist -- book chapters

Introduction (Async) Background (FSM) Burst-mode synthesis path walk-through CHASM: Optimal state assignment OPTIMIST: Optimal state minimization for synchronous FSMs OPTIMISTO: Synchronous state minimization for optimum output logic OPTIMISTA: Asynchronous state minimization for optimum output logic MINIMALIST: An extensible toolkit for burst-mode synthesis Conclusions

Petri net, Signal Transition Graph (STG)

Jordi Cortadella, Luciano Lavagno, and Alex Yakovlev, Advanced tutorial Hardware Design and Petri Nets, 21st Intl. Conf. on Application and theory of Petri Nets, 2000 Jordi Cortadella, M. Kishinevsky, A. Kondratyev, Luciano Lavagno, and Alex Yakovlev, Logic Synthesis for Asynchronous Controllers and Interface, Springer, 2002 (TK7868 .L6 L5864)

Advanced tutorial Hardware Design and Petri Nets

Introduction to hardware design and petri nets (0.5 hrs) Hardware modeling with petri nets (0.5 hrs) Direct synthesis of petri nets (0.5 hrs) Logic synthesis of async circuits from STGs (1.5 hrs) Analysis and verification (1 hr) Petri nets and hardware description languages (1.5 hrs) Performance analysis (0.5 hrs) Petri net models for quasi-static-scheduling (1 hr)

Logic Synthesis for Asynchronous Controllers and Interface

Introduction Design flow Background Logic synthesis State encoding Logic decomposition Synthesis with relative timing Design examples Other work Conclusions

The classic design process involves the following steps

The intended sequential circuit is specified in the form of a primitive flow table A minimum-row reduced flow table is obtained by merging compatible states in the primitive flow table The states are encoded Boolean equations for output variables and state variables are derived

The synthesis process involves the following steps

Specify the desired behavior of the circuit and its (dummy) environment using STG Check that the STG satisfies 5 properties Check that the specification satisfies complete state encoding Select an implementation template and derive the Boolean equations

The synthesis process involves the following steps

Derive the Boolean equations for the desired implementation template Manually modify the implementation such that the circuit can be forced into the desired initial state by an explicit reset or initialization signal Enter the design into a CAD tool and perform simulation and layout of the circuit

Petri net, Signal Transition Graph (STG)

a+

b+

a+

b+

c+

c+

a-

b-

a-

b-

cc-

Separating Inputs, Outputs and Internals

a+

b+

a+

b+

c+ acba-

c+ bc-

In the STG:

PN transition are signal transitions PN places and arcs are causal relations Simple places (one arc in, one arc out) are omitted MARKING
assignment of tokens to places state of the circuit

State Graph (SG)

000
State:

abc

a+

b+

100
b+

010
a+

110
c+

111
ab-

SG more complex than STG Bad for design spec Needed for synthesis

011
b-

101
a-

001
c-

State Graph (SG)

Quiescent Region QR(c=0)

000
a+ b+

100
b+

010
a+

Excitation Region ER(c=R)

110
c+

111
Quiescent Region QR(c=1)
ab-

011
b-

101
a-

Excitation Region ER(c=F)

001
c-

State Graph (SG)

000
a+ b+

Quiescent Region QR(c=0)

KEEP C=0

100
b+

010
a+

Excitation Region ER(c=R)

110
c+

SET C

111
ab-

Quiescent Region QR(c=1)

KEEP C=1

011
b-

101
a-

Excitation Region ER(c=F)

001
c-

RESET C

Synthesis: C Element

Two methods:

Using gates Using SR latch

Synthesis: C Element using gates

c\ab 00
0 1

01

11

10

000
a+ b+

0 0 R 0 F 1 1 1
c=ab+ac+bc

100
b+

010
a+

110
c+

SET C

111
a b c
ab-

KEEP C=1

011
b-

101
a-

Hazardous Material !

001
c-

Hazardous Hazards
ac a b
SLOW

ab bc

a b ac ab bc c

(slow)

Hazardous Hazards

Hazards are no big deal in sync circuits Hazards are deadly in (some) async circuits Now you know why you were taught about them in school We can build hazard-free circuits We can (sometimes) make timing assumptions and add delays

Hiding Hazards Behind Delays

ac a b
SLOW

c d

ab bc

a b ac ab bc c d

(slow rise)

Do you like slowing your circuit ?

Avoiding Hazards with Complex Gates

a b c

c a a
T1

Theoretically, same hazard problem (e.g. T1 slow) Must use caution or delay output

a a b

b c b c

Synthesis: C Element using SR Latch

c\ab 00
0 1

01

11

10

000
a+ b+

0 0 R 0 F 1 1 1
reset=ab

KEEP C=0

100
b+

010
a+

110
set=ab
a b
c+

SET C

111
aS Q

b-

KEEP C=1

011
b-

101
a-

001
c-

RESET C

Synthesis using SR latches

Needs SET, RESET regions May use KEEP 0, KEEP 1 regions May use unreachable states (more later) Area / performance / power may be more or less than gate circuits May use C elements instead of SR latches SR latches enable implementation with standard libraries

Implementation using Latches or C elements

SET LOGIC RESET LOGIC

S R

SET LOGIC RESET LOGIC

Generalized C Element
a b c
c b

+ C -

set(z) = ab reset(z) = b'c'

reset z

c c b a z b a b

reset

set z

c b a

a z

b a

set

set

reset

DYNAMIC (Pseudostatic)

STATIC

More interesting PNs and STGs

x+ x+

(input) CHOICE

MUTUALLY EXCLUSIVE

FORKs
MUTUALLY EXCLUSIVE x+

CONTROLLED CHOICE

x+

JOINs
MERGE

STG with Input Choice

y+

x+

z+

b+ x-

y-

z-

b-

A Simple Choice Net

a b c d

a b c d

I
b+ c+ cba+ b+ b+

II RR00
ca+

01R0
c+ b-

0F10

1R00
b+

d+ c+ d-

0F10
a-

110R
d+

a-

F110
d-

11R1

111F

c+

Unreachable States

b+

RR00
c-

a+

cd\ab 00

01

11

10

01R0
c+ b-

00F0

1R00
b+

00

0F10
a-

110R
d+

01
11 10

x
x

x
x

x
x x

F110
d-

11R1

111F

c+

Regions and Maps

cd\ab 00
b+

01

11

10

RR00
c-

a+

00

0 R 0 0 x x x R x x 1 x

01R0
c+ b-

00F0

1R00
b+

01 11 10

0F10
a-

110R
d+

F 1 1 x c=d+ab+bc

F110
d-

11R1

111F
For c

c+

set(c)=d+ab
reset(c)=b

c=d+ab+bc

d a b

set(c)=d+ab reset(c)=b

d a b

Regions and Maps

cd\ab 00
b+

01

11

10

RR00
c-

00
a+

0 0 R 0
x x x 1 x x F x

01R0
c+ b-

00F0

1R00
b+

01 11 10

0F10
a-

110R
d+

0 0 0 x d=abc

F110
d-

11R1

111F
For d

c+

set(d)=abc
reset(d)=c

Walks on SG and KM
I
b+

cd\ab 00

01

11

10

RR00
c-

a+

00

01R0
c+ b-

00F0

1R00
b+

01 11 10

x x

x x

x x x

0F10
a-

110R
d+

F110
d-

11R1

II

111F

c+

II

Exercise: A decomposed gate implementation is not speed-independent due to hazards. Explain, using the walks.

STG Rules

Any STG:

Input free-choiceOnly mutex inputs may control the choice) 1-BoundedMaximum 1 token per place LivenessNo deadlocks

STG for Speed Independent circuits:

Consistent state assignmentSignals strictly alternate between + and PersistencyExcited signals fire, namely they cannot be disabled by another transition
Complete state codingDifferent markings must represent different states

Synthesizable STG:

We use the following circuit to explain STG rules:

req ack

REQ ACK

1-Bounded (Safety)

STG is safe if no place or arc can ever contain more than one token Often caused by one-sided dependency

req+ ack-

ack+ req-

REQ+ ACK-

ACK+ REQ-

STG is not safe: If left cycle goes fast and right cycle lags, then arc ack+ REQ+ accumulates tokens. (REQ+ depends on both ack+ and ACK- ) Possible solution: stop left cycle by right cycle

Liveness

STG is live if from every reachable marking, every transition can eventually be fired

reset-

reset_ok-

req+ ack-

ack+ req-

The STG is not live: Transitions reset, reset_ok cannot be repeated. But non-liveness is useful for initialization

Consistent State Assignment

The following subset of STG makes no sense:

a+ a-

a+ a-

Persistency

STG is persistent if for all arcs a* b*, other arcs ensure that b* fires before opposite transition of a* (*is either + or -) Non-persistency may be caused by one-sided relations
req+ ackack+ reqREQ+ ACKACK+ REQ-

STG is not persistent (in addition to being unsafe): If left cycle goes fast and right cycle lags, then ack+ ack- before REQ+ . Danger: Logic design may be REQ+ = ack+ Exception: If a* b*, assume that the environment assures persistency. Possible solution: stop left cycle by right cycle.

Complete State Coding

STG has a complete state coding if no two different markings have identical values for all signals.
ack0100 0000

req,ack,REQ,ACK:

req+ ack+

1000

1010

REQ+ ACK1000

ACK+
1011

reqcd\ab 00 00 01 11 10

REQ1001

1100

01

11

10

Disaster!

Complete State Coding

Possible solution: Add an internal state variable

req,ack,REQ,ACK,x:

ack-

req+

10000

10100

REQ+

ACK+

x-

x+

req-

ack+
11001 10001

ACK-

REQ-

Petrify : A tool for synthesizing SI circuits from STGs

Petrify Environment :
write_sg

STG

petrify

lib

SG

draw_astg

EQN

ps

Petrify

Unix (Linux) command line tool petrify h for help (flags etc.) petrify cg for complex gates petrify gc for generalized C-elements petrify tm for tech mapping draw_astg to draw write_sg to create state graphs Documented on line, incl. tutorial

See http://www.lsi.upc.es/~jordic/petrify/petrify.htm

A faster STG?

Does it need an extra variable?

req+ REQ+

ack+

ACK+

req-

REQ-

ack-

ACK-

Drawn by draw_astg

Note reverse colors

req,ack,REQ,ACK:

The SG
0000 r+ 1000 R+ a+ 1100 1010 R+ ra+ 0100 1110 A+ R+ ar0110 1111 A+ ar0111 Ra0011 0101 Rr+ a1011 0001 RAa+ r+ 1111 1001 RAra+ 0111 1101 ARra0101 Aa-

A+
1011 Ra+ 1001 RAa+ 1101 1000 Ara+ 1100 Ar0100 a-

req,ack,REQ,ACK:

The SG
0000 r+ 1000 R+ a+ 1100 1010 R+ ra+ 0100 1110 A+ R+ ar0110 1111 A+ ar0111 Ra0011 0101 Rr+ a1011 0001 RAa+ r+ 1111 1001 RAra+ 0111 1101 ARra0101 Aa-

A+
1011 Ra+ 1001 Ra+ 1101 Ar1100 Ar0100 R+ a-

A1000 R+ a+ R+

Drawn by write_sg & draw_astg

Extra states inserted by petrify

Rearranged STG
req+ REQ+ ACK+ c2REQACKc2+ c0+

c1ack+ reqc1+ c0ack-

Initial Internal State: c0=c1=c2=1

The new State Graph

The Synthesized Complex Gates Circuit

INORDER = r A a R csc0 csc1 csc2; OUTORDER = [a] [R] [csc0] [csc1] [csc2]; [a] = a (csc2 + csc0) + csc1'; [R] = csc2 (csc0 (a + r) + R); [csc0] = csc0 (csc1' + a') + R' csc2; [csc1] = r' (csc0 + csc1); [csc2] = A' (csc0' (csc1' + a') + csc2);

Technology Mapping
INORDER = r A a R csc0 csc1 csc2; OUTORDER = [a] [R] [csc0] [csc1] [csc2]; [0] = R'; # gate [1] = [0]' A' + csc2'; # gate [a] = a csc0' + [1]; # gate [3] = csc1'; # gate [4] = csc0' csc2' [3]'; # gate [5] = [4]' (csc1' + R'); # gate [R] = [5]'; # gate [7] = (csc2' + a') (csc0' + A'); # gate [8] = csc0'; # gate [csc0] = [8]' csc1' + [7]'; # gate [csc1] = A' (csc0 + csc1); # gate rs_nor: [11] = R'; # gate [12] = csc0' ([11]' + csc1'); # gate [csc2] = [12] (r' + csc2) + r' csc2; # gate inv: combinational oai12: combinational sr_nor: asynch inv: combinational nor3: combinational aoi12: combinational inv: combinational aoi22: combinational inv: combinational oai12: combinational asynch inv: combinational aoi12: combinational c_element1:asynch

The Synthesized Gen-C Circuit

INORDER = r A a R csc0 csc1 csc2; OUTORDER = [a] [R] [csc0] [csc1] [csc2]; [0] = csc0' csc1 (R' + A); [1] = csc0 csc2 (a + r); [2] = csc2' A; [R] = R [2]' + [1]; # [4] = a csc1 csc2'; [csc0] = csc0 [4]' + csc2; # [6] = r' csc0; [csc1] = csc1 r' + [6]; # [8] = A' csc0' (csc1' + a'); [csc2] = csc2 R' + [8]; # [a] = a [0]' + csc1'; #

mappable onto gC mappable onto gC mappable onto gC

mappable onto gC mappable onto gC

A safer STG?

req+

REQ+

ack+

ACK+

req-

REQ-

ack-

ACK-

A safer STG?

The safer STG is a serial circuit

req+ REQ+

ack+

ACK+

INORDER = r A a R; OUTORDER = [a] [R]; [a] = A; [R] = r;

req-

REQ-

req
ackACKack

REQ
ACK

Yet another STG?

req+

REQ+

ack+

ACK+

req-

REQ-

ack-

ACK-

Yet another STG?

Output Handshake First

req+

REQ+

ack+

ACK+

req-

REQ-

ack-

ACK-

Still a serial controller

Synthesis
INORDER = r A a R csc0; OUTORDER = [a] [R] [csc0]; [a] = csc0 A'; # gate and2_1: combinational [R] = r csc0'; # gate and2_1: combinational [2] = A' (csc0' + r'); # gate aoi12: combinational [csc0] = [2]'; # gate inv: combinational

a c0 A r
S Q R Q

A A r

c0 r R

=
r

+ -

c0

c
c0 R

A different STG

req+

REQ+

ack+
Redundant, will be ignored by petrify

ACK+

req-

REQ-

ack-

ACK-

A different STG

Synthesis
INORDER = r A a R; OUTORDER = [a] [R]; [a] = R; [1] = r A'; [2] = r' A; [R] = R [2]' + [1];

# mappable onto gC

R = R(Ar)+Ar = R(A+r)+Ar = Ar + RA +Rr

A r a

Latch Control
req REQ ACK

Data-less fifo:
ack

req ack
Lt Enable

REQ ACK
Enable=0: transparent

Latch:

Constraints on sequence of events

Must keep input data available until after it is latched Assume input data available only when req=1 Once ack+, req- (and input data invalid) can follow very fast Lt+ before ack+

Latch Control: STG Fragments

req+ req+ ACKreqACK+ REQ+

ack+

REQ+

REQ-

ACK+

req-

Lt+

Lt-

REQ-

ack-

ack+

ack-

ACK-

Latch Control: Combined STG

req+ Lt+ ack+ ACK+ REQ+

reqLtack-

REQ-

ACK-

Latch Control: Combined STG

INORDER = Rin Aout Ain Rout Lt; OUTORDER = [Ain] [Rout] [Lt]; [Ain] = Lt; [1] = Aout' Rin; [2] = Aout Rin'; [Rout] = Rout [2]' + [1]; # mappable onto gC [Lt] = Rout; R = R(Ar)+Ar = R(A+r)+Ar = Ar + RA +Rr

A r a Lt

MUX Control

So far all examples are doable by hand A deceptively simple example: Control for 4-phase bundled data mux

PUSH channels

4-phase Bundled-data Mux

We have already drawn this (dual-rail control):

x y z ctl.f ctl.t x-ack

x y

0 1

z
x-req ctl.f ctl.t y-req y-ack ctl-ack

C C
z-req

ctl

C C
z-ack

Easier to start with the dual-rail control

The environment

Four independent environments (rCf, rCt share aC) Must not specify any dependency by mistake:
r0+ r1+ rCf+ rCt+ R+

a0+
r0-

a1+
r1-

aC+
rCf-

aC+
rCt-

A+
R-

a0In0

a1In0

aCCtl.f

aCCtl.t

AOut

The control

A+ must precede a0+ or a1+ (make sure data passed through and were captured) In0 and In1 handshakes must be made MUTEX Choices are matches with Merges

rCt+ aCrCf+

r1+
P3

a1+ R+

rCtP2 P4

A+

P1

aC+ a0+

r0+

rCfr1-

Duplicate arrow Input Free Choice Controlled Choice Merge r0-

P5

mux.g

mux.gc

Replicated transitions: R+, R+/1 Inserted state variable to retain In0 vs. In1 info

Compact state graph

Mux Control Synthesis

INORDER = r0 r1 rCf rCt A a0 a1 aC R csc0 csc1; OUTORDER = [a0] [a1] [aC] [R] [csc0] [csc1]; [0] = r0 csc0; [a1] = csc1 r1; [2] = csc1 (A + csc0); [3] = rCt' rCf' csc1'; [aC] = aC [3]' + [2]; # mappable [R] = a0' csc0' csc1 r0 + csc0 csc1'; [6] = a0' csc1 A r0 + csc1' r1 A'; [7] = aC (r0' + a0); [csc0] = csc0 [7]' + [6]; # mappable [9] = r0 A' + csc0 A; [10] = r0' csc0' r1'; [csc1] = csc1 [10]' + [9]; # mappable [a0] = a0 r0 + [0]; # mappable

onto gC

onto gC

onto gC onto gC

Another Mux (4p ctl, bd) (Fig 6.24)

SG for the Fig 6.24 mux

All-bundled Mux

All-bundled Mux Synthesis

INORDER = In0Req OutAck In1Req Ctl CtlReq In1Ack In0Ack csc0; OUTORDER = [In1Ack] [In0Ack] [OutReq] [CtlAck] [csc0]; [In1Ack] = OutAck csc0'; [In0Ack] = OutAck csc0; [2] = CtlReq (In1Req csc0' + In0Req Ctl'); [3] = CtlReq' (In1Req' csc0' + In0Req' csc0); [OutReq] = OutReq [3]' + [2]; # mappable onto [5] = OutAck' csc0; [CtlAck] = CtlAck [5]' + OutAck; # mappable onto [7] = OutAck' CtlReq'; [8] = CtlReq Ctl; [csc0] = csc0 [8]' + [7]; # mappable onto OutReq CtlAck

gC
gC

gC

Reduced concurrency mux