History

Verilog was invented by Phil Moorby in 1985 as a hardware modeling language. Verilog was later submitted to IEEEand became IEEE Standard 13641995, commonly referred to as Verilog-95. Extensions to Verilog-95 were submitted to IEEE. These extensions became IEEE Standard 1364-2001 known as Verilog 2001. Verilog 2005, IEEE Standard 1364-2005, focus mostly on minor corrections, as any language improvement was done as a separate project, known as System Verilog. System Verilog incorporates Object oriented programming concepts.

Verilog Numbers
4'b1010 - Binary 1010 (using 4 bits) 12'h123 - Hexidecimal 123 (using 12 bits)

20'd44 - Decimal 44 (using 20 bits - 0 extension is automatic)

6'o77 - Octal 77 (using 6 bits)

Verilog Data Types

wire
Variable used simply to connect components together

reg
Variable that saves a value as part of a behavioral description Usually corresponds to a wire in the circuit Is NOT necessarily a register in the circuit

Verilog Data Types

Bits - value on a wire 0, 1 X - dont care/dont know Z - undriven, tri-state

Vectors wire [31:0] BusA; reg [31:0] BusB;

A[3:0] - vector of 4 bits: A[3], A[2], A[1], A[0] Treated as an unsigned integer value e.g. , A < 0 ??

Verilog Data Types

Arrays reg [3:0]salman[1:0];
salman

Parameters parameter port_id=5; // constant

Verilog Operators

Verilog Continous Assignment

Assignment is continuously evaluated assign corresponds to a connection or a simple component with the described function Target is NEVER a reg variable Target is always a wire use of Boolean operators
assign A = X | (Y & ~Z);
assign B[3:0] = 4'b01XX; assign C[15:0] = 12'h00ff;

(~ for bit-wise, ! for logical negation) bits can take on four values (0, 1, X, Z) variables can be n-bits wide (MSB:LSB)

assign #3 {Cout, S[3:0]} = A[3:0] + B[3:0] + Cin;

use of arithmetic operator multiple assignment (concatenation) delay of performing computation, only used by simulator, not synthesis

Verilog Continuous Assignment

module Compare1 (A, B, Equal, Alarger, Blarger); input A, B; output Equal, Alarger, Blarger; assign Equal = (A & B) | (~A & ~B); assign Alarger = (A & ~B); assign Blarger = (~A & B); endmodule

Verilog always Statement

All behavioral programming in enclosed within an always statement
module and_gate (out, in1, in2); input in1, in2; output out; reg out; always @(in1 or in2) begin out = in1 & in2; end endmodule

Not a real register!! A Verilog register Neededb ecause of assignment in always block

Specifies when block is executed I.e., triggered by which signals

Verilog Procedural Assignments

Procedural assignments update values of reg, integer, real or time variables.
Blocking procedural assignment = always @(posedge clock) begin reg1 = in1; reg2 = @(nededge clock)in2&in3; reg3 = reg1; end Non-Blocking procedural assignment <= always @(posedge clock) begin reg1 <= in1; reg2 <= @(nededge clock)in2&in3; reg3 <= reg1; end execution is concurrent in nature

execution is sequential in nature

Continuous vs Procedural Assignments

Continuous assignment for interconnecting modules
assign b = reset&a;

always @(a,b.)

reset

always @(a,b.)

Procedural assignment for module behavior

RTL

In integrated circuit design, Register Transfer Level (RTL) description is a way of describing the operation of a synchronous digital circuit. In RTL design, a circuit's behavior is defined in terms of the flow of signals (or transfer of data) between hardware registers, and the logical operations performed on those signals.