Presented By:

Hukam Singh
1NH02EC016
IC TECHNOLOGIES

 Full custom IC technology

 Semi custom IC technology

 PLDs
Semicustom IC technology

TYPES:

 Gate Array ASIC technology

 Standard Cell ASIC technology

HARDCOPY II STRUCTURED ASIC
DEFINITION

 Permanent form.

 Reproduction for direct use.

 Migrating FPGA design to structured ASIC.

 What is the difference between HardCopy II structured
ASICs and previous generations of HardCopy structured
ASICs?

 Based on fine grained architecture

 Offer significantly lower cost per gate

 Higher densities

 Higher performance

 More features
Process technology of HardCopy II
structured ASICs

 1.2-V, 90-nm, all-layer-copper process technology

 Manufactured on 300-mm wafers.

 Same facility as Stratix II FPGAs.

 Customized with top two metal layers.

Members of HardCopy II structured ASIC
family

 Includes five members

HC210W
HC210
HC220
HC230
HC240
 HardCopy II family overview

Feature HC210
W HC210 HC220 HC230 HC240
Additional 0 0 0.3 0.7
gates for 1.4
DSP
Total RAM 875,5 875,5 3,059, 6,345, 8,847,
Bits 20 20 712 216 360
PLLs 4 4 4 8 12

Maximum I/O 300 334 494

Pins 698 951
484 – 484 – 672- 1,020 1,508-
Packages pin pin Pin -Pin Pin
wire FBGA FBGA FBGA FBGA
bond
HardCopy Features

 Density range

– Between 1 million and 2.2 million ASIC gates

 Power reduction

- 50 percent reduction

 Supports embedded PLLs

 HardCopy Features

 Supports high-speed I/O interface protocols:

Stratix II FPGAs support bus protocols, Like

SPI-4.2, SFI-4, XSBI, HyperTransport, NPSI

for applications such as interface bridging, backplanes, and chip-

to-chip communications.

 Supports external memory interfaces

SRAM and DRAM devices, including SDRAM, DDR SDRAM,

HardCopy Features

 Temperature range
junction temperatures ranging from -40°C to 100°C

 Supports high-speed differential I/O electrical standards

like LVDS and LVPECL

 Available in lead-free packages

Design Migration

 Different Stratix II devices can be used to prototype a HardCopy

II design.

 The HardCopy II Device Resource Guide in Quartus II design

software version 5.0

 A HardCopy II Device Resource Guide is generated every time a

user compiles a Stratix II design using Quartus II software
version 4.2 or later.

 This report can guide the user.

Testability addressed

 Base arrays are embedded with testability circuits.

 Comes standard with BIST.

 Do not require any functional vectors

 Using automatic test pattern generation (ATPG) vectors.


Results in very high test coverage of approx. 99%
 How long does it take to migrate a design to
a HardCopy structured ASIC ?

 The design can be migrated to a HardCopy series structured ASIC

in two to four weeks.

 HardCopy prototypes will be available within five weeks.

 Production units will be delivered within eight weeks.

Implementation Timeline

Migration
&
Verification
Custom Masks
Prototype Fabrication
Assembly & Test
Prototype
Signoff
Production
~2 Weeks ~7 Weeks Variable

~8 Weeks

20 Weeks
The HardCopy Design Center migrates the FPGA
design by

 Generating a Verilog structural netlist.

 Verifying that the design satisfies timing requirements.

 Manufacturing prototypes using the same fab and process

technology used for the FPGA.

 Volume production starts once you have approved the

prototypes for satisfactory functionality.

 We get production devices in approximately 20 weeks.

Hardware Design Considerations
Back–End Design Flow

 Device Netlist Generation

Q II generates a Verilog netlist
HC stratix & APEX use .sof to program the FPGA

 Design for Testability Insertion

Inserts necessary test structures

 Clock Tree & Global Signal Insertion

Adds a layer of CTB to connect the GCR to registers in
design.
Back–End Design Flow

 Timing & Signal Integrity Driven Place & Route

 Parasitic Extraction & Timing Analysis

Generates .gds2 file
Used to calculate path delays

 Layout Verification
Verification for manufacturability
DRC & antenna checking of long traces of signal in layout
Back–End Design Flow

 Design Signoff
final place and route netlist functional verification
layout verification for manufacturability
timing analysis
Merits

 Improves performance

 Preserves the FPGA architecture and features,

and minimizes risk.

 Offers a quick turnaround of the FPGA design to a

structured ASIC

 Pin-compatibility
Merits

a low-risk approach.

 lower development cost,

 improved time-to-market,

 improved flexibility
….. Hence A Natural Choice
Questions!!