vLSl ueslgn verlflcaLlon

LecLure 02 Why ls preslllcon

verlflcaLlon requlred?
1ypes of ueslgn verlflcaLlon
Why is pre-silicon verification required?
Ref: "Connecting Pre-SiIicon and Post-SiIicon Verification" - Sandip Ray and Warren A. Hunt Jr
http://www.cs.utexas.edu/users/fsandip, hunt
Ref: "Connecting Pre-SiIicon and Post-SiIicon Verification" - Sandip Ray and Warren A. Hunt Jr
http://www.cs.utexas.edu/users/fsandip, hunt
Ref: "Connecting Pre-SiIicon and Post-SiIicon Verification" - Sandip Ray and Warren A. Hunt Jr
http://www.cs.utexas.edu/users/fsandip, hunt
%ypes of Verification
W Ver|f|cat|on 9reslllcon process LhaL ls used durlng Lhe
deslgn phase for galnlng confldence LhaL Lhe deslgn wlll
produce Lhe expecLed resulLs
W uncLlonal verlflcaLlon
W 9erformance verlflcaLlon
W SlmulaLlon
W LmulaLlon
W ormal verlflcaLlon
W Semlormal verlflcaLlon
unctional Verification
W uncLlonal verlflcaLlon valldaLes LhaL Lhe deslgn meeLs Lhe
requlremenLs
W SysLemlevel LesLbenches are creaLed based on Lhe lnpuL speclflcaLlons
W 1he varlous aspecLs of Lhe daLa and conLrol flow are valldaLed whlch
lncludes passlng lnformaLlon beLween Lhe exLernal world lnlLlaLlng or
LermlnaLlng l/C devlces and verlfylng sofLware
W 1he sysLemlevel LesLbenches creaLed durlng Lhe funcLlonal deslgn can
also be used for performance verlflcaLlon
unctional Verification
(.Contd)
cLlvlLy whlch verlfles Lhe funcLlonallLy of SlC's/SCCs agalnsL Lhelr
speclflcaLlon
uncLlonal verlflcaLlon also helps ln cleanlng up of speclflcaLlons
lso referred Lo as
W SlmulaLlon
W Loglc verlflcaLlon
W ueslgn verlflcaLlon (uv)
W lmplemenLaLlon valldaLlon
CaLe level slmulaLlon are done on Lhe gaLe level neLllsL (afLer synLhesls or
afLer place and rouLe) for verlfylng Lhe funcLlonallLy afLer Lhe LranslaLlon
from 81L Lo gaLes
W 1hese are normally done for llmlLed number of LesL cases
W 1hese can be performed wlLh or wlLhouL Llmlng lnformaLlon
evels of unctional Verification
W verlflcaLlon for all large SlCs ls done aL dlfferenL levels
unlL/Module level verlflcaLlon
1op Level verlflcaLlon
SysLem level verlflcaLlon
&nit evel Verification
-eed for unlL Level verlflcaLlon
VLarge deslgns wlll have mulLlple unlLs
VLase of verlflcaLlon aL unlL level
VSaves efforL and Llme
V1esL bench deslgn for compleLe funcLlonal unlL level verlflcaLlon
becomes easy
VLasy Lo check corner cases and sLress condlLlons
unlL level verlflcaLlon ls compleLe and relevanL lf
Vueslgn parLlLlonlng ls such LhaL all feaLures Lo be verlfled are
compleLely conLalned wlLhln Lhe unlL and can be verlfled on a
sLand alone basls
VLach unlL Lo be verlfled should have a deLalled speclflcaLlon
documenL addresslng lL's full funcLlonallLy
%op evel verification
1op level verlflcaLlon ls
verlflcaLlon of all Lhe unlLs of a slngle chlp LogeLher
1he sLress ls on Lhe verlflcaLlon of Lhe lnLerfaces of dlfferenL
unlLs and exLernal lnLerface
Lnsurlng LhaL Lhe chlp meeLs Lhe funcLlonal speclflcaLlons
or very large SlCs Lop level verlflcaLlon can also refer Lo a parL
of Lhe chlp whlch can be loglcally parLlLloned ( usually called as
subsysLem)
W Lx 1ransmlLLer chaln of Lhe Modem chlp
$ystem evel Verification
SysLem level verlflcaLlon ls
VverlflcaLlon of Lhe whole sysLem conslsLlng of several SlCs and
oLher componenLs
Vused Lo LesL some of Lhe sofLware componenLs LgMlcrocode and
appllcaLlon sofLware Lg ln SCC verlflcaLlon uslng coverlflcaLlon
envlronmenL
VSame as Lop level verlflcaLlon ln case of slngle SlC where no
sofLware ls lnvolved
VSysLem level LesLlng also concenLraLes on Lhe lnLeracLlon of Lhe SlC
under LesL wlLh all lLs surroundlng componenLs
VlL ls very essenLlal Lo undersLand fully Lhe appllcaLlon ln whlch Lhe
SlC ls used Lo make Lhe sysLem LesLlng effecLlve
!erformance Verification
W 9erformance verlflcaLlon ls done durlng Lhe archlLecLure selecLlon and mapplng phase
ln Lhls phase Lhe goal ls Lo check LhaL Lhe selecLed archlLecLures meeL performance
requlremenLs ln addlLlon Lo Lhe funcLlonal requlremenLs
W 9erformance verlflcaLlon valldaLes all Lhe archlLecLural enLlLles and lnLerfaces beLween
Lhem before deLalled deslgn lmplemenLaLlon ll l9s Lhe opLlmlzed daLa conLrol flow
deLalls and sofLware descrlpLlon are used as lnpuLs for Lhe performance verlflcaLlon
W 1he verlflcaLlon uses Lhe slmulaLors LhaL are embedded ln Lhe sysLem deslgn
envlronmenL 1o verlfy Lhe archlLecLure Lhe LesLbench requlred aL Lhe sysLemlevel ls
creaLed
W fLer performance verlflcaLlon Lhe ouLpuL lncludes opLlmlzed llbrary elemenLs and
deLalled funcLlonallLy and performance speclflcaLlons for hardware and sofLware
lmplemenLaLlon
$imulation
W ueflnlLlon SlmulaLlon refers Lo modellng of a deslgn lLs funcLlon and
performance
W sofLware slmulaLor ls a compuLer program an emulaLor ls a hardware
slmulaLor
W SlmulaLlon ls used for deslgn verlflcaLlon
W valldaLe assumpLlons
W verlfy loglc
W verlfy performance (Llmlng)
W 1ypes of slmulaLlon
W Loglc or swlLch level
W 1lmlng
W ClrculL
W aulL
W SlmulaLlon Lechnologles lnclude evenLbased and cyclebased slmulaLors
LransacLlonbased verlflcaLlon code coverage MS slmulaLlon PW/SW co
verlflcaLlon acceleraLors such as emulaLlon rapld proLoLype sysLems hardware
modelers and hardware acceleraLors
$imulators
W SlmulaLors are Lhe mosL common and famlllar verlflcaLlon Lools
W SlmulaLlon alone ls never Lhe goal of an lndusLrlal pro[ecL
W SlmulaLors aLLempL Lo creaLe an arLlflclal unlverse LhaL mlmlcs Lhe
envlronmenL LhaL Lhe real deslgn wlll see
W Cnly a approxlmaLlon of reallLy
ulglLal values n sLd loglc have 9 values
8eallLy slgnal ls a conLlnuous value beLween C-u and vdd
$imulators
W LxecuLe a descrlpLlon of Lhe deslgn
W uescrlpLlon llmlLed Lo well deflned language wlLh preclse semanLlcs
W SlmulaLors are noL a sLaLlc Lool requlre Lhe user Lo seL up an
envlronmenL ln whlch Lhe deslgn wlll flnd lLself Lhls seLup ls ofLen
called LesLbench
W 9rovldes lnpuLs and monlLors resulLs
$imulators
W SlmulaLlon ouLpuLs are valldaLed exLernally agalnsL deslgn lnLenL
(speclflcaLlon)
W 1wo Lypes
LvenL based
Cycle based
vent Based $imulators
W LvenL based slmulaLors are drlven based on evenLs
W n aLLempL Lo lncrease Lhe slmulaLed Llme per unlL of wall Llme
W CuLpuLs are a funcLlon of lnpuLs
1he ouLpuLs change only when Lhe lnpuLs do
Moves slmulaLlon Llme ahead Lo Lhe nexL Llme aL whlch
someLhlng occurs
1he evenL ls Lhe lnpuL changlng
1hls evenL causes slmulaLor Lo reevaluaLe and calculaLe new
ouLpuL
Cycle Based $imulators
W SlmulaLlon ls based on clockcycles noL evenLs
ll comblnaLlonal funcLlons collapsed lnLo a slngle operaLlon
W Cycle based slmulaLors conLaln no Llmlng and delay lnformaLlon
ssumes enLlre deslgn meeLs seLup and holdLlme for all 's
1lmlng ls usually verlfled by sLaLlc Llmlng analyzer
W Can handle only synchronous clrculLs
Cnly 'evenL' ls acLlve edge of clock
ll oLher lnpuLs are allgned wlLh clock (cannoL handle
asynchronous evenLs)
Moore machlne sLaLe changes whenever clock changes mealy
machlnes Lhey also depend on lnpuLs whlch can change
asynchronously
W Much fasLer Lhan evenL based
mulation
W #LmulaLlon ls qulLe slmply Lhe LranslaLlon of sofLware wrlLLen for a dlfferenL
subseL of hardware or for a dlfferenL operaLlng sysLem lnLo sofLware whlch
wlll run on Lhe currenL plaLform"
W LmulaLlon sysLems are speclally deslgned hardware and sofLware sysLems
LhaL Lyplcally conLaln reconflgurable loglc ofLen fleld programmable gaLe
arrays (9C)
W Some of Lhe emulaLlon sysLems avallable ln Lhe lndusLry conLaln hlghspeed
array processors 1hese sysLems are programmed Lo Lake on Lhe behavlor of
Lhe LargeL deslgn and can emulaLe lLs funcLlonallLy Lo Lhe degree LhaL lL can
be dlrecLly connecLed Lo Lhe sysLem envlronmenL ln whlch Lhe flnal deslgn ls
lnLended Lo operaLe
W 8ecause Lhese sysLems are reallzed ln hardware Lhey can perform aL speeds
LhaL are orders of magnlLude fasLer Lhan sofLware slmulaLors and ln some
lnsLances can approach Lhe LargeL deslgn speeds
eatures of mulation
W Lnables Lhe early creaLlon of a hardware model of Lhe chlp
W Lnables Lhe user Lo deLecL and correcL Lhe bugs early ln Lhe deslgn
W blllLy Lo develop and debug Lhe appllcaLlon sofLware
W Pandles deslgn complexlLy of 30000 Lo 20 mllllon gaLes
W 8uns aL near realLlme speeds ln some cases
W 8econflgurable for a varleLy of appllcaLlons
W Scalable as per Lhe deslgn complexlLy and cosL
W blllLy Lo connecL lnclrculL emulaLors (lCL)
W lnbullL loglc analyzer faclllLy for debugglng
W 9robes and monlLors Lhe pln/slgnal ln Lhe sysLem
W 8us models for sLandard buses such as perlpheral componenL lnLerconnecL
(9Cl) LLherneL and oLhers
ormal Verification
9rocess of checklng wheLher a deslgn saLlsfles some requlremenLs
(properLles)
MaLhemaLlcally prove LhaL lmplemenLaLlon saLlsfles speclflcaLlon
W ueslgn musL be ln #verlflable" formaL
W deslgn ls a seL of lnLeracLlng sysLems each havlng a flnlLe number of
conflguraLlons or #sLaLes"
W SLaLes and LranslLlon beLween sLaLes consLlLuLe SMs
W CbLaln a compleLe SM descrlpLlon of Lhe sysLem
W Clven a presenL sLaLe (or currenL conflguraLlon) Lhe nexL sLaLe (or successlve
conflguraLlon) of an SM can be wrlLLen as a funcLlon of lLs presenL sLaLe and
lnpuLs (LranslLlon funcLlon or LranslLlon relaLlon)
W -exL SLaLe f (presenL sLaLe lnpuLs)
ormal Verification %echniques
1heorem 9rovlng
Model Checklng
Lqulvalence Checklng
%heorem !roving
W SysLem and lLs deslred properLles modeled as formulaes ln some
maLhemaLlcal loglc glven by a formal sysLem whlch deflnes a seL of
axloms and a seL of lnference rules
W 1heorem provlng ls Lhe process of flndlng a proof of a properLy
from Lhe axloms of Lhe sysLem
W MachlneasslsLed Lheorem provlng
odel Checking & quivalence Checking
Model Checklng
compotes fooctlooollty to o set of JeslqoetptovlJeJ ptopettles ot cbotoctetlstlcs
nswers Lhese quesLlons
- Pave l deslgned whaL l wanLed Lo deslgn ?
- uoes my lmplemenLaLlon saLlsfy Lhe properLles of my speclflcaLlon ?
Lqulvalence Checklng
9tove fooctloool epolvoleoce betweeo two lmplemeototloos of o Jeslqo
nswers Lhese quesLlons
- Pas Lhe deslgner or Lhe Lool corrupLed Lhe deslgn wlLh unexpecLed changes
?
- Pas my lmplemenLaLlon been preserved durlng process LransformaLlons ?
quivalence Checking
W Compares Lwo
lmplemenLaLlons assumes
one as golden or reference
(le funcLlonally correcL)
W ueLecLs problems ln
LransformaLlon sLeps
W Lxample 81L Lo -eLllsL
-eLllsL Lo -eLllsL
W Compares 8oolean and
SequenLlal loglc funcLlons
W LxhausLlve verlflcaLlon
lVlL-2
lVlL-l
(Goluoo koIorooco}
Jool
%7,381472,943
lVlL-2
Assortloos
Jool
odel Checking
8ocs oou lotoot uoIloltloo
W sserLlons (deslgner
deflned characLerlsLlcs)
are proven or dlsproved
W Lxample unreachable
sLaLes lsolaLed sLaLes
deadlocks ln sLaLe
machlnes lnLerface
behavlor
W LxhausLlve verlflcaLlon
$emi-formal Verification
Mlx of funcLlonal verlflcaLlon and formal verlflcaLlon Lechnlques
- 81L sserLlons
- ormer 9roperLy Language
1yplcal sserLlons
- CnehoL buses
- ull and parallel case synLhesls pragmas
- rray accesses
- 8us conLenLlon
- valld daLa noL losL ln sLalled plpellnes
- Low prlorlLy evenLs evenLually processed
- 8equesLs handled wlLhln speclfled wlndow
- 9ackeL valld slgnal asserLed correcLly
Semlformal verlflcaLlon llnks slmulaLlon and formal verlflcaLlon
$emi-formal Verification (.Contd)
W Same checkers asserLlons LhaL waLch for bugs ln slmulaLlon become LargeLs
for semlformal Lools
W LxacLly Lhe same monlLors LhaL are used Lo check Lhe legallLy of lnLerface
proLocols ln slmulaLlon are slmply reused as consLralnLs by semlformal
Lools
8unnlng Lhe slmulaLlon LesLs Lyplcally flres some checkers reveallng
some of Lhe bugs
1hen semlformal Lools can LargeL Lhe checkers dlrecLly flndlng Lhe
rlghL sLlmulus Lo Lrlgger addlLlonal bugs
$emi-formal Verification (.Contd)
Lxample use of l8M oCs
W oCs Lakes Sugar properLles (aka asserLlons) and LranslaLes Lhem lnLo PuL
Checkers
W PuL checkers are lnLegraLed lnLo Lhe slmulaLlon envlronmenL Checkers
monlLor Lhe slmulaLlon resulLs on a cyclebycycle basls for vlolaLlon of Lhe
properLles
W Lach Checker lmplemenLs a sLaLe machlne LhaL enLers and asserLs an error
sLaLe lf Lhe respecLlve properLy falls Lo hold ln a slmulaLlon run
W users of oCs reporL a drasLlc lmprovemenL up Lo 30 ln LesLbench
developmenL Llme