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Introduction To 8086 :

 The main limitations of the 8 bit microprocessors

were their low speed of execution ,low memory
addressing capability, limited number of general
purpose registers & a less powerful instruction set.
All these limitations of the 8 bit microprocessors
tempted the designers to go for more powerful
processors in terms of advanced architecture ,
more processing capability and a more powerful
instruction set. 8086 was a result of such
development design efforts.
 Intel 8086 is a 16-bit µp that is intended to be used
as CPU in microcomputer
 8086 has 16-bit data bus,so it can read data from
or write data to memory and ports either 16 bits or
8 bits at a time.
The 8086 has 20- bit address bus,so it can address
any one of 220 (1048576) memory locations. Each of
the 1048576 memory locations of 8086 represents a
byte wide location. Sixteen bit words will be stored in
two consecutive locations.If the first byte of the word
is at an ODD address the 8086 will read the first byte
with one bus operation & second byte with another
bus operation. And if the first byte of a word is at an
EVEN address the 8086 can read the entire word in
one operation.
8086 Internal Architecture :
The 8086 CPU is divided into two independent
functional units so that dividing the work
between these two units speed up processing.
These functional units are as follows:
BIU (Bus Interface Unit)

EU (The Execution Unit)

Internal Block Diagram Of 8086 :

BIU Memory Interface C-bus

Address adder (Σ) 5
Instruction stream 2
CS Byte queue
A - bus

CH CL Arithmetic & Logic Unit
SI Operands
DI Flags
The Bus Interface Unit (BIU):
The BIU sends out addresses,fetches
instructions from the memory, reads data
from ports & memory and writes data to ports
& memory. Its various functional parts are :
The Queue

The Segment Registers

The Instruction Pointer

The QUEUE :
While the EU is decoding or executing an
instruction which does not require use of the buses , the
BIU fetches up to six instruction bytes for the following
instructions & stores these prefetched bytes in a FIRST-
IN-FIRST-OUT register set called QUEUE . When the EU
is ready for its next instruction ,it simply reads the
instruction bytes for the instruction from the queue in
the BIU. This is much faster than sending out an address
to the system memory & waiting for memory to send
back the next instruction byte or bytes.
As the time required to access registers is less than the
time required to access the memory , it increases the
overall processing speed of the microprocessor.
Fetching the next instruction while current instruction

executes is called as “PIPELINING”.

The Segment Registers :
The address of the
memory bytes need to be accessed is generated
with the help of segment registers . The BIU contain
four 16-bit registers :
Code Segment
Data Segment
Stack segment
Extra Segment
these segment registers are used to hold the upper
16-bits of the starting address of the logical group of
the memory,called the segment,that 8086 is
working with a particular time.
Logical Organisation Of 8086 memory:

Top of extra segment

80000H 64K
Extra segment base ES= 8000 H

6FFFF H Top of stack segment

60000 H Stack segment base SS= 6000 H

5489F H Top of code segment

Code segment base CS= 448A H
448A0 H

3FFFF H Top of data segment

64K Bottom of
30000 H Data segment
DS= 3000 H
In the 8086 microprocessor , the total memory is
divided into segments . Each segment is of 64k .
However the segments can be overlapping , thereby
giving an impression that they can actually of variable
size , with maximum as 64k .
Each of these segments can
be used for a specific function . For example :
Code segment for is used for storing the
instructions. Stack segment is used as STACK.
Data and extra segments are used for storing the
data bytes.
In the assembly language program , there
can be more than one data/code/stack segments
defined . However only one segment of each type
can be active at any time.
The starting address of the segments which are
currently active , or in use , at any time is stored in
the respective segment register . As the segment
register is of only 16-bits, while the address width is
of 20-bits , therefore to get the complete starting
address of the segment , the segment register is
multiplied by 16 or (10)H . The physical address is
calculated as follows :

Ex:1 Physical address calculation using SP &SS

Maximum value of stack segment


01010 H SP = 10 H
01000 H Base of stack segment
The value of the SP (stack pointer) = 0010 H
The value of the(Stack Segment register)SS =0100 H
Physical Address of the top of the stack is =
= 0100 H * 10 H + 0010 H
= 01010 H

Implied zero(obtained on
SS 0 1 0 0 0
multiplication by 16)
SP + 0 0 1 0

P.A. 0 1 0 1 0

Physical Address = segment register *16 +

effective address
Example 2 : Physical Address calculation using Data
Offset and Data Segment:
The offset of the data byte = 0020 H
The value of DS register = 0200 H
Physical Address of Data byte = 0200 H* 10 H + 0020 H
= 02020 H
11FFF Top of data segment

02020 Offset = 20H

02000 Base of data segment
Example 3 : Physical address calculation using
Instruction Pointer & Code Segment register :
The value of the instruction pointer ,
holding the address of instruction currently being
executed = 1234 H
The value of CS = 3200 H
Physical Address of the instruction currently being
executed = 3200 H *10 H+ 1234 H
= 33234 H

41FFF H Top of Code Segment

33234 H I P = 1234 H
32000 H Base of Code Segment
Instruction Pointer :
As discussed earlier , the entire memory
of 8086 is divided into logical partitions , called
segments . One of the segment , called the code
segment , is used to store the segment address of
the instructions. The pointer to the instruction that is
currently being executed is actually the offset of the
instruction within the code segment. This pointer is
Execution Unit (EU):
EU tells the BIU which
memory location to access , and what to do with that .
This involves decoding & execution of the instructions .
It consists of the following sections :
a) Control Circuitry , Instruction Decoder
and ALU :
Instructions are fetched from the instruction
Queue , and stored in the decoder ,where the
instruction is translated into sequence of actions which
the EU carries out. The arithmetic & logic operations
are performed in the ALU . All actions are controlled by
control circuitry.
b) Registers :
The 8086 registers can be divided
into 5 groups according to their functionality. They
are as follows:
1) General Purpose Registers
2) Segment Registers
3) Pointer & Index Registers
4) Special Purpose Registers
5) Flag Registers
General Purpose registers :
8086 has four 16-bits general
purpose registers. They are AX ,BX , CX , DX. In addition to
being used as 16-bit registers , they can be used as 8-bit
registers also as AL, AH, BH , BL , CH , CL , DH ,
DL.Though these registers are general purpose but with
certain instruction they acquire a special meaning.
AX register is called as Accumulator.
BX is mainly used as Base register. This means by default it
is assumed to contain the offset of memory region within data
segment .
CX is assumed to work as a counter in some loop like
instructions .
DX register in I/o instructions is assumed to contain the port
Pointer & Index Registers :
8086 contains three 16-bit
pointer & index registers. They are BP(Base Pointer),
Source Index (SI) and Destination Index(DI).
These three registers can also be used as general
purpose registers . Their main purpose is to contain
the indexes , in stack segment , data segment and
extra segment respectively .
Special Registers :
A stack is a block of memory used to
store address & data . This data is accessed in LIFO
manner . 8086 has reserved 64k of memory aside to
be used as stack. The base of the stack is stored in
SS register & top of the stack is referred by another
special register called as Stack Pointer (SP).
Flag Registers :
8085 compatible
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
u u u u O D IF TF SF ZF u A u PF u C

U undefined CF – carry flag

PF – parity flag
OF- overflow flag AF – auxiliary carry flag(BCD)
DF - String direction flag ZF – zero flag
IF - interrupt enable flag SF – sign flag
TF – Single step trap flag