DEPARTMENT OF TECHNICAL EDUCATION

ANDHRA PRADESH
Name : P. SRINIVAS
Designation : Lecturer
Branch : Electronics & Communication Engg.
Institute : Govt. Polytechnic, Warangal.
Year/Semester : III Semester
Subject : Digital Electronics
Subject Code : EC-304 (7/15)
Topic : Combinational Logic Circuits
Duration : 50 min.
Sub Topic : 2’s complement Parallel
adder/subtractor
Teaching Aids : Animation & images.
EC304.26 1
Objectives

On completion of this period, you would be able to learn

• Draw 2’s complement parallel adder/ subtractor circuit.

• Know the working of 2’s complement parallel adder/

subtractor circuit

EC304.26 2
Recap

In the previous classes we have learnt about

• Half Adder.

• Full Adder.

• 4-bit Parallel binary adder

EC304.26 3
Function of X-OR gate

Fig 1

• When y = 1, z = x (If one of the inputs to the X-OR

gate is 1, the output is the complement of the other.)

• When y = 0, z = x (If one of the inputs to the X-OR

gate is 0, the output is same as the other input.)

EC304.26 4
Block Diagram of Full Adder

A Sum

Full Adder
B

C Carry

Fig 2

EC304.26 5
Truth Table of Full Adder

A B C CARRY SUM
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Table 1
EC304.26 6
2’s Complement Adder/Subtractor
B3 A3 B2 A2 B1 A1 B0 A0

C3 C2 C1 C0
FA FA FA FA

C4 S3 (D3) S2 (D2) S1 (D1) S0 (D0)

Fig:1
EC304.26 7
 2’s Complement Adder/Subtractor

• Subtraction can be done by addition of the 2's Complement.

1. Complement each bit (1's Complement.)

2. Add 1 to the result.

• The circuit shown computes A + B and A – B:

EC304.26 8
 In the circuit shown in Fig.1:

When S=0

• The circuit acts as subtractor, the number B3B2B1B0 is

subtracted from A3A2A1A0 and gives difference=D3D2D1D0.

When S=1

• The circuit acts as an adder, the number B3B2B1B0 is added

to A3A2A1A0 and gives the SUM = C3S3S2S1S0.

EC304.26 9
Operation
Adder
When S=0
• Output of the X-OR gates will be the same as B data bits.

• Carry input to the first full adder is 0 (because S=0).

• A and B bits are applied as the two inputs to the parallel Adder.

• Thus the output is the sum of A and B.

EC304.26 10
Subtractor
When S=1

• Output of the X-OR gates will be the complement of the B data

bits.
• Carry input to the first Full Adder is now 1 (because S=1).

• Addition of 1 to the 1’s complement of B bits are applied as

the inputs to the parallel adder.

• This is the process of subtracting a binary number from another

using 2’s complement method.

EC304.26 11
SUMMARY

We have discussed about

• 2’s complement adder/ subtractor circuit

EC304.26 12
QUIZ

EC304.26 13
1. 2’s Complement adder/subtractor circuit can perform

a) Addition only

c) Subtraction only

e) Addition and Subtraction

g) None of the above

EC304.26 14
2. In the 2’s complement adder/subtractor

a. Sign magnitude numbers represent negative numbers.

c. The sign magnitude numbers have 1 as leading bit.

e. The sign magnitude numbers have 0 as leading bit.

g. 2’s complement represents positive number.

EC304.26 15
Frequently Asked Questions

1. Explain the working of 2’s complement

adder/subtractor.

EC304.26 16
Assignment

1. Write the functions of X-OR gate and Full Adder.

2. Explain 2’s complement method of Subtraction.

3. Explain the working of 2’s complement adder/subtractor

circuit.

EC304.26 17