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ANDHRA PRADESH
Name of the faculty : M. HEMALATHA
Designation : Lecturer
Branch : ECE
Institute : GMR Govt.
polytechnic,madanepally
Year/Semester :III Semester
Subject :Digital Electronics
Subject code :EC 304
Major Topic : Sequential Logic Circuits
Duration : 50 min
Sub-topic : Introduction, Latch.
Teaching Aids : PPT
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OBJECTIVES
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Recap
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SEQUENTIAL LOGIC CIRCUITS
Inputs
Outputs
Combinational
Logic Circuit
Memory
Element/ Circuit
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• Memory element is capable of storing binary information.
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SEQUENTIAL LOGIC CIRCUITS
Synchronous Asynchronous
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COMPARISION BETWEEN ASYNCHRONUS AND
SYNCHRONUS CIRCUITS
Asynchronous Synchronous
1.All the flip-flop in this circuit All the flip-flops are triggered by the
are triggered at different instants same clock pulse at the same time
by different clock sources
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S – R Latch (Flip-Flop)
Latch is a bistable circuit that can reside in either of two stable
states by virtue of feed back.
Inputs Output
NAND Latch R S Q
Q 0 0 Unpredictable
R State
0 1 1
1 0 0
_
Q 1 1 No change
S
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NOR Latch
Truth Table
Inputs Output
R Q
R S Q
0 0 No change
_
0 1 1
Q
S 1 0 0
1 1 Unpredictable
state
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Flip Flops
1. S – R Flip Flop
2. J – K Flip Flop
3. D Flip Flop
4. T Flip Flop
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SUMMARY
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Quiz
d) Present inputs
f) Previous outputs
h) A and b
j) None
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2. In a RS NAND latch, if R=0 and S=1, the
output Q is
c) 1
e) 0
g) Unpredictable
i) None
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3) The unpredictable state occurs in NOR
lath when R= and S=
c) 1,1
e) 1,0
g) 0,1
i) 0,0
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Frequently Asked Questions
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