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Historical Overview of Personal Computers In light of Performance Parameters

SEQUENCE
Scope & Objectives Introduction to PCs Performance Measure Performance Parameters Major Limitations Solutions Clock Doubling Cache Memory Pipelining Instructions Multibus Systems Historical Overview of Intel PCs
8086 to Pentium-III

SCOPE & OBJECTIVE


The Scope And Objective is to Briefly Discuss the Technological Factors Leading to Advancements in PCs Performance and to Analyze the Salient Features of PCs over the Last Two Decades

INTRODUCTION
Central Processing Unit (CPU) Memory Unit

Interconnecting Network
Input Output Devices

PERFORMANCE MEASURE
Same Hardware Environment Same Software Environment Same Operating System Number of Instructions Executed in a

Specified Time

STEPS INVOLVED
CPU Fetches Instruction from RAM
CPU Decodes Instruction CPU Fetches Data (If Required) CPU Performs required Operation

CPU Stores result back into RAM

PERFORMANCE PARAMETERS
CPU Execution Speed

Decoding Time
Operation Time Memory Read / Write Time RAM Speed Bus Speed

MAJOR LIMITATIONS
Single CPU Clock System CPU and Devices have Different Rates RAM Speed No where Close to CPU Speed System Bus Speed Low Bandwidth (Data Rate) Input / Output Devices Speed Variety of Devices (FDD, HDD, CDD)

SOLUTIONS
Single CPU Clock System Clock Doubling Concept RAM Speed Cache Memory System Bus Speed Pipelining Concept (RISC) Input / Output Devices Speed Multiple Bus Architectures

CLOCK DOUBLING
High Internal Clock
For CPU

Low External Clocks


For RAM

For Buses

CACHE MEMORY
High Speed Memory
Level - 1 Cache Level - 2 Cache Level - 3 Cache

Low Capacity due to High Cost

CACHE MEMORY (Contd)


Mother Board of PC
CPU IC Pack

CPU Chip

L-1 Split Cache

L-3 Cache L-2 Unified Cache

RAM

CACHE MEMORY
Information Flow
I/O Devices RAM Cache L-3 Cache L-2
Cache L-1- D Cache L-1- I

PIPELINING CONCEPT
RISC Computers
Five Stages of Instruction Pipelining
Instruction Fetch

Instruction Decode
Fetch Operands

Execute Instruction
Store Result

PIPELINING CONCEPT
Time for One Inst
Time T-1 T-2 Inst 1 Fetch Dec 2 3 4 5 Fetch T-3 Data Dec Fetch T-4 Exe Data Dec Fetch Exe Data Dec Fetch Exe Data Dec Exe Data Exe T-5 T-6 T-7 T-8

MULTIBUS ARCHITECTURE
Cache Bus Level 2 Cache CPU P-II Local Bus PCI Bridge Memory Bus Main Memory

PCI Bus SCSI USB ISA Bridge IDE Disk VGA

PCI Slot

Mouse

K/B ISA Bus

Mon itor

Modem

Sound Card

Printer

ISA Slot

BUS CHARACTERISTICS
ISA Bus 20 Address Lines 8 Data Lines 8.33 MHz Speed Max BW = 16.7 MB/Sec Extended ISA Bus 32 Address Lines 16 Data Lines 8.33 MHz Speed Max BW = 33.3 MB/Sec

BUS CHARACTERISTICS
PCI Bus High Speed = 33 MHz Up to 64 Data Lines Max BW = 264 MB/Sec or 2.112 Gbps Backward (ISA) Compatibility

Historical Overview

Ist Generation PCs


1978 : 8080 Based PC
16 Bit CPU / System Bus Speed 4.77 MHz Hardware (mother board) 8 Bits

1980 : 8088 Based PC


16 Bit CPU Internally 8 Bit Data Bus Externally Speed 4.77 MHz Hardware Compatible

2nd Generation PCs


1982 : 80286 Based PC
16 Bit CPU / System Bus
Speed 6 - 12 MHz

Hardware 16 Bits
Four Times Faster Than 8088

Backward Compatible

3rd Generation PCs


1985 : 80386 Based PC
Intel Microprocessor 32 Bit CPU Speed 16 - 33 MHz Windows Became Possible Multitasking Environment

Cloned PCs Emerged


AMD, Cyrix Speed 40 MHz

4th Generation PCs


1985 : 80486 Based PC
32 Bit CPU / System Bus
8 KB L-1 Cache

Pipelining of Instructions
Speed 75 - 100 MHz

5th Generation PCs


1993 : Pentium PC
Superscalar PC
Parallel Processing

64 Bit Data Processing


16 KB L-1 Cache

Speed 100 - 200 MHz


Bus Speed Limited to 66 MHz

5th Generation PCs


1997 : Pentium MMX PC
Superscalar PC
64 Bit Data Processing

32 KB L-1 Cache
New Set of Instructins 57 New Instructions for Graphics Speed 166 - 233 MHz Bus Speed Limited to 66 MHz

6th Generation PCs


Pentium Pro PC
4 Stage Parallel Pipelining
256 KB L-2 Cache

New Set of Instructins


RISC Concept with CISC Backward Compatibility Bus Speed Limited to 100 MHz

6th Generation PCs


Pentium II PC
7 Stage Pipelining
4 Parallel Execution Units

Two Split 16 KB L-1 Cache


256 KB L-2 Unified Cache New Set of Instructins MMX Instructions Included Speed 233 - 300 MHz

6th Generation PCs


Celeron PC
Same as Pentium II
L-2 Cache Chopped Away

Inexpensive for Low End Users

7th Generation PCs


Pentium III (Katamai) PC
Katamai New Instructions Set
70 New Instructions

Additional Registers for CPU


Speed 500 - 866 MHz

7th Generation PCs


Pentium III (CuMine) PC
Katamai New Instructions Set
Integrated L-2 Cache

Operable at Full CPU Speed


Data Bus 256 Bits

Speed 600 1000 MHz and Above


System Bus Speeds 100 - 133 MHz

THANK YOU

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