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SEQUENCE
Scope & Objectives Introduction to PCs Performance Measure Performance Parameters Major Limitations Solutions Clock Doubling Cache Memory Pipelining Instructions Multibus Systems Historical Overview of Intel PCs
8086 to Pentium-III
INTRODUCTION
Central Processing Unit (CPU) Memory Unit
Interconnecting Network
Input Output Devices
PERFORMANCE MEASURE
Same Hardware Environment Same Software Environment Same Operating System Number of Instructions Executed in a
Specified Time
STEPS INVOLVED
CPU Fetches Instruction from RAM
CPU Decodes Instruction CPU Fetches Data (If Required) CPU Performs required Operation
PERFORMANCE PARAMETERS
CPU Execution Speed
Decoding Time
Operation Time Memory Read / Write Time RAM Speed Bus Speed
MAJOR LIMITATIONS
Single CPU Clock System CPU and Devices have Different Rates RAM Speed No where Close to CPU Speed System Bus Speed Low Bandwidth (Data Rate) Input / Output Devices Speed Variety of Devices (FDD, HDD, CDD)
SOLUTIONS
Single CPU Clock System Clock Doubling Concept RAM Speed Cache Memory System Bus Speed Pipelining Concept (RISC) Input / Output Devices Speed Multiple Bus Architectures
CLOCK DOUBLING
High Internal Clock
For CPU
For Buses
CACHE MEMORY
High Speed Memory
Level - 1 Cache Level - 2 Cache Level - 3 Cache
CPU Chip
RAM
CACHE MEMORY
Information Flow
I/O Devices RAM Cache L-3 Cache L-2
Cache L-1- D Cache L-1- I
PIPELINING CONCEPT
RISC Computers
Five Stages of Instruction Pipelining
Instruction Fetch
Instruction Decode
Fetch Operands
Execute Instruction
Store Result
PIPELINING CONCEPT
Time for One Inst
Time T-1 T-2 Inst 1 Fetch Dec 2 3 4 5 Fetch T-3 Data Dec Fetch T-4 Exe Data Dec Fetch Exe Data Dec Fetch Exe Data Dec Exe Data Exe T-5 T-6 T-7 T-8
MULTIBUS ARCHITECTURE
Cache Bus Level 2 Cache CPU P-II Local Bus PCI Bridge Memory Bus Main Memory
PCI Slot
Mouse
Mon itor
Modem
Sound Card
Printer
ISA Slot
BUS CHARACTERISTICS
ISA Bus 20 Address Lines 8 Data Lines 8.33 MHz Speed Max BW = 16.7 MB/Sec Extended ISA Bus 32 Address Lines 16 Data Lines 8.33 MHz Speed Max BW = 33.3 MB/Sec
BUS CHARACTERISTICS
PCI Bus High Speed = 33 MHz Up to 64 Data Lines Max BW = 264 MB/Sec or 2.112 Gbps Backward (ISA) Compatibility
Historical Overview
Hardware 16 Bits
Four Times Faster Than 8088
Backward Compatible
Pipelining of Instructions
Speed 75 - 100 MHz
32 KB L-1 Cache
New Set of Instructins 57 New Instructions for Graphics Speed 166 - 233 MHz Bus Speed Limited to 66 MHz
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