Chapter 2

Algebraic Methods for the Analysis and

Synthesis of Logic Circuits

Chapter 2 1
 Fundamentals of Boolean Algebra (1)

• Basic Postulates
• Postulate 1 (Definition): A Boolean algebra is a closed algebraic system
containing a set K of two or more elements and the two operators • and +.
• Postulate 2 (Existence of 1 and 0 element):
(a) a + 0 = a (identity for +), (b) a • 1 = a (identity for •)
• Postulate 3 (Commutativity):
(a) a + b = b + a, (b) a • b = b • a
• Postulate 4 (Associativity):
(a) a + (b + c) = (a + b) + c (b) a• (b•c) = (a•b) •c
• Postulate 5 (Distributivity):
(a) a + (b•c) = (a + b) •(a + c) (b) a• (b + c) = a•b + a•c
• Postulate 6 (Existence of complement):
(a) a + a = 1 (b) a • a = 0
• Normally • is omitted.
Chapter 2 2
 Fundamentals of Boolean Algebra (2)

• Fundamental Theorems of Boolean Algebra

• Theorem 1 (Idempotency):
(a) a + a = a (b) aa = a
• Theorem 2 (Null element):
(a) a + 1 = 1 (b) a0 = 0
• Theorem 3 (Involution)
a =a
• Properties of 0 and 1 elements (Table 2.1):

OR AND Complement
a+0=0 a0 = 0 0' = 1
a+1=1 a1 = a 1' = 0

Chapter 2 3
 Fundamentals of Boolean Algebra (3)

• Theorem 4 (Absorption)
(a) a + ab = a (b) a(a + b) = a

• Examples:
– (X + Y) + (X + Y)Z = X + Y [T4(a)]
– AB'(AB' + B'C) = AB' [T4(b)]

• Theorem 5
(a) a + a'b = a + b (b) a(a' + b) = ab

• Examples:
– B + AB'C'D = B + AC'D [T5(a)]
– (X + Y)((X + Y)' + Z) = (X + Y)Z [T5(b)]

Chapter 2 4
 Fundamentals of Boolean Algebra (4)

• Theorem 6
(a) ab + ab' = a (b) (a + b)(a + b') = a

• Examples:
– ABC + AB'C = AC [T6(a)]
– (W' + X' + Y' + Z')(W' + X' + Y' + Z)(W' + X' + Y + Z')(W' + X' + Y + Z)
= (W' + X' + Y')(W' + X' + Y + Z')(W' + X' + Y + Z) [T6(b)]
= (W' + X' + Y')(W' + X' + Y) [T6(b)]
= (W' + X') [T6(b)]

Chapter 2 5
 Fundamentals of Boolean Algebra (5)

• Theorem 7
(a) ab + ab'c = ab + ac (b) (a + b)(a + b' + c) = (a + b)(a + c)

• Examples:
– wy' + wx'y + wxyz + wxz' = wy' + wx'y + wxy + wxz' [T7(a)]
= wy' + wy + wxz' [T7(a)]
= w + wxz' [T7(a)]
=w [T7(a)]
– (x'y' + z)(w + x'y' + z') = (x'y' + z)(w + x'y') [T7(b)]

Chapter 2 6
 Fundamentals of Boolean Algebra (6)

• Theorem 8 (DeMorgan's Theorem)

(a) (a + b)' = a'b' (b) (ab)' = a' + b'

• Generalized DeMorgan's Theorem

(a) (a + b + … z)' = a'b' … z' (b) (ab … z)' = a' + b' + … z'

• Examples:
– (a + bc)' = (a + (bc))'
= a'(bc)' [T8(a)]
= a'(b' + c') [T8(b)]
= a'b' + a'c' [P5(b)]
– Note: (a + bc)' ≠ a'b' + c'

Chapter 2 7
 Fundamentals of Boolean Algebra (7)

• More Examples for DeMorgan's Theorem

– (a(b + z(x + a')))' = a' + (b + z(x + a'))' [T8(b)]
= a' + b' (z(x + a'))' [T8(a)]
= a' + b' (z' + (x + a')') [T8(b)]
= a' + b' (z' + x'(a')') [T8(a)]
= a' + b' (z' + x'a) [T3]
= a' + b' (z' + x') [T5(a)]

– (a(b + c) + a'b)' = (ab + ac + a'b)' [P5(b)]

= (b + ac)' [T6(a)]
= b'(ac)' [T8(a)]
= b'(a' + c') [T8(b)]

Chapter 2 8
 Fundamentals of Boolean Algebra (8)

• Theorem 9 (Consensus)
(a) ab + a'c + bc = ab + a'c (b) (a + b)(a' + c)(b + c) = (a + b)(a' + c)

• Examples:
– AB + A'CD + BCD = AB + A'CD [T9(a)]
– (a + b')(a' + c)(b' + c) = (a + b')(a' + c) [T9(b)]
– ABC + A'D + B'D + CD = ABC + (A' + B')D + CD [P5(b)]
= ABC + (AB)'D + CD [T8(b)]
= ABC + (AB)'D [T9(a)]
= ABC + (A' + B')D [T8(b)]
= ABC + A'D + B'D [P5(b)]

Chapter 2 9
 Switching Functions

• Switching algebra: Boolean algebra with the set of elements K = {0, 1}

• If there are n variables, we can define 2 2 switching functions.
n

• Sixteen functions of two variables (Table 2.3):

AB f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15

00 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
01 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
10 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
• A switching function can be represented by a table as above, or by a switching
expression as follows:
• f0(A,B)= 0, f6(A,B) = AB' + A'B, f11(A,B) = AB + A'B + A'B' = A' + B, ...
• Value of a function can be obtained by plugging in the values of all variables:
The value of f6 when A = 1 and B = 0 is: 1⋅ 0'+1'⋅0 = 0 + 1 = 1.
Chapter 2 10
 Truth Tables (1)

• Shows the value of a function for all possible input combinations.

• Truth tables for OR, AND, and NOT (Table 2.4):

ab f(a,b)=a+b ab f(a,b)=ab a f(a)=a'

00 0 00 0 0 1
01 1 01 0 1 0
10 1 10 0
11 1 11 1

Chapter 2 11
 Truth Tables (2)

• Truth tables for f(A,B,C) = AB + A'C + AC' (Table 2.5)

ABC f(A,B,C) ABC f(A,B,C)

000 0 FFF F
001 1 FFT T
010 0 FTF F
011 1 FTT T
100 1 TFF T
101 0 TFT F
110 1 TTF T
111 1 TTT T

Chapter 2 12
 Algebraic Forms of Switching Functions (1)

• Literal: A variable, complemented or uncomplemented.

• Product term: A literal or literals ANDed together.
• Sum term: A literal or literals ORed together.

• SOP (Sum of Products):

• ORing product terms
• f(A, B, C) = ABC + A'C + B'C

• POS (Product of Sums)

• ANDing sum terms
• f (A, B, C) = (A' + B' + C')(A + C')(B + C')

Chapter 2 13
 Algebraic Forms of Switching Functions (2)

• A minterm is a product term in which all the variables appear

exactly once either complemented or uncomplemented.
• Canonical Sum of Products (canonical SOP):
– Represented as a sum of minterms only.
– Example: f1(A,B,C) = A'BC' + ABC' + A'BC + ABC (2.1)
• Minterms of three variables:
Minterm Minterm Code Minterm Number
A'B'C' 000 m0
A'B'C 001 m1
A'BC' 010 m2
A'BC 011 m3
AB'C' 100 m4
AB'C 101 m5
ABC' 110 m6
ABC 111 m7
Chapter 2 14
 Algebraic Forms of Switching Functions (3)

• Compact form of canonical SOP form:

f1(A,B,C) = m2 + m3 + m6 + m7 (2.2)
• A further simplified form:
f1(A,B,C) = Σ m (2,3,6,7) (minterm list form) (2.3)
• The order of variables in the functional notation is important.
• Deriving truth table of f1(A,B,C) from minterm list:
Row No. Inputs Outputs Complement
(i) ABC f1(A,B,C)= Σ
m(2,3,6,7) f1'(A,B,C)= Σ
m(0,1,4,5)
0 000 0 1 ← m0
1 001 0 1 ← m1
2 010 1 ← m2 0
3 011 1 ← m3 0
4 100 0 1 ← m4
5 101 0 1 ← m5
6 110 1 ← m6 0
7 111 1 ← m7 0
Chapter 2 15
 Algebraic Forms of Switching Functions (4)

• Example: Given f(A,B,Q,Z) = A'B'Q'Z' + A'B'Q'Z + A'BQZ' + A'BQZ, express

f(A,B,Q,Z) and f '(A,B,Q,Z) in minterm list form.

f(A,B,Q,Z) = A'B'Q'Z' + A'B'Q'Z + A'BQZ' + A'BQZ

= m0 + m1 + m6 + m7
= Σ m(0, 1, 6, 7)

f '(A,B,Q,Z) = m2 + m3 + m4 + m5 + m8 + m9 + m10 + m11 + m12

+ m13 + m14 + m15
= Σ m(2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15)
2 n −1

• ∑m
i =0
i =1
(2.6)
• AB + (AB)' = 1 and AB + A' + B' = 1, but AB + A'B' ≠ 1.

Chapter 2 16
 Algebraic Forms of Switching Functions (5)

• A maxterm is a sum term in which all the variables appear

exactly once either complemented or uncomplemented.
• Canonical Product of Sums (canonical POS):
– Represented as a product of maxterms only.
– Example: f2(A,B,C) = (A+B+C)(A+B+C')(A'+B+C)(A'+B+C') (2.7)
• Maxterms of three variables:
Maxterm Maxterm Code Maxterm Number
A+B+C 000 M0
A+B+C' 001 M1
A+B'+C 010 M2
A+B'+C' 011 M3
A'+B+C 100 M4
A'+B+C' 101 M5
A'+B'+C 110 M6
A'+B'+C' 111 M7
Chapter 2 17
 Algebraic Forms of Switching Functions (6)

• f2(A,B,C) = M0M1M4M5 (2.8)

= ΠM(0,1,4,5) (maxterm list form) (2.9)

• The truth table for f2(A,B,C):

Rwo No. Inputs M0 M1 M4 M5 Outputs

(i) ABC A+B+C A+B+C' A'+B+C A'+B+C' f2(A,B,C)
0 000 0 1 1 1 0
1 001 1 0 1 1 0
2 010 1 1 1 1 1
3 011 1 1 1 1 1
4 100 1 1 0 1 0
5 101 1 1 1 0 0
6 110 1 1 1 1 1
7 111 1 1 1 1 1

Chapter 2 18
 Algebraic Forms of Switching Functions (7)

• Truth tables of f1(A,B,C) of Eq. (2.3) and f2(A,B,C) of Eq. (2.7) are identical.
• Hence, f1(A,B,C) = Σ m (2,3,6,7)
= f2(A,B,C)
= ΠM(0,1,4,5) (2.10)
• Example: Given f(A,B,C) = ( A+B+C')(A+B'+C')(A'+B+C')(A'+B'+C'),
construct the truth table and express in both maxterm and minterm form.
– f(A,B,C) = M1M3M5M7 = ΠM(1,3,5,7) = Σ m (0,2,4,6)
Row No. Inputs Outputs
(i) ABC f(A,B,C)= ΠM(1,3,5,7) = Σ
m(0,2,4,6)
0 000 1 m0
1 001 0 ←M1
2 010 1 m2
3 011 0 ←M3
4 100 1 m4
5 101 0 ←M5
6 110 1 m6
Chapter 2 7 111 0 ←M7 19
 Algebraic Forms of Switching Functions (8)

• Relationship between minterm mi and maxterm Mi:

– For f(A,B,C), (m1)' = (A'B'C)' = A + B + C' = M1
– In general, (mi)' = Mi (2.11)
(Mi)' = ((mi)')' = mi (2.12)

Chapter 2 20
 Algebraic Forms of Switching Functions (9)

• Example: Relationship between the maxterms for a function and its

complement.
– For f(A,B,C) = ( A+B+C')(A+B'+C')(A'+B+C')(A'+B'+C')
– The truth table is:

Row No. Inputs Outputs Outputs

(i) ABC f (A,B,C) f '(A,B,C)= ΠM(0,2,4,6)
0 000 1 0 ← M0
1 001 0 1
2 010 1 0 ← M2
3 011 0 1
4 100 1 0 ← M4
5 101 0 1
6 110 1 0 ← M6
7 111 0 1

Chapter 2 21
 Algebraic Forms of Switching Functions (10)

– From the truth table

f '(A,B,C) = ΠM(0,2,4,6) and f(A,B,C) = ΠM(1,3,5,7)
– Since f(A,B,C) ⋅ f '(A,B,C) = 0,
2 3 −1
(M0M2M4M6)(M1M3M5M7) = 0 or ∏ M = 0 i
i =0
2 n −1
– In general, ∏ M = 0 i
(2.13)
i =0
– Another observation from the truth table:
f(A,B,C) = Σ m (0,2,4,6) = ΠM(1,3,5,7)
f '(A,B,C) = Σ m (1,3,5,7) = ΠM(0,2,4,6)

Chapter 2 22
 Derivation of Canonical Forms (1)

• Derive canonical POS or SOP using switching algebra.

• Theorem 10. Shannon's expansion theorem
(a). f(x1, x2, …, xn) = x1 f(1, x2, …, xn) + (x1)' f(0, x2, …, xn)
(b). f(x1, x2, …, xn) = [x1 + f(0, x2, …, xn)] [(x1)' + f(1, x2, …, xn)]

• Example: f(A,B,C) = AB + AC' + A'C

– f(A,B,C) = AB + AC' + A'C = A f(1,B,C) + A' f(0,B,C)
= A(1⋅B + 1⋅C' + 1'⋅C) + A'(0⋅B + 0⋅C' + 0'⋅C) = A(B + C') + A'C
– f(A,B,C) = A(B + C') + A'C = B[A(1+C') + A'C] + B'[A(0 + C') + A'C]
= B[A + A'C] + B'[AC' + A'C] = AB + A'BC + AB'C' + A'B'C
– f(A,B,C) = AB + A'BC + AB'C' + A'B'C
= C[AB + A'B⋅1 + AB'⋅1' + A'B'⋅1] + C'[AB + A'B⋅0 + AB'⋅0' + A'B'⋅0]
= ABC + A'BC + A'B'C + ABC' + AB'C'

Chapter 2 23
 Derivation of Canonical Forms (2)

• Alternative: Use Theorem 6 to add missing literals.

• Example: f(A,B,C) = AB + AC' + A'C to canonical SOP form.
– AB = ABC' + ABC = m6 + m7
– AC' = AB'C' + ABC' = m4 + m6
– A'C = A'B'C + A'BC = m1 + m3
– Therefore,
f(A,B,C) = (m6 + m7) + (m4 + m6) + (m1 + m3) = Σm(1, 3, 4, 6, 7)

• Example: f(A,B,C) = A(A + C') to canonical POS form.

– A = (A+B')(A+B) = (A+B'+C')(A+B'+C)(A+B+C')(A+B+C)
= M3M2M1M0
– (A+C')= (A+B'+C')(A+B+C') = M3M1
– Therefore,
Chapter 2 f(A,B,C) = (M3M2M1M0)(M3M1) = ΠM(0, 1, 2, 3) 24
 Incompletely Specified Functions

• A switching function may be incompletely specified.

• Some minterms are omitted, which are called don't-care minterms.
• Don't cares arise in two ways:
– Certain input combinations never occur.
– Output is required to be 1 or 0 only for certain combinations.
• Don't care minterms: di Don't care maxterms: Di

• Example: f(A,B,C) has minterms m0, m3, and m7 and don't-cares d4 and d5.
– Minterm list is: f(A,B,C) = Σm(0,3,7) + d(4,5)
– Maxterm list is: f(A,B,C) = ΠM(1,2,6)·D(4,5)
– f '(A,B,C) = Σm(1,2,6) + d(4,5) = ΠM(0,3,7)·D(4,5)
– f (A,B,C)= A'B'C' + A'BC + ABC + d(AB'C' + AB'C)
= B'C' + BC (use d4 and omit d5)

Chapter 2 25
 Electronic Logic Gates (1)

• Electrical Signals and Logic Values

Electric Signal Logic Value

Positive Logic Negative Logic
High Voltage (H) 1 0
Low Voltage (L) 0 1

– A signal that is set to logic 1 is said to be asserted, active, or true.

– An active-high signal is asserted when it is high (positive logic).
– An active-low signal is asserted when it is low (negative logic).

Chapter 2 26
 Electronic Logic Gates (2)

a a &
AND f ( a ,  b ) =  ab AND f ( a ,  b ) =  ab
b b
³
a a 1
OR f ( a ,  b ) =  a  +  b OR f ( a ,  b ) =  a  +  b
b b
a 1
NOT a f ( a ) =  a NOT f ( a ) =  a
b
a a &
NAND f ( a ,  b ) =  ab NAND f ( a ,  b ) =  ab
b b
³
a a 1
NOR f ( a ,  b ) =  a  +  b NOR f ( a ,  b ) =  a  +  b
b b
EXCLUSIVE a f ( a ,  b ) =  a EXCLUSIVE a
OR
⊕ b
OR
= 1 f ( a ,  b ) =  a ⊕ b
b b

Symbol set 1 Symbol set 2
(ANSI/IEEE Standard 91­1984)

Chapter 2 27
 Electronic Logic Gates (3)
V cc 4B 4A 4Y 3B 3A 3Y V cc 4Y 4B 4A 3Y 3B 3A
14 13 12 11 10 9 8 14 13 12 11 10 9 8

1 2 3 4 5 6 7 1 2 3 4 5 6 7
1A 1B 1Y 2A 2B 2Y GND 1Y 1A 1B 2Y 2A 2B GND
7400:  Y  =  AB 7402:  Y  =  A  +  B
Quadruple two­input NAND gates Quadruple two­input NOR gates

V cc 6A 6Y 5A 5Y 4A 4Y V cc 4B 4A 4Y 3B 3A 3Y
14 13 12 11 10 9 8 14 13 12 11 10 9 8

1 2 3 4 5 6 7 1 2 3 4 5 6 7
1A 1Y 2A 2Y 3A 3Y GND 1A 1B 1Y 2A 2B 2Y GND
7404:  Y  =  A 7408:  Y  =  AB
Hex inverters Quadruple two­input AND gates

Chapter 2 28
 Electronic Logic Gates (4)

V cc 1C 1Y 3C 3B 3A 3Y V cc 2D 2C NC 2B 2A 2Y
14 13 12 11 10 9 8 14 13 12 11 10 9 8

1 2 3 4 5 6 7 1 2 3 4 5 6 7
1A 1B 2A 2B 2C 2Y GND 1A 1B NC 1C 1D 1Y GND
7410:  Y  =  ABC 7420:  Y  =  ABCD
Triple three­input NAND gates Dual four­input NAND gates

Chapter 2 29
 Electronic Logic Gates (5)

V cc NC H G NC NC Y V cc 4B 4A 4Y 3B 3A 3Y
14 13 12 11 10 9 8 14 13 12 11 10 9 8

1 2 3 4 5 6 7 1 2 3 4 5 6 7
A B C D E F GND 1A 1B 1Y 2A 2B 2Y GND
7430:  Y  =  ABCDEFGH 7432:  Y  =  A  +  B
8­input NAND gate Quadruple two­input OR gates

V cc 4B 4A 4Y 3B 3A 3Y
14 13 12 11 10 9 8

1 2 3 4 5 6 7
1A 1B 1Y 2A 2B 2Y GND
7486:  Y  =  A  Å   B
Quadruple two­input exclusive­OR gates

Chapter 2 30
 Basic Functional Components (1)

• AND

A
a b f AND   ( a ,  b ) =  ab A B Y Y
B
0 0 0 L L L (c)
0 1 0 L H L
1 0 0 H L L A & Y
1 1 1 H H H B
(a) (b) (d)

(a) AND logic function.

(b) Electronic AND gate.
(c) Standard symbol.
(d) IEEE block symbol.

Chapter 2 31
 Basic Functional Components (2)

• OR

A
a b f OR ( a ,  b ) =  a  +  b A B Y Y
B
0 0 0 L L L (c)
0 1 1 L H H
1 0 1 H L H A ≥1 Y
1 1 1 H H H B
(a) (b) (d)

(a) OR logic function.

(b) Electronic OR gate.
(c) Standard symbol.
(d) IEEE block symbol.

Chapter 2 32
 Basic Functional Components (3)

• Meaning of the designation ≥ 1 in IEEE symbol:

ab sum(a, b) sum(a, b) ≥
1 fOR(a, b) = a + b
00 0 False 0
01 1 True 1
10 1 True 1
11 2 True 1

Chapter 2 33
 Basic Functional Components (4)

• NOT

A Y
(c)
a f NOT   ( a ) =  a A Y
0 1 L H A 1 Y
1 0 H L
(a) (b) (d)

(a) NOT logic function.

(b) Electronic NOT gate.
(c) Standard symbol.
(d) IEEE block symbol.

Chapter 2 34
 Basic Functional Components (5)

• Positive Versus Negative Logic

Positive Logic Negative Logic

1 is represented by High Voltage Low Voltage
0 is represented by Low Voltage High Voltage

Chapter 2 35
 Basic Functional Components (6)

• AND Gate Usage in Negative Logic

A B Y a
y  =  a  +  b
1 1 1 b
1 0 1 A
Y (c)
0 1 1 B
0 0 0 a
(a) (b) y  =  ab
b
(d)
– (a) AND gate truth table (L = 1, H = 0)
– (b) Alternate AND gate symbol (in negative logic)
– (c) Preferred usage
– (d) Improper usage
– y = a·b = (2.14)
a ⋅ b = a + b = fOR (a , b )
– (2.15)
y = (a ) + (b ) = a + b = fOR ( a, b)
Chapter 2 36
 Basic Functional Components (7)

• OR Gate Usage in Negative Logic

A B Y a
y  =  ab
1 1 1 b
1 0 0 A
Y (c)
0 1 0 B
0 0 0 a
(a) (b) y  =  a  +  b
b
(d)

– (a) OR gate truth table(L = 1, H = 0)

– (b) Alternate OR gate symbol (in negative logic)
– (c) Preferred usage
– (d) Improper usage
– y = a + b = a + b = a ⋅ b = fAND (a , b ) (2.16)
– (2.17)
y = (a ) ⋅ (b ) = a ⋅ b = fAND (a, b)
Chapter 2 37
 Basic Functional Components (8)

• Example 2.32: Building smoke alarm system

– Components: two smoke detectors, a sprinkler, and an automatic
telephone dialer
– Behavior:
• Sprinkler is activated if either smoke detector detects smoke.
• When both smoke detector detect smoke, fire department is called.
– Signals:
• D1, D 2 : Active-low outputs from two smoke detectors.
• : Active-low input to the sprinkler
SPK
• DIAL : Active-low input to the telephone dialer.
– Logic equations
• SPK = D1 + D 2 (2.18)
• DIAL = D1⋅ D 2 (2.19)

Chapter 2 38
 Basic Functional Components (9)

• Logic diagram of the smoke alarm system

Smoke
detectors
Sprinkler
D1 D 1  + D 2
G1
D2
SPK

Telephone
D 1 D 2 dialer
G2
DIAL

Chapter 2 39
 Basic Functional Components (10)

• NAND

a b f NAND   ( a ,  b ) =  ab A B Y

0 0 1 L L H
0 1 1 L H H
1 0 1 H L H
1 1 0 H H L
(a) (b)

A A A &
Y Y Y
B B B

(c) (d) (e)

– (a) NAND logic function

– (b) Electronic NAND gate
– (c) Standard symbol
– (d) IEEE block symbol

Chapter 2 40
 Basic Functional Components (10)

• Matching signal polarity to NAND gate inputs/outputs

– (a) Preferred usage (b) Improper usage

a a
y y
b b

a a
y y
b b
(a) (b)

• Additional properties of NAND gate:

fNAND (a, a) = a ⋅ a = a = fNOT (a )

fNAND (a, b) = a ⋅ b = a ⋅ b = fAND (a, b)
fNAND (a , b ) = a ⋅ b = a + b = fOR (a, b)
• Hence, NAND gate may be used to implement all three elementary operators.
Chapter 2 41
 Basic Functional Components (11)

• AND, OR, and NOT gates constructed exclusively from NAND gates

a ab a f ( a ,  a )  = a  a  =  a
f ( a ,  b ) =  ab  =  ab
b

AND gate NOT gate

a a
f ( a ,  b ) =  a  +  b  =  a  +  b

b
b
OR gate

Chapter 2 42
 Basic Functional Components (12)

• NOR

a b f NOR   ( a ,  b ) =  a + b A B Y

0 0 1 L L H
0 1 0 L H L
1 0 0 H L L
1 1 0 H H L
(a) (b)

A A A ³1
Y Y Y
B B B

(c) (d) (e)

– (a) NAND logic function

– (b) Electronic NAND gate
– (c) Standard symbol
– (d) IEEE block symbol
Chapter 2 43
 Basic Functional Components (13)

• Matching signal polarity to NOR gate inputs/outputs

– (a) Preferred usage (b) Improper usage

a a
y y
b b

a a
y y
b b
(a) (b)
• Additional properties of NAND gate:

fNOR (a, a) = a + a = a = fNOT (a)

fNOR (a, b) = a + b = a + b = fOR (a, b)
fNOR (a , b ) = a + b = a ⋅ b = fAND (a, b)
• Hence, NAND gate may be used to implement all three elementary operators.

Chapter 2 44
 Basic Functional Components (14)

• AND, OR, and NOT gates constructed exclusively from NOR gates.

a a  +  b
f ( a ,  b ) =  a  +  b a f ( a ,  a ) =  a  +  a  =  a
b

OR gate NOT gate

a a
f ( a ,  b ) =  ab  =  ab

b
b
AND gate

Chapter 2 45
 Basic Functional Components (15)

• Exclusive-OR (XOR)
– fXOR(a, b) = a ⊕ b = a b + ab (2.24)

ab fXOR(a, b) = a ⊕
b AB Y
00 0 LL L
01 1 LH H
10 1 HL H
11 0 HH L
(a) XOR logic function (b) Electronic XOR gate

A A
Y =1 Y
B B

(c) Standard symbol (d) IEEE block symbol

Chapter 2 46
 Basic Functional Components (16)

• POS of XOR
a ⊕ b = a b + ab
= a a + a b + ab + bb [P2(a), P6(b)]
[P5(b)]
= a ( a + b) + b ( a + b )
[P5(b)]
= (a + b )(a + b)

• Some other useful relationships

– a⊕a=0 (2.25)
– a⊕ a =1 (2.26)
– a⊕0=a (2.27)
– a⊕1= a (2.28)
– a ⊕b = a⊕b (2.29)
– a⊕b=b⊕a (2.30)
– a ⊕ (b ⊕ c) = (a ⊕ b) ⊕ c (2.31)
Chapter 2 47
 Basic Functional Components (17)

• Output of XOR gate is asserted when the mathematical sum of inputs is one:

ab sum(a, b) sum(a, b) = 1? f(a, b) = a ⊕

b
00 0 False 0
01 1 True 1
10 1 True 1
11 2 False 0

• The output of XOR is the modulo-2 sum of its inputs.

Chapter 2 48
 Basic Functional Components (18)

• Exclusive-NOR (XNOR)
– fXNOR(a, b) = a ⊕ b = a b (2.32)

A
a b f XNOR ( a ,  b ) =  a      b A B Y Y
B
0 0 1 L L H (c)
0 1 0 L H L
1 0 0 H L L A =1
1 1 1 H H H Y
B
(a) (b)
(d)

– (a) XNOR logic function

– (b) Electronic XNOR gate
– (c) Standard symbol
– (d) IEEE block symbol

Chapter 2 49
 Basic Functional Components (19)

• SOP and POS of XNOR

a b = a⊕b
[P2]
= a b + ab
[T8(a)]
= a b ⋅ ab
= (a + b )(a + b) [T8(b)]
= aa + ab + a b + b b [P5(b)]
= ab + a b [P6(b), P2(a)]

• a⊕b = a b

Chapter 2 50
 Analysis of Combinational Circuits (1)

• Digital Circuit Design:

– Word description of a function
⇒ a set of switching equations
⇒ hardware realization (gates, programmable logic devices, etc.)

• Digital Circuit Analysis:

– Hardware realization
⇒ switching expressions, truth tables, timing diagrams, etc.

• Analysis is used
– To determine the behavior of the circuit
– To verify the correctness of the circuit
– To assist in converting the circuit to a different form.

Chapter 2 51
 Analysis of Combinational Circuits (2)

• Algebraic Method: Use switching algebra to derive a desired form.

• Example 2.33: Find a simplified switching expressions and logic network for
the following logic circuit (Fig. 2.21a).

a P1
b
P4

a
c P2 f  ( a ,  b ,  c )

b P3
c
(a)

Chapter 2 52
 Analysis of Combinational Circuits (3)

• Write switching expression for each gate output:

– P = ab, P = a + c, P3 = b ⊕ c , P4 = P1 ⋅ P2 = ab ⋅ (a + c)
1 2
• The output is: f (a, b, c) = P + P = (b ⊕ c ) + ab ⋅ (a + c)
3 4
• Simplify the output function using switching algebra:
f (a, b, c) = (b ⊕ c ) + ab ⋅ a + c
= bc + b c + ab ⋅ a + c [Eq. 2.24]
= bc + b c + (a + b )ac [T8]
[T5(b)]
= bc + b c + ab c
= bc + b c [T4(a)]
f ( a , b, c ) = b c [Eq. 2.32]
Therefore, f (a,b,c) = (b c)' = b ⊕ c
b f  ( a ,  b ,  c )
c

Chapter 2 53
 Analysis of Combinational Circuits (4)

• Example 2.34: Find a simplified switching expressions and logic network for
the following logic circuit (Fig. 2.22).

a a       b
b
( a       b )( b       c )

b
c b       c
f  ( a ,  b ,  c )

a a  +  b
b

a a  +  b  +  a  +  c
c a  +  c
Given circuit

Chapter 2 54
 Analysis of Combinational Circuits (5)

• Derive the output expression:

f(a,b,c)
= (a ⊕ b)(b ⊕ c) ⋅ (a + b + a + c)
= (a ⊕ b)(b ⊕ c) + a + b + a + c) [T8(b)]
= (a ⊕ b)(b ⊕ c) + (a + b )(a + c) [T8(a)]
= (ab + a b)(bc + b c) + (a + b )(a + c) [Eq. 2.24]
= ab bc + ab b c + a bbc + a bb c + a a + a c + ab + b c [P5(b)]
= ab c + a bc + a c + ab + b c [P6(b), T4(a)]
= a bc + a c + ab + b c [T4(a)]
= a bc + a c + ab [T9(a)]
a
= a b + a c + ab c [T7(a)]
f  ( a ,  b ,  c )
= ac + a ⊕ b [Eq. 2.24]
a
b
Simplified circuit

Chapter 2 55
 Analysis of Combinational Circuits (6)

• Truth Table Method: Derive the truth table one gate at a time.

• The truth table for Example 2.34:

abc ac a⊕b f(a,b,c)

000 0 0 0
001 1 0 1
010 0 1 1
011 1 1 1
100 0 1 1
101 0 1 1
110 0 0 0
111 0 0 0

Chapter 2 56
 Analysis of Combinational Circuits (7)

• Analysis of Timing Diagrams

– Timing diagram is a graphical representation of input and output signal
relationships over the time dimension.
– Timing diagrams may show intermediate signals and propagation delays.

Chapter 2 57
 Analysis of Combinational Circuits (8)

• Example 2.35: Derivation of truth table from a timing diagram

A
A
B Y  =   f a   ( A ,  B ,  C ) B

C
Inputs
Outputs

Z  =   f b   ( A ,  B ,  C ) Y  =   f a   ( A ,  B ,  C )

Z  =   f b   ( A ,  B ,  C )
C
t0 t1 t2 t3 t4 t5 t6 t7
(a)
(b)

Inputs Outputs
Time ABC f a ( A ,  B ,  C ) f b ( A ,  B ,  C )
t0 0 0 0 0 0
t1 0 0 1 1 1
t2 0 1 0 1 0
t3 0 1 1 0 1
t4 1 0 0 0 0
t5 1 0 1 0 1
t6 1 1 0 1 1
t7 1 1 1 1 0
Chapter 2 (c) 58
 Analysis of Combinational Circuits (9)

• Propagation Delay
– Physical characteristics of a logic circuit to be considered:
• Propagation delays
• Gate fan-in and fan-out restrictions
• Power consumption
• Size and weight

– Propagation delay: The delay between the time of an input change and
the corresponding output change.
– Typical two propagation delay parameters:
• tPLH = propagation delay time, low-to-high-level output
• tPHL = propagation delay time, high-to-low-level output
– Approximation:
t +t
• t PD = PLH PHL
2
Chapter 2 59
 Analysis of Combinational Circuits (10)

• Propagation delay through a logic gate

b
a
c
b c

(a) Two­input AND gate (b) Ideal (zero) delay

a a

b b

c c
t PD t PD t PLH t PHL
(c)  t PD  =   t PLH  =   t PHL (d)  t PLH  <  t PHL

Chapter 2 60
 Analysis of Combinational Circuits (11)

• Power dissipation and propagation delays for several logic families (Table 2.7)

Logic Propagation Delay Power Dissipation

Family tPD(ns) Per Gate (mW) Technology
7400 10 10 Standard TTL
74H00 6 22 High-speed TTL
74L00 33 1 Low-power TTL
74LS00 9.5 2 Low-power Schottky TTL
74S00 3 19 Schottky TTL
74ALS00 3.5 1.3 Advanced low-power
Schottky TTL
74AS00 3 8 Advanced Schottky TTL
74HC00 8 0.17 High-speed CMOS

Chapter 2 61
 Analysis of Combinational Circuits (12)

• Propagation delays of primitive 74LS series gates (Table 2.8)

tPLH tPHL
Chip Function Typical Maximum Typical Maximum
74LS04 NOT 9 15 10 15
74LS00 NAND 9 15 10 15
74LS02 NOR 10 15 10 15
74LS08 AND 8 15 10 20
22
74LS32 OR 14 22 14 22

Chapter 2 62
 Analysis of Combinational Circuits (13)

• Example 2.36: Given a circuit diagram and the timing diagram, find the truth
table and minimum switching expression.
D
C F
A ABC f   ( A ,  B ,  C )
Y  =   f   ( A ,  B ,  C ) 0 0 0 0
0 0 1 1
E 0 1 0 0
B G 0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
A
1 1 1 0
B

D f ( A, B, C )
E
= ∑ m(1,4,5,6)
F

G
= A B C + AB C + AB C + ABC
f   ( A ,  B ,  C ) = AC + B C
t0 t1 t3 t4 t5 t6 t7
t 1  + 2 t2 t 2  + 2 t 4  + 3 t 7  + 3
t 4  + 2 t 7  + 2
t 1  + 1 t 2  + 1 t 4  + 1 t 7  + 1

Chapter 2 63
 Synthesis of Combinational Logic Circuits (1)

• AND-OR and NAND Networks

– Switching expression must be in SOP form.
– Example: fδ ( p, q, r , s ) = pr + qrs + ps
Bubbles
Òcancel
Ó
p p p
x1 x1
r r r
q f d    ( p ,  q ,  r ,  s ) q x2 f d    ( p ,  q ,  r ,  s ) q x2 f d    ( p ,  q ,  r ,  s )
r r r
s s s
p p x3 p x3
s s s
(a) AND­OR network (b) NAND network (c) NAND network (preferred form)

– fδ ( p, q, r , s ) = pr + qrs + ps [T3]
= pr ⋅ qrs ⋅ ps [T8(a)]
= x1 ⋅ x2 ⋅ x3
where x1 = pr , x2 = qrs, and x3 = ps

Chapter 2 64
 Synthesis of Combinational Logic Circuits (2)

• OR-AND and NOR Networks

– Switching expression must be in POS form.
– Example: fε ( A, B, C , D) = ( A + B + C )( B + C + D)( A + D)
A A A
B B y1 B y1
C C C
B f e    ( A ,  B ,  C ,  D ) B y2 f e    ( A ,  B ,  C ,  D ) B y2 f e    ( A ,  B ,  C ,  D )
C C C
D D D
A A y3 A y3
D D D
(a) OR­AND network (b) NOR network (c) NOR network (preferred form)

– fε ( A, B, C , D) = ( A + B + C )( B + C + D)( A + D) [T3]
= A + B+C + B+C + D+ A + D [T8(b)]
= y1 + y2 + y3

where y1 = A + B + C , y2 = B + C + D, and y3 = A + D

Chapter 2 65
 Synthesis of Combinational Logic Circuits (3)

• Two-level Circuits
– Input signals pass through two levels of gates before reaching the output.

p p
x1 x1
r r
q x2 f d    ( p ,  q ,  r ,  s ) q x2 f d    ( p ,  q ,  r ,  s )
r r
s s
p x3 p x3
s s
Level 2 Level 1 Level 3 Level 2 Level 1
(a) Two­level network (b) Three­level network

– Implementation procedure for NAND (NOR) logic:

• Step 1. Express the function in minterm (maxterm) list form.
• Step 2. Write out the minterms (maxterms) in algebraic form.
• Step 3. Simplify the function in SOP (POS) form.
• Step 4. Transform the expression into the NAND (NOR) form.
• Step 5. Draw the NAND (NOR) logic diagram.
Chapter 2 66
 Synthesis of Combinational Logic Circuits (4)

• Circuits with more than two levels are often needed due to fan-in constraints.

a
b
c f  =  abcde
d
e
(a) A single five­input AND gate

a
a b
b
c
c
d
d f  =  abcde
f  =  abcde
e e
(b) Three­level network of two­input gates (c) Four­level network of two­input gates.

Chapter 2 67
 Synthesis of Combinational Logic Circuits (5)

• Example 2.37: NAND implementation of fφ (X,Y,Z) = Σm(0,3,4,5,7)

1. fφ (X,Y,Z) = Σm(0,3,4,5,7)
2. fφ (X,Y,Z) = m0 + m3 + m4 + m5 + m7
= XY Z + XYZ + XY Z + XY Z + XYZ
3. fφ ( X , Y , Z ) = Y Z + YZ + XZ [T6(a)]
4a. fφ ( X , Y , Z ) = Y Z + YZ + XZ [T4]
or
4b. fφ ( X , Y , Z ) = Y Z + YZ + XZ [T3]
= Y Z ⋅ YZ ⋅ XZ [T8(a)]
Y
Z

Y f    ( X ,  Y ,  Z )
Z

X
Z
(a) NAND implementation
Chapter 2 68
 Synthesis of Combinational Logic Circuits (6)

• AND-OR-invert Circuits
– A set of AND gates followed by a NOR gate.
– Used to readily realize two-level SOP circuits.
– 7454 circuit: F = AB + CD + EF + GH

Make no external
connection
V cc B H G Y
14 13 12 11 10 9 8 A
Y1
B

C
Y2
D
Y
Output
E
Y3
F

G
Y4
H

1 2 3 4 5 6 7
A C D E F NC GND Enable lines
(a) 7454 circuit package (top view) (b) 7454 used as a 4­to­1 multiplexer
Chapter 2 69
 Synthesis of Combinational Logic Circuits (7)

• Factoring
– A technique to obtain higher-level forms of switching functions.
– Higher-level forms:
• May need less hardware
• May be used when there are fan-in constraints
• More difficult to design
• Slower
• Example 2.39:
f ( A, B, C , D) = AB + AD + AC = A( B + D + C ) = A( BCD )

A
B A f    ( A ,  B ,  C ,  D )
A f    ( A ,  B ,  C ,  D )
D B
C
A D
C
Chapter 2 (a) Original form (b) After factoring 70
 Synthesis of Combinational Logic Circuits (8)

• Example 2.40: f (a,b,c,d) = Σm(8,13) with only two-input AND and OR gates.
– Write the canonical SOP form:
f (a,b,c,d) = Σm(8,13) = ab c d + abc d (2.34)
Two four-input AND gates and one two-input OR gate are needed.
– Apply factoring:
f (a, b, c, d ) = ab c d + abc d = (ac )(bd + b d ) (2.35)

b
d

f   = ( a ,  b ,  c ,  d )

c
a
Chapter 2 71
 Synthesis of Combinational Logic Circuits (9)

• Example 2.41: A burglar alarm with four control switches, each of which
produces logic 1 when:
Switch A: Secret switch is closed
Switch B: Safe is in its normal position in the closet
Switch C: Clock is between 1000 and 1400 hours
Switch D: Closet door is closed.
Write the equations of the control logic that produces logic 1 when
the safe is moved AND the secret switch is closed,
OR
the closet is opened after banking hours,
OR
the closet is opened with the control switch open.

f ( A, B, C , D) = AB + C D + A D

Chapter 2 72
 Synthesis of Combinational Logic Circuits (10)

• Example 2.42: The Doe family voter:

– Vote for either hamburgers (0) or chicken (1).
– Majority wins.
– If Mom and Dad agree, they win.
– John (Dad): A, Jane (Mom):B, Joe: C, Sue: D.
– The logic function is:
f ( A, B, C , D) = A BCD + AB CD + ABC D + ABC D + ABCD + ABCD
= A BCD + AB CD + AB
= AB + ACD + A BCD
= AB + ACD + BCD
A
B

C
D
  f   ( A ,  B ,  C ,  D )

Chapter 2 73
 Synthesis of Combinational Logic Circuits (11)

• Example 2.43: Logic equations for a circuit that adds two 2-bit binary
numbers (A1A0)2 and (B1B0)2, and produces sum bits (S1S0)2 and carry bit C1;

A 1A 0
+ B1 B0
C1S1S0

Chapter 2 74
 Synthesis of Combinational Logic Circuits (12)

• Truth Table: • Logic equations:

A1 A0 B1 B0 C1 S1 S0 S0 = A1 A0 B1B0 + A1 A0 B1B0 + A1 A0 B1B0
0 0 0 0 0 0 0
0 0 0 1 0 0 1 + A1 A0 B1B0 + A1 A0 B1B0 + A1 A0 B1B0
0 0 1 0 0 1 0 + A1 A0 B1B0 + A1 A0 B1B0
0 0 1 1 0 1 1
0 1 0 0 0 0 1
0 1 0 1 0 1 0 S1 = A1 A0 B1B0 + A1 A0 B1B0 + A1 A0 B1B0
0 1 1 0 0 1 1 + A1 A0 B1B0 + A1 A0 B1B0 + A1 A0 B1B0
0 1 1 1 1 0 0
1 0 0 0 0 1 0
+ A1 A0 B1B0 + A1 A0 B1B0
1 0 0 1 0 1 1
1 0 1 0 1 0 0
1 0 1 1 1 0 1 C1 = A1 A0 B1B0 + A1 A0 B1B0 + A1 A0 B1B0
1 1 0 0 0 1 1 + A1 A0 B1B0 + A1 A0 B1B0 + A1 A0 B1B0
1 1 0 1 1 0 0
1 1 1 0 1 0 1
1 1 1 1 1 0 0
Chapter 2 75
 Synthesis of Combinational Logic Circuits (13)

• Reduced equations:

S0 = A0 B0 + A0 + B0

S1 = A1 A0 B1 + A1B1B0 + A1 A0 B1B0
+ A1 A0 B1B0 + A1B1B0 + A1 A0 B1

C1 = A0 B1B0 + A1 A0 B0 + A1B1

Chapter 2 76
 Computer-aided Design (1)

• Design Cycle

Concept

Modeling
and
design capture

Synthesis

Design Design Test

optimization database vectors

Logic
simulation
Analysis

Fail Results
?
Pass

Implementation
Realization

Physical
design

Testing
Test

Finished circuit

Chapter 2 77
 Computer-aided Design (2)

• Digital Circuit Modeling

– Purpose of modeling:
• Helps the designer formalize a solution.
• To check errors, verify correctness, and predict timing characteristics.
– CAD tools are available for design optimization and transformation of
design from abstract form to a physical realization.
– Model can represent different levels of design abstraction.

Level Abstraction
Behavioral Algorithms to be realized
Register • Structure of modules
Transfer • Data flow among modules and control algorithm
Gate Structure of primitive logic gates
Transistor Structure of transistors and low-level components
Layout Geometric patterns of materials for IC layout
Chapter 2 78
 Computer-aided Design (3)

• High-level abstract model (behavioral model)

– Describes only desired behavior.
– Usually represented using a hardware description language (HDL), e.g.,
VHDL or Verilog.
– Other representation mechanisms: logic equations, truth tables, and
minterm or maxterm lists.

Chapter 2 79
 Computer-aided Design (4)

• Behavioral models of a full-adder circuit:

(a) block diagram, (b) truth table, (c) logic equations.

a  b c in
a  b c in c out s
0 0 0 0 0
0 0 1 0 1 s  =  a         b         c
Full_adder 0 1 0 0 1 in

0 1 1 1 0 c out   =  ab  +  ac in   +  bc in

1 0 0 0 1
1 0 1 1 0 (c)
1 1 0 1 0
c out s 1 1 1 1 1
(a) (b)

Chapter 2 80
 Computer-aided Design (5)

• VHDL behavioral model of a full adder circuit (Figure 2.38)

– Entity defines the interface between the circuit and the outside world.
– Architecture defines the function implemented within the circuit.
– Multiple architectures may be defined for a given entity.

• Structural model
– Interconnection of components.
– Behavior is deduced from the behavioral models of individual
components and their interconnection.
– Represented by:
• Logic or schematic diagram
• Netlist (textual representation of schematic diagram)
• HDL description of circuit structures.

Chapter 2 81
 Computer-aided Design (6)

• Structural models of a full-adder circuit:

(a) schematic diagram, (b) netlist
a
I1 x1
b X1 s
I2 X2 O1
c in
I3 I1 IN a
I2 IN b
a1 I3 IN c in
A1 X1 XOR2 x1 a b
X2 XOR2 s x1 c in
a2 c out A1 AND2 a1 a b
A2 R1 O2 A2 AND2 a2 a c in
A3 AND2 a3 b c in
R1 OR3 c out a1 a2 a3
a3 O1 OUT s
A3
O2 OUT c out

(a) (b)

– In a netlist, each circuit element is defined as follows:

gate_name, gate_type, output, input1, input2, …, inputN
– VHDL structural model of a full-adder circuit: Figure 2.40.
Chapter 2 82
 Computer-aided Design (7)

• Mixed-mode model
– Contains both behavioral and structural components.
– Mixed-mode model of the full-adder circuit: (a) full-adder block diagram,
(b) circuit for sum function, (c) truth table for carry function.

a  b c in c out
a
b Sum s 0 0 0 0
c in module 0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
Carry 1 0 1 1
c out 1 1 0 1
module
1 1 1 1

(a) (c)

a
b s
c in

(b)
Chapter 2 83
 Computer-aided Design (8)

• Design synthesis process

Behavioral models

HDL model Truth table Logic equations

Function Automatic Automatic

library synthesis synthesis Structural models

Schematic Netlist

Logic
equations Design
Component
library optimization

Constraints Minimize
Schematic

Optimized
Back logic Netlist
annotation equations generation

Map design
Component onto circuit
library elements

Circuit
netlist

Chapter 2 84
 Computer-aided Design (9)

• Capture tools
– Each circuit model in the design process must be captured in a format that
can be stored and processed by a digital computer.
– Schematic capture: an interactive graphics tool with which a designer
draws a logic diagram.

Chapter 2 85
 Computer-aided Design (10)

• Schematic capture process

MENU DRAWING AREA MENU DRAWING AREA

ZOOM ZOOM Parts Library

IN OUT and2
and3
SELECT DELETE
or2
COPY MOVE or3
nand2
nand3
PLACE DRAW
COMP NET nor2
nor3
NAME PARAM xor2
not
OPEN SAVE in
SHEET SHEET out

(a) (b)

MENU DRAWING AREA MENU DRAWING AREA

a
ZOOM ZOOM ZOOM ZOOM 11 x1
IN OUT IN OUT b X1 s
12 X2 O1
cin
SELECT DELETE SELECT DELETE 13

COPY MOVE COPY MOVE

a1
A1
PLACE DRAW PLACE DRAW
COMP NET COMP NET
a2 cout
A2 R1 O2
NAME PARAM NAME PARAM
a3
OPEN SAVE OPEN SAVE A3
SHEET SHEET SHEET SHEET

(c) (d)

Chapter 2 86
 Computer-aided Design (11)

• Logic Simulation
– Three primary purposes:
1. Logic verification: only logical correctness is checked.
2. Performance analysis: propagation delays and potential timing
problems are analyzed.
3. Test development (fault simulation): helps develop optimal test set.
– Simulation environment

Design

Netlist Test
vectors

Component Simulator
models

Logic Timing
verification analysis
data data
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• Simulation Test Inputs

– Test set: a carefully designed set of test inputs.
– For logic verification, a list of input vectors is used (time is ignored).
– For timing analysis, the time of each input change is also specified.
functional
test set for input tabular waveform

full-adder waveform format format

a  b c in
0 0 0 Time a b c in a   = 0 :0, 10 :1;
a b   = 0 :0, 5:1,15:0;
0 0 1 0 0 0 0
0 1 0 c in   = 0 :0;
b 5 0 1 0
0 1 1 10 1 1 0
1 0 0 c 15 1 0 0
1 0 1
1 1 0 0 5 10 15
1 1 1
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• Event-Driven Simulation
– Event: a change in the value of a signal at a given time.
– Event-driven simulation example for an AND gate:

b
a c
c
b

T0 T1 T 1   +     t T2
(a) (b)

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• Event-driven simulation procedure

– Input test set is converted into a set of events.
– The set of events are entered into an event queue (or event list).
– In each simulation step, the first event is retrieved and is made to occur.
– Output of each affected gate is recomputed, and new event is created.
– Record of all events along with output results are maintained.
– Simulation continues until the event queue is empty or time limit expires.

Time a b c in c out s Time a b c in c out s

a
0 00 0 0 X X 0 0 0 0 X X
2 0 0 0 0 0 2 0 0 0 0 0
b 0
4 0 0 0 0 5 0 1 0 0 0
c in 6 0 1 0 0 0 7 0 1 0 0 1
8 1 1 0 0 1 10 1 1 0 0 1
10 1 1 0 0 1 12 1 1 0 1 0
c out 1
12 1 0 1 0 15 1 0 0 1 0
14 1 0 1 0 17 1 0 0 0 1
s 16 1 0 0 1 0
18 1 0 0 0 1
0 5 7 10 12 15 17 20 20 1 0 0 0 1

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• Debugging a full-adder using simulation

erroneous simulation output: expanded simulation:

full-adder error in s at time 3 isolates error to n3
circuit

Time a  b c in s Time a bc in n1 n2 n3 n4 s
a n1
00 0 0 X XX X X
0 0 0 0 X 10 0 0 1 1X 1X
3 0 0 0 1
n2
b 20 0 0 1 10 1X
30 0 0 1 10 11
n3
s 5 0 1 0 1 50 1 0 1 10 11
c in 10 1 1 0 1 10 1
12 1
1
1
0
0
1 10 11
1 11 11
n4 13 1 1 0 0 13 1 1 0 1 11 10
15 1 0 0 1 11 10
15 1 0 0 0 17 1 0 0 1 01 10
18 1 0 0 1 18 1 0 0 1 01 11

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• Detection of static hazard via simulation

– A glitch in g at time t3 can be detected from the output waveforms.
– This occurs because both e and f become 0 momentarily between t2 and t3.

d
e

f
a e g
b g
d
c f Time   t   t   t
t1 t2 t3 t4

(a) (b)

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• Symbolic Logic Signal Values

– Designers sometimes need signal values other than just 0 or 1.
– Logic signal values are represented by a state and a strength.
– A third state X represents an unknown state or a potential problem.
– Truth tables for three-valued logic (with X added)

AND 0 1 X OR 0 1 X NOT 0
0 0 0 0 0 0 1 X 0 1
1 0 1 X 1 1 1 1 1 0
X 0 X X X X 1 X X X

– Signal strength values:

• Forcing (F): signal line is strongly forced to a given state.
• Resistive (R): signal line is weakly forced to a given state.
• Floating (Z): signal line is not forced forced at all.
• Unknown (U): signal strength cannot be determined.
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• Signal strengths are used to resolve conflicting gate outputs:

output resolved in favor of output value

stronger signal. unable to be resolved

V CC

F0 I1 F1

Ux

I1 I2
F0 R1 F1
F0
F0
(b)
I2
F1
F0

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• Primitive Device Delay Models

– Every primitive logic gate has an intrinsic delay.
– A gate can be modeled as an ideal (zero-delay) gate and a transport delay
element.

a c*
  t c
b
Ideal Time
gate delay

– Different models of transport delays:

• Unit/Nominal Delay
• Rise Fall Delay
• Ambiguous or Min/Max Delay

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• Unit/Nominal Delay
– Unit delay: assign to each gate in a circuit the same unit delay.
– Nominal delay: delays are determined separately for each type of gate
(e.g., on time unit for NOR and two time units for XOR).

 t   t

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• Rise/Fall Delay
– Different delays for 0 to 1 transition and 1 to 0 transition.
– tPLH (rise time): propagation delay from low to high.
– tPHL (fall time): propagation delay from high to low.

t PLH t PHL
(rise time) (fall time)

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• Ambiguous or Min/Max Delay

– Sometimes it is impossible to predict exact rise or fall time of a signal.
– For worst-case performance analysis, {tmin, tmax} is specified for each
timing parameter.

c
t min

t max

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• A problem with min/max delay: the results tend to be pessimistic.

circuit model worst-case delays:

ambiguity region gets larger
at each successive level
a f
b h
c
d d
e g
e
g

h
15
10 12 14 16 20 25

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• Inertial Delay
– An input value must persist for some minimum duration of time to
provide the output with the needed inertia to change.
– The minimum duration is called inertial delay.
– Effect of inertial delay:
a a

b b

c c
(a) Transport delay model (b) Inertial delay model

– Gate model with both inertial delay and transport delay:

 t a*
a
c*  t c
b  t
b*
Inertial Ideal Transport
delay gate delay
Chapter 2 100