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Computer Architecture

Computer architecture
design Refers to those attributes of the system visible to the programmer, that have a direct impact on the logical execution of the program Hardware and software

attributes
Instruction set Number of bits to represent data types I/O mechanisms Memory addressing

types
Open architecture
Allows the system to easily be connected to devices and programs made by other manufacturer

Closed architecture
Design is proprietary, make it difficult to connect the system to other system

developments
Clock speeds
70s 80s 90s 1MHz 8 20 MHz 50 100 MHz

Scalar processor
Achieve average execution of no more than one instruction per clock cycle

Superscalar processor
More instructions per clock cycle

Bus
Communication channel between the various parts of the system

parts
Data lines
Carry instruction from memory to processor during each instruction fetch cycle and data between processor and memory or I/O. Bi-directional Specify size of data being processed internally

Address lines
Carry address of memory or I/O locations to be accessed 8 bit 16 bit 32 bit 16 lines 20 lines / 24 lines 32 lines

Control lines
Carry signals to activate the data or instruction transfer within the system Indicate type of transfer
Example:
Memory Read or write I/O read or write

Architectural developments
1. Pipelined processor design pipelined consist of a number of stages with each stage performing one sequential step of the overall task.

Instruction fetch/execute overlap - execution and fetching of the next instruction can be done simultaneously. 3 steps can be overlapped: fetch decode execute

2. Processor memory interface concerned with: a. carrying information from memory to processor during fetch cycle. b. carrying data from processor to memory during execute cycle.

2a. Increase communication bandwidth - increase data line - match the speed of memory to processor

2b. Prefetch buffers - instruction and data is held in a FIFO buffer.

2c. Cache - a high-speed storage mechanism. - separate of part of the memory unified cache both instruction and data can be stored.

2d. Memory hierarchy inboard outboard offline - as one goes down,


1. Decrease cost per bit 2. Increase capacity 3. Increase access time (slower)

Instruction sets
1. Use of memory and registers - 32 registers chosen for storing integers - R0 to R31 where R0 = 0.

2. Operand size - use of size field in the instruction determine the size of operands.

00 01 10 11

8 bit 16 bit 32 bit 64 bits

3. Size of memory locations n bits allows 2n locations

4. Instructions bits 6 bits for opcode 5 bits per register in the instruction.

Classes of instruction
1. Register register format opcode Rd Rs1 Rs2 unused Example: add R4, R5, R2

2. Register constant format opcode Rd Rs1 16-bit constant Exmaple: add R5, R6, 32

3. Register memory format - operand must be loaded first to register from memory. - need to specify address of memory location LOAD memory to register STORE register to memory

Example: LD R1, 100[R4] ST R4, 200[R2}

LOAD: opcode Rd add. Reg. 16-bit offset STORE: opcode source add. Reg. 16-bit offset

LOAD:
opcode Rd add. Reg. unused 11-bit offset

STORE:
opcode unused add. Reg. source 11bit offset