Introduction to Low Power Design

M. Balakrishnan CSE Department, IIT Delhi

CSV881: Selected Topics in Hardware Design (Low Power Design)

1-credit course (14 lectures) Instructors:

Prof. M. Balakrishnan (CSE Department) Dr. Preeti Ranjan Panda (CSE Department)

Classes
Balas classes: Monday 4:00 to 5:00 PM Preetis classes: Wednesday 3:00 to 4:00 PM

Live classes at IITD and Cadence NOIDA through 2-way audio-video link

Class Schedule
S.No. 1 2 3 4 5 6 7 8 9 10 11 12 Topics Introduction to Low Power Design Low Power RTL Synthesis Power Optimisations in Processor Architectures Low Power Logic Design Low Power Logic Synthesis Power Optimisations in Processor Architectures Power Aware Program Transformations Low Power FSM Synthesis Faculty M. Balakrishnan M. Balakrishnan M. Balakrishnan Preeti Ranjan Panda Preeti Ranjan Panda M. Balakrishnan M. Balakarishnan Preeti Ranjan Panda Time 4 - 5 PM 4 - 5 PM 4 - 5 PM 3 - 4 PM 3 - 4 PM 4 -5 PM 4 - 5 PM 3 - 4 PM Dates 15-Sep 22-Sep 29-Sep 1-Oct 8-Oct 13-Oct 20-Oct 22-Oct

Power Issues in Memory Systems

Power Aware Program Transformations Power Issues in Bus Design Power Estimation & Modeling Power Issues in OS

Preeti Ranjan Panda

M. Balakarishnan Preeti Ranjan Panda M. Balakrishnan Preeti Ranjan Panda

3 - 4 PM
4 - 5 PM 3 - 4 PM 4 - 5 PM 3 - 4 PM

29-Oct
3-Nov 5-Nov 10-Nov 12-Nov

13
14

Power Issues in OS

Preeti Ranjan Panda

3 - 4 PM

19-Nov

Know Your Instructors

M. Balakrishnan

Preeti Ranjan Panda

Course Evaluation
Credit Registration
Transcribe one lecture (deadline: 2 weeks from the lecture date) 50% 1 hour test at the end of the course 50%

Audit/Professional Candidate Registration

1 hour test at the end of the course 50% (For satisfactory grade minimum 50% marks)

Motivation for Low Power Design

Low power design is important from three different reasons Device temperature
Failure rate, Cooling and packaging costs

Life of the battery

Meantime between charging, System cost

Environment
Overall energy consumption

Power Projections (2000)

Suns

10000
Power Density (W/cm2) 1000 100 10 8086 Rocket Nuclear Reactor Hot Plate 486 1990 Nozzle

Surface

8008 8085 4004 286 386 8080 1 1970 1980

P6 Pentium 2000 2010

Source: Borkar De, Intel

Power Projections (2000)

100000

10000
Power (Watts) 1000 100

transition from NMOS to CMOS

18KW 5KW 1.5KW 500W

Pentium P6 286 486 10 8086 386 8080 8008 8085 1 4004 1971 1974 1978 1985 1992 2000 2004 2008 Source: Borkar De, Intel

0.1

Low Power or Low Energy Design

Power
Direct impact on instantaneous energy consumption and temperature

Energy
Power integrated over time is energy and impact on battery shelf life and environment

E(T) = 0

P(t) dt

Power Consumption
Dynamic
Transition Short circuit

Leakage
Sub-threshold leakage Diode/Drain leakage Gate leakage
At 250nm leakage power was only 5% but it is increasing rapidly as geometries decrease

Dynamic Energy Consumption

Transition Power
Vdd

Vin CL

Vout

Energy/transition = CL * VDD2 * P01 Power = CL * VDD2 * f

Dynamic Energy Consumption

Short-circuit Power
Vdd

Vin CL

Vout

Energy/transition = tsc * VDD * Ipeak * P 0/11/0 Power = tsc * VDD * Ipeak * f

Leakage Energy
Vout OFF

Drain junction leakage Sub-threshold current

Gate leakage

Independent of switching

Dynamic vs Static Power

1E +4

Power Density (W/cm^2)

1E +2

Active Power
1E +0

Shrinking Margin
1E -2

1E -4

1E -6

SubThreshold Power

1E -8 0.01

0.1

10

Gate Length (microns)

Source: Leon Stok, DAC 42

Low Power Design Needs

Low power design techniques
Effectiveness Effect/tradeoff with other design parameters like area (cost), performance, reliability, manufacturability etc.

Power modeling and estimation

Accuracy of the models Time for estimation

Design Approaches
System design: Top down
Effective low power transformations in synthesis Fast estimation techniques for an effective exploration of a large design space

Cell library design: Bottom up

Low power circuit design techniques Accurate estimation Effective models for synthesis tools

Design Levels
System Algorithmic/Module RTL Gate Circuit Device technology

System Level Design

Same MP3 Application running on different systems consume significantly different amounts of power
System

partitioning

Busses/Memory/IO devices /interfaces Choice of components Coding

System states (sleep/snooze etc)

DVS/DFS/..

Algorithmic/sub-system Level
Choice of algorithm (operation count etc.) Word length choices Module interfaces Implementation technology
SW: Processor selection HW: ASIC/FPGA/..

Behavioral synthesis constraints and trade-off

RTL
Pipelining/retiming Module selection Multiple frequency and voltage islands Reduction in switching activity through transformations

Gate Level
Clock gating Power gating Clock tree optimization Logic level transformations to reduce switching activity

Circuit Level
Transistor sizing Power efficient circuits Cell design Multi-threshold circuits

Device Technology
Multi-oxide devices Multiple cell types on a single substrate
Logic, SRAM, Flash etc.

Support for many other low power design techniques (multiple thresholds, multiple voltages, multiple frequencies etc.)

References

Thank You