ntroduction to

CMO8 VL8
Design
Lecture 1:
Circuits & Layout
David Harris
Harvey Mudd College
Spring 2004
CMOS VLSI Design 1: Circuits & Layout SIide 2
Outline
Brief History
CMOS Gate Design
Pass Transistors
CMOS Latches & Flip-Flops
Standard Cell Layouts
Stick Diagrams
CMOS VLSI Design 1: Circuits & Layout SIide 3
Brief History
First integrated circuit
Flip-flop using two transistors
Built by Jack Kilby at Texas nstruments
2003
ntel Pentium 4 3processor ( million transistors)
2 Mbit DRM (> 0. billion transistors)
3% compound annual growth rate over 4 years
No other technology has grown so fast so long
Driven by miniaturization of transistors
Smaller is cheaper, faster, lower in power!
Revolutionary effects on society
CMOS VLSI Design 1: Circuits & Layout SIide 4
nnual 8ales
0

transistors manufactured in 2003

00 million for every human on the planet
0
0
00
0
200
2 4 0 2 4 2000 2002
Year
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)
CMOS VLSI Design 1: Circuits & Layout SIide 5
nvention of the Transistor
'acuum tubes ruled in first half of 20
th
century
Large, expensive, power-hungry, unreliable
47 first point contact transistor
John Bardeen and Walter Brattain at Bell Labs
Read Crystal Fire
by Riordan, Hoddeson
CMOS VLSI Design 1: Circuits & Layout SIide 6
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls
large currents between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
'oltage applied to insulated gate controls current
between source and drain
Low power allows very high integration
CMOS VLSI Design 1: Circuits & Layout SIide 7
70's processes usually had only nMOS transistors
nexpensive, but consume power while idle
0s-present CMOS processes for low idle power
MO8 ntegrated Circuits
ntel 0 2-bit SRM ntel 4004 4-bit 3Proc
CMOS VLSI Design 1: Circuits & Layout SIide 8
Moore's Law
Gordon Moore plotted transistor on each chip
Fit straight line on semilog scale
Transistor counts have doubled every 2 months
Year
T
r
a
n
s
i
s
t
o
r
s
4004
00
00
0
02
ntel3
ntel4
Pentium
Pentium Pro
Pentium
Pentium
Pentium 4
,000
0,000
00,000
,000,000
0,000,000
00,000,000
,000,000,000
70 7 0 0 2000
Integration LeveIs
SSI 0 gates
MSI 000 gates
LSI 0,000 gates
VLSI > 0k gates
CMOS VLSI Design 1: Circuits & Layout SIide 9
Corollaries
Many other factors grow exponentially
Ex clock frequency, processor performance
Year

0
00
,000
0,000
70 7 0 0 2000 200
4004
00
00
0
02
ntel3
ntel4
Pentium
Pentium Pro//
Pentium 4
C
l
o
c
k

S
p
e
e
d

(
M
H
z
)
CMOS VLSI Design 1: Circuits & Layout SIide 10
CMO8 Gate Design
ctivity
Sketch a 4-input CMOS NND gate
CMOS VLSI Design 1: Circuits & Layout SIide 11
CMO8 Gate Design
ctivity
Sketch a 4-input CMOS NOR gate

B
C
D
Y
CMOS VLSI Design 1: Circuits & Layout SIide 12
Complementary CMO8
Complementary CMOS logic gates
nMOS 5:ll-down network
pMOS 5:ll-:5 network
a.k.a. static CMOS
pMOS
pull-up
network
output
inputs
nMOS
pull-down
network
Pull-up OFF Pull-up ON
Pull-down OFF Z (float)
Pull-down ON 0 X (crowbar)
CMOS VLSI Design 1: Circuits & Layout SIide 13
8eries and Parallel
nMOS = ON
pMOS 0 = ON
$eries both must be ON
!arallel either can be ON
(a)
a
b
a
b
g
g2
0
0
a
b
0

a
b

0
a
b

OFF OFF OFF ON

(b)
a
b
a
b
g
g2
0
0
a
b
0

a
b

0
a
b

ON OFF OFF OFF

(c)
a
b
a
b
g g2
0 0
OFF ON ON ON
(d) ON ON ON OFF
a
b
0
a
b

a
b
0
a
b
0 0
a
b
0
a
b

a
b
0
a
b
g g2
CMOS VLSI Design 1: Circuits & Layout SIide 14
Conduction Complement
Complementary CMOS gates always produce 0 or
Ex NND gate
Series nMOS Y=0 when both inputs are
Thus Y= when either input is 0
Requires parallel pMOS
Rule of Cond:.tion Com5lements
Pull-up network is complement of pull-down
Parallel -> series, series -> parallel

B
Y
CMOS VLSI Design 1: Circuits & Layout SIide 15
Compound Gates
Com5o:nd gates can do any inverting function
Ex (AND-AND-OR-INVERT, AOI22)

B
C
D

B
C
D
B C D
B
C D
B
D
Y

B
C
D
B
D
Y
(a)
(c)
(e)
(b)
(d)
(f)
CMOS VLSI Design 1: Circuits & Layout SIide 16
ample: O3

CMOS VLSI Design 1: Circuits & Layout SIide 17
ample: O3

B
Y
C
D
D C
B

CMOS VLSI Design 1: Circuits & Layout SIide 18

8ignal 8trength
$trength of signal
How close it approximates ideal voltage source
'
DD
and GND rails are strongest and 0
nMOS pass strong 0
But degraded or weak
pMOS pass strong
But degraded or weak 0
Thus nMOS are best for pull-down network
CMOS VLSI Design 1: Circuits & Layout SIide 19
Pass Transistors
Transistors can be used as switches
g
s d
g
s d
CMOS VLSI Design 1: Circuits & Layout SIide 20
Pass Transistors
Transistors can be used as switches
g
s d
g = 0
s d
g =
s d
0 strong 0
nput Output
degraded
g
s d
g = 0
s d
g =
s d
0 degraded 0
nput Output
strong
g =
g =
g = 0
g = 0
CMOS VLSI Design 1: Circuits & Layout SIide 21
Transmission Gates
Pass transistors produce degraded outputs
%ransmission gates pass both 0 and well
CMOS VLSI Design 1: Circuits & Layout SIide 22
Transmission Gates
Pass transistors produce degraded outputs
%ransmission gates pass both 0 and well
g = 0, gb =
a b
g = , gb = 0
a b
0 strong 0
nput
Output

strong
g
gb
a
b
a b
g
gb
a b
g
gb
a b
g
gb
g = , gb = 0
g = , gb = 0
CMOS VLSI Design 1: Circuits & Layout SIide 23
Tristates
%ristate b:11er produces Z when not enabled
EN Y
0 0
0
0

Y
EN

Y
EN
EN
CMOS VLSI Design 1: Circuits & Layout SIide 24
Tristates
%ristate b:11er produces Z when not enabled
EN Y
0 0 Z
0 Z
0 0

Y
EN

Y
EN
EN
CMOS VLSI Design 1: Circuits & Layout SIide 25
onrestoring Tristate
Transmission gate acts as tristate buffer
Only two transistors
But nonrestoring
W Noise on is passed on to Y
Y
EN
EN
CMOS VLSI Design 1: Circuits & Layout SIide 26
Tristate nverter
Tristate inverter produces restored output
'iolates conduction complement rule
Because we want a Z output

Y
EN
EN
CMOS VLSI Design 1: Circuits & Layout SIide 27
Tristate nverter
Tristate inverter produces restored output
'iolates conduction complement rule
Because we want a Z output

Y
EN

Y
EN = 0
Y = 'Z'
Y
EN =
Y =

EN
CMOS VLSI Design 1: Circuits & Layout SIide 28
Multipleers
2 m:lti5lexer chooses between two inputs
S D D0 Y
0 X 0
0 X
0 X
X
0

S
D0
D
Y
CMOS VLSI Design 1: Circuits & Layout SIide 29
Multipleers
2 multiplexer chooses between two inputs
S D D0 Y
0 X 0 0
0 X
0 X 0
X
0

S
D0
D
Y
CMOS VLSI Design 1: Circuits & Layout SIide 30
Gate-Level Mu Design

How many transistors are needed?

(too many transistors) $ $
CMOS VLSI Design 1: Circuits & Layout SIide 31
Gate-Level Mu Design

How many transistors are needed? 20

(too many transistors) $ $
4
4
D
D0
S
Y
4
2
2
2
Y
2
D
D0
S
CMOS VLSI Design 1: Circuits & Layout SIide 32
Transmission Gate Mu
Nonrestoring mux uses two transmission gates
CMOS VLSI Design 1: Circuits & Layout SIide 33
Transmission Gate Mu
Nonrestoring mux uses two transmission gates
Only 4 transistors
S
S
D0
D
Y S
CMOS VLSI Design 1: Circuits & Layout SIide 34
nverting Mu
nverting multiplexer
Use compound O22
Or pair of tristate inverters
Essentially the same thing
Noninverting multiplexer adds an inverter
S
D0
D
Y
S
D0
D
Y
0

S
Y
D0
D
S
S
S
S
S
S
CMOS VLSI Design 1: Circuits & Layout SIide 35
:1 Multipleer
4 mux chooses one of 4 inputs using two selects
CMOS VLSI Design 1: Circuits & Layout SIide 36
:1 Multipleer
4 mux chooses one of 4 inputs using two selects
Two levels of 2 muxes
Or four tristates
S0
D0
D
0

Y
S
D2
D3
D0
D
D2
D3
Y
SS0 SS0 SS0 SS0
CMOS VLSI Design 1: Circuits & Layout SIide 37
D Latch
When CLK = , latch is trans5arent
D flows through to Q like a buffer
When CLK = 0, the latch is o5aq:e
Q holds its old value independent of D
a.k.a. trans5arent lat.h or level-sensitive lat.h
CLK
D Q
L
a
t
c
h
D
CLK
Q
CMOS VLSI Design 1: Circuits & Layout SIide 38
D Latch Design
Multiplexer chooses D or old Q

0
D
CLK
Q
CLK
CLK
CLK
CLK
D Q
Q
Q
CMOS VLSI Design 1: Circuits & Layout SIide 39
D Latch Operation
CLK =
D
Q
Q
CLK = 0
D
Q
Q
D
CLK
Q
CMOS VLSI Design 1: Circuits & Layout SIide 40
D Flip-flop
When CLK rises, D is copied to Q
t all other times, Q holds its value
a.k.a. 5ositive edge-triggered 1li5-1lo5, master-slave
1li5-1lo5
F
l
o
p
CLK
D Q
D
CLK
Q
CMOS VLSI Design 1: Circuits & Layout SIide 41
D Flip-flop Design
Built from master and slave D latches
QM
CLK
CLK
CLK
CLK
Q
CLK
CLK
CLK
CLK
D
L
a
t
c
h
L
a
t
c
h
D Q
QM
CLK
CLK
CMOS VLSI Design 1: Circuits & Layout SIide 42
D Flip-flop Operation
CLK =
D
CLK = 0
Q
D
QM
QM
Q
D
CLK
Q
CMOS VLSI Design 1: Circuits & Layout SIide 43
#ace Condition
Back-to-back flops can malfunction from clock skew
Second flip-flop fires late
Sees first flip-flop change and captures its result
Called hold-time 1ail:re or ra.e .ondition
CLK
D
Q
F
l
o
p
F
l
o
p
CLK2
Q2
CLK
CLK2
Q
Q2
CMOS VLSI Design 1: Circuits & Layout SIide 44
onoverlapping Clocks
Nonoverlapping clocks can prevent races
s long as nonoverlap exceeds clock skew
We will use them in this class for safe design
ndustry manages skew more carefully instead

2
2

QM
Q D
CMOS VLSI Design 1: Circuits & Layout SIide 45
Gate Layout
Layout can be very time consuming
Design gates to fit together nicely
Build a library of standard cells
Standard cell design methodology
'
DD
and GND should abut (standard height)
djacent gates should satisfy design rules
nMOS at bottom and pMOS at top
ll gates include well and substrate contacts
CMOS VLSI Design 1: Circuits & Layout SIide 46
ample: nverter
CMOS VLSI Design 1: Circuits & Layout SIide 47
ample: D3
Horizontal N-diffusion and p-diffusion strips
'ertical polysilicon gates
Metal '
DD
rail at top
Metal GND rail at bottom
32 2 by 40 2
CMOS VLSI Design 1: Circuits & Layout SIide 48
8tick Diagrams
$ti.k diagrams help plan layout quickly
Need not be to scale
Draw with color pencils or dry-erase markers
CMOS VLSI Design 1: Circuits & Layout SIide 49
iring Tracks
wiring tra.k is the space required for a wire
4 2 width, 4 2 spacing from neighbor = 2 pitch
Transistors also consume one wiring track
CMOS VLSI Design 1: Circuits & Layout SIide 50
ell spacing
Wells must surround transistors by 2
mplies 2 2 between opposite transistor flavors
Leaves room for one wire track
CMOS VLSI Design 1: Circuits & Layout SIide 51
rea stimation
Estimate area by counting wiring tracks
Multiply by to express in 2
CMOS VLSI Design 1: Circuits & Layout SIide 52
ample: O3
Sketch a stick diagram for O3 and estimate area

CMOS VLSI Design 1: Circuits & Layout SIide 53
ample: O3
Sketch a stick diagram for O3 and estimate area

CMOS VLSI Design 1: Circuits & Layout SIide 54
ample: O3
Sketch a stick diagram for O3 and estimate area