Assignment 1(1)

• Create a test cell with rank 1 using LASI. In

this cell draw a 10 by 10 box using POL1
layer. Place the lower left cornet of the box
at the origin . Show how to measure the
diagonal distance of the box.
 Procedure
• 1. Go to load menu, cell name TESTCELL.
• 2.Open layer button Select layer POL1.
• 3.Select obj ->Box->add
• 4. For diagonal dist: use z and space.
 Assignment 1(2)
• State all possible combination of commands
available to increase the size of the box
problem 1 to 20 by 30.
 Procedure
• 1. Get
• 2. Mov
 Assignment 1(3)
• Write the word “test”on the MET1 layer
with the size 3,9 & 24 in the cell of
problem1. Also comment all possible ways
to getting and moving the text.
 Procedure
• Tsiz ->select ‘text size’ 3
• Text ->click to add text where need
• Do the same procedure for text size 9 & 24.
 Assignment 1(4)
• Using a path and a poligon in the
cell(testcell) of prob 1,generate two objects
width 10 & length 10 directly next to the
box from problem 1.
 Procedure
• Cwth -> Put ‘new path width’ 10
• Obj -> Select ‘POLY/PATH’
 Assignment 1(5)
• Using POL1 layer draw a triangle that
measures normally10 on each side. Using
LASI’s measurement tool measure the
length of triangle side .
 Procedure
• Obj ->POLY/PATH ->add Draw a line of
10 lam
• Suppose height of the triangle is ‘h’ & side
is ‘s’.Then we get
h=sqart(sqare(s)+square(s/2))
=sqart(sqare(10)+square(10/2))=6.67
 Assignment 1(6)
• Draw a circle using polygon(path of 0
width) and the ‘arc’ command.
 Procedure
• Obj->POLY/PATH->add command Draw a
line.
• Arc command make circle.
 Assignment 2(1)
• Creat a cell called “testcell1” with rank 2
using LASI. In this cell draw the following
nwell and pwell.The nwell be a rank1 cell
and added to the testcell in the said manner.
 Procedure
• Obj->POLY/PATH->add command.
• Rot->Rotate 180 deg.
• Flp->command to plop the view of nwell.
 Assignment 2(2/a)
• What is the resistance of the resister1 ,frawn
using a nwell layer with asheet resistance of
2 kiloohm/square. The length of the first
resistor is 20 and the width is “w”. W=6 is
the width of the nwell. Draw the layout of
the above mentioned restor.
 Procedure
• R= Rsheet*(W/L)
=2*20/6
=6.67
• ‘Res’ command set manual
R(Ohms/sq)=2000
• ‘Confg’ command set ‘auto R’ value
‘2000 0 –800 6’
 Assignment 2(2/b)
• Find out the length required to design one
resistor similar to resistor1 with sheet
resistance 2koloohm/square and overall
resiatance value of 10 k. Design the rule
check of finished resistor.
 Procedure
• R =Rsheet*(L/W)
ie, 10=2*(L/6) =>L=30 lam.
• ‘Cwth’->Select W=6.
• Obj->POLY/PATH->add=> to make 30
lam long resistor.
• Get->res=>to measure the value of resistor.
 Assignment 2(2/c)
• Design resistor with layout similar to
resiator2 and resistance value equal to
resistor1.The width of the each segment of
resiator2 equal to W. At the corner segment
length has been assumed as L=W.
Draw the layout of the following resistor
using LASI. Design the rule check of
finished resistor.
 Procedure
• R= Rsheet*(W/L)
• For corner correction resistance value
reduced in the corner by 60%
• For eg:
30*6 resistance of Rsheet = 2k/sq.
R=2*30/6=10k
• Now I bend this in the middle
Then the calculation is
R =2*(15-3)*2+2*60%
=9.2k
• So the calculation is we have to increase
resistance by 0.8k.
ie, 0.8=2*(L/6) =>L=2.4
• So we have to increase the res. Length by
2.4 lam.
 Assignment 2(3)
• Lay out (using a path object in LASI or any
other layout program) a normally 250 kilo
ohm resistor using the n-well and serpentine
pattern shown in the figure. Assume that the
maximum length of a segment is 100 and
the sheet resistance is 2 kiloohm/square.
The width of the n-well is 6. Design the rule
check of finished resistor
 Procedure
• To make 250k we have to determine the
“L” that is =250*3+10*2.4=774 lam
• I took 97*2+95*4+40*5=774 lam
• I have written a “C” program that will
calculate this value. Only the input of the
prog is Max val=100; & End val=97;
Rest will calculate automatically.
 Assignment 3(1/a)
• Lay out two nwells as shown in the figure1
by maintaining all the design rules
coinstrains( the process technology may
vary from one to another but all the DRCs
related to the technology must be checked )
 Assignment 3(1/b)
• Lay out of the following metal layer as
shown in the figure2 and 3 by maintaining
all the design rules constrain.
 P-MOS
• P-MOS transistor with L=2 λ,W=9 λ
 Procedure
• Step1: select menu1->layr->Actv->ok(box
of 16λ*9 λ) .
• Step2:to place the gate ,select the layer->
Poll->ok.
• Step3:PSEL box with 2 λ overlap to active
box.
• Step4:layr->CONT->ok.
• Step 5: To add metal contact,Layr->Met1-
>ok.
• Step6: To add connecter text, select menu2-
>Tlyr->CTXT->ok.
• Step7:To add outline,Layr->OTLN->ok.
 N-MOS
• N-MOS with L=2 λ,W=3 λ.
 Frame cell
• To make any gates we have to make frame
shell.
• Top side
Menu1->Layr->Actv(W-4L)->ok
PSEL(2L overlap with Actv_box)->ok
Layr->CONT(2L X 2L Right-side)->ok
Layr->Met1(W-4L overlap with CONT)->ok
• Bottom Side
Menu1->Layr->Actv(W-4L)->ok
NSEL(2L overlap with Actv_box)->ok
Layr->CONT(2L X 2L Left-side)->ok
Layr->Met1(W-4L overlap with CONT)->ok
Layr->OTLN(Including Top-side & Bottom-
side)-ok
 LOGIC GATES
• Inverter
• Need one n-mos and one p-mos.
• *Start Lasi chk
• VDD 1 0 DC 5V
• VIN1 2 0 DC 0 AC 0 0 PULSE(0 5V 0 1NS
1NS 20NS 40NS)
• .OPTION RELTOL=0.1 ABSTOL=1U
VNTOL=50MV
• .PROBE
• .TRAN 1NS 150NS
• *End lasi input
 LOGIC GATES
• Nand
• Need two n-mos and two p-mos
• * Start of E:\Lasi7\Msulib\Nand_gate_header.txt
• *Start Lasi chk*
• VDD 1 0 DC 5V
• VIN1 2 0 DC 0 AC 0 0 PULSE(0 5V 0 1NS 1NS
20NS 60NS)
• VIN2 4 0 DC 0 AC 0 0 PULSE(0 5V 0 1NS 1NS
20NS 40NS)
• .OPTIONS RELTOL=0.1 ABSTOL=1U
VNTOL=50MV
• .PROBE
• .TRAN 1NS 150NS
• *End lasi input*
• * End of E:\Lasi7\Msulib\Nand_gate_header.txt
 LOGIC GATES
• And gate
• * Start of E:\Lasi7\Msulib\And_gate_header.txt
• *Start Lasi chk*
• VDD 1 0 DC 5V
• VIN1 2 0 DC 0 AC 0 0 PULSE(0 5V 0 0NS 0NS
20NS 60NS)
• VIN2 4 0 DC 0 AC 0 0 PULSE(0 5V 0 0NS 0NS
25NS 45NS)
• .OPTIONS RELTOL=0.1 ABSTOL=1U
VNTOL=50MV
• .PROBE
• .TRAN 1NS 150NS
• *End lasi input*
• * End of E:\Lasi7\Msulib\And_gate_header.txt
 LOGIC GATES
• NOR GATE
• * Start of E:\Lasi7\Msulib\Nor_gate_header.txt
• *Start Lasi chk*
• VDD 1 0 DC 5V
• VIN1 2 0 DC 0 AC 0 0 PULSE(0 5V 0 1NS 0NS
20NS 60NS)
• VIN2 4 0 DC 0 AC 0 0 PULSE(0 5V 0 1NS 0NS
25NS 45NS)
• .OPTION RELTOL=0.1 ABSTOL=1U
VNTOL=50MV
• .PROBE
• .TRAN 1NS 150NS
• *End lasi input*
• * End of E:\Lasi7\Msulib\Nor_gate_header.txt
 LOGIC GATES
• OR GATE
• * Start of E:\Lasi7\Msulib\Or_gate_header.txt
• *Start Lasi chk*
• VDD 1 0 DC 5V
• VIN1 2 0 DC 0 AC 0 0 PULSE(0 5V 0 0NS 0NS
20NS 60NS)
• VIN2 4 0 DC 0 AC 0 0 PULSE(0 5V 0 0NS 0NS
25NS 45NS)
• .OPTION RELTOL=0.1 ABSTOL=1U
VNTOL=50MV
• .PROBE
• .TRAN 1NS 150NS
• *End lasi input*
• * End of E:\Lasi7\Msulib\Or_gate_header.txt
Thank you