HIGH SPEED ADDER USED IN DSP

Technical Seminar Presentation 2004

HIGH SPEED ADDER USED IN DIGITAL SIGNAL PROCESSING

Presented by

Banasree Nag

Under the guidance of

Mr M. Suresh
Presented by Banasree Nag

EI200198051

HIGH SPEED ADDER USED IN DSP

Technical Seminar Presentation 2004

INTRODUCTION
Among the various arithmetic operation addition is the simplest operation. A combinational circuit that performs the addition of two bits known as half adder. And that performs the addition of three bits known as full adder. A full adder can be implemented from two half adders
Presented by Banasree Nag EI200198051

HIGH SPEED ADDER USED IN DSP

Technical Seminar Presentation 2004

HALF ADDER
Half adder circuit needs two binary inputs and two binary outputs X and Y to the inputs and S and C to the outputs.
U5A U2A X 1 2 74ALS35A U6A Y 1 2 74ALS35A 1 3 2 74ALS32 74ALS808A U4A 1 3 2 74ALS808A C 2 U3A 1 3 2 74ALS808A 1 3 S U1A

Presented by Banasree Nag

EI200198051

HIGH SPEED ADDER USED IN DSP

Technical Seminar Presentation 2004

FULL ADDER
U1A

U5A X Y 1 3 2 7408 U6A 1 3 Z 2 74ALS1032A 7408 U7A 1 3 2 7408 74ALS1032A 1 3 C 2 2 U10A 1 3

U4A X 1 2 1 2 13 12 1 U2A 74ALS11A U4A Y 1 2 1 2 13 12 2 74ALS11A U6A Z 1 2 1 2 13 U7A 12 74ALS11A U4A 1 2 13 12 74ALS11A 74ALS32 1 3 2 74ALS32 2 74ALS32 1 3 S 3 U8A U5A

U10A

U3A

Carry of full adder

Presented by Banasree Nag

Sum of full adder

EI200198051

HIGH SPEED ADDER USED IN DSP

Technical Seminar Presentation 2004

This simple adder has some draw back. It is slow and it will not produce the correct result unless the signals are given enough time to propagate through the gates connected from the inputs to the outputs. The solution for reducing the delay of the circuit is to employ faster gates with reduced delays.
Presented by Banasree Nag EI200198051

HIGH SPEED ADDER USED IN DSP

Technical Seminar Presentation 2004

There is some other adder, which takes minimum time to perform the addition operation. These areRipple Adder, Carry Look Ahead Adder, Carry Select Adder, 2s Complement Adder,

Conditional Sum Adder,

Carry Save Adder.
Presented by Banasree Nag EI200198051

HIGH SPEED ADDER USED IN DSP

Technical Seminar Presentation 2004

RIPPLE CARRY ADDER

In a ripple-carry adder the result of an addition of two bits depends on the carry generated by the addition of the previous two bits. Thus, the Sum of the most significant bit is only available after the carry signal has rippled through the adder from the least significant stage to the most significant stage.

Presented by Banasree Nag

EI200198051

HIGH SPEED ADDER USED IN DSP

Technical Seminar Presentation 2004

DELAY IN RIPPLE CARRY ADDER

In the ripple carry adder, the addition of (1+1 = 102) in the least significant stage causes a carry bit to be generated. This carry bit will consequently generate another carry bit in the next stage, and so on, until the final carryout bit appears at the output. As a result, the final Sum and Carry bits will be valid after a considerable delay

Presented by Banasree Nag

EI200198051

HIGH SPEED ADDER USED IN DSP

Technical Seminar Presentation 2004

CONTINUED..

The disadvantage of the ripple-carry adder is that it can get very slow when one needs to add many bits. For instance, for a 32-bit adder, the delay would be about 66 ns if one assumes a gate delay of 1 ns.
Presented by Banasree Nag EI200198051

HIGH SPEED ADDER USED IN DSP

Technical Seminar Presentation 2004

CARRY LOOK AHEAD ADDERS

For first addition operation the most widely used is the principle of look-ahead carry.

Adder design with this consideration in mind are called high speed adder.

Presented by Banasree Nag

EI200198051

HIGH SPEED ADDER USED IN DSP

Technical Seminar Presentation 2004

Presented by Banasree Nag

EI200198051

HIGH SPEED ADDER USED IN DSP

Technical Seminar Presentation 2004

DELAY IN CARRY LOOK AHEAD ADDER

Presented by Banasree Nag

EI200198051

HIGH SPEED ADDER USED IN DSP

Technical Seminar Presentation 2004

DISCUSSION
The implementation of six adder structures is presented.

Presented by Banasree Nag

EI200198051

HIGH SPEED ADDER USED IN DSP

Technical Seminar Presentation 2004

ACTIVE CAPACITANCE

Presented by Banasree Nag

EI200198051

HIGH SPEED ADDER USED IN DSP

Technical Seminar Presentation 2004

MAXIMUM OPERATION FREQUENCY

Presented by Banasree Nag

EI200198051

HIGH SPEED ADDER USED IN DSP

Technical Seminar Presentation 2004

10. CONCLUSION
Most of the adder structures discussed in this paper are applicable to general-purpose designs, with a few exceptions.

This paper has presented a comprehensive comparison of the six most commonly used adder structures.

Presented by Banasree Nag

EI200198051

HIGH SPEED ADDER USED IN DSP

Technical Seminar Presentation 2004

continued..

A detailed analysis of the area requirement, the maximum operational speed and the power consumption has provided a convenient way to compare the advantages and trade-offs of each design. Thus, the adder best suited to any given design may be easily selected using the data presented. THANK YOU

Presented by Banasree Nag

EI200198051