Project Participants: PROJECT GUIDE

Manoj.

A DIGITAL MODULATION UNIT

AIM OF PROJECT
This project is dedicated to design a chip which is

capable to provide various methods of source encoding, channel encoding and modulation. Here user will be free to select different arrangement according to requirement.

Digital MODULATION Unit

SALIENT FEATURES
DMU is a software tool that speeds up and makes easy the

implementation of communications systems. The tool allows the software defined radio designers to develop digital base-band or intermediate frequency modems and finally to generate automatically the VHDL code to implement the system on Xilinx FPGAs. This project will be based on front end VLSI technology using Hardware description Language VHDL.

The FPGA revolution has truly taken hold in the world of high-performance and real-time embedded applications.
This model DMU" is a general model which can be applicable in many systems such as military, medical, industries ,laboratories and satellite systems for digital modulation. It is a good model for data acquisition in the high speed systems.

Tools
Xilinx Project Navigator 6.1iTo make the coding of VHDL, check syntax , view RTL schematic and view pin diagram.

Modelsim 6.4cTo see waveform of the project before making a chip.

Block diagram of Digital Communication System

VHDL IMPLEMENTATION DESIGN OF 4:1 MULTIPLEXER

SELECTION LINE PROCESS

00 01 10 11

ASK FSK PSK DECIMAL TO BINARY

REGISTER TRANSFER LEVEL VIEW OF DMU

Modules Prepared
SOURCE ENCODER DECIMAL TO BINARY CONVERSION Eg. 1=0001 2=0010 3=0011

WE PREPARE THIS USING LOOK UP TABLE

WAVEFORM OF DECIMAL TO BINARY CONVERSION

LOGIC FOR AMI CODE

INPUT MESSAGE SIGNAL IS 1 BIT
OUTPUT IS ALTERNATE 1 AND 0 FOR

CONSECUTIVE 1 OR ZERO i.e. 1 =CLOCK WITH RISING EDGE NEXT 1=CLOCK WITH NEGATIVE EDGE

CHANNEL ENCODER (AMI )

MODULATION SCHEME
AMPLITUDE SHIFT KEYING

FREQUENCY SHIFT KEYIG

PHASE SHIFT KEYING

LOGIC FOR ASK IMPLEMENTATION

CARRIER WAVE =CLOCK
MESSAGE SIGNAL=8 BIT SIGNAL IF BIT IS 1 THEN OUTPUT IS CARRIER WAVE AND

IF BIT IS 0 THEN OUTPUT IS ZERO

WAVEFORM OF ASK MODULE

LOGIC FOR FSK IMPLEMENTATION

CARRIRE WAVE IS CLOCK
MESSAGE SIGNAL=8 BIT IF MESSAGE IS 1 BIT THEN OUTPUT IS CLOCK

WITH F1 FREQUENCY AND IF MESSAGE IS 0 BIT THEN CLOCK WITH F2 FREQUENCY

WAVEFORM OF FSK MODULE

LOGIC FOR PSK IMPLEMENTATION

CARRIRE WAVE IS CLOCK
MESSAGE SIGNAL IS 8 BIT IF MESSAGE HAS BIT1 THEN OUTPUT IS 0 i.e.

NO PHASE SHIFT ELSE 1 FOR PHASE SHIFT

WAVEFORM OF PSK

HDL SYNTHESIS REPORT

MACRO STATISTICS

Total memory usage is 61636 kilobytes REGISTERS 3 BIT =24

2-BIT =8 1-BIT =64

 COUNTERS
2 BIT UP COUNTER=24 4 BIT UP COUNTER=08

 MULTIPLEXERS
2 TO 1 MUX=40 8 TO 4 MUX=01

ADDERS/ SUBSTRACTERS 2BIT ADDER=08 3 BIT ADDER=16

 COMPARATORS
2 BIT COMPARATOR LESSEQUAL=32 2 BIT COMPARATOR GREATER

=16

4 BIT COMPARATOR LESSEQUAL=08

INPUT/OUTPUT PINS =20

PIN DIAGRAM OF MODULATION UNIT

ADVANTAGES
N number of ICs can be

replaced by a single IC made Easy to use. Cheap. It can be widely used for academic demonstration.

SYSTEM

ON
CHIP

Reference
VHDL -Primer Bhaskar
Communication System-Simon Haykin Circuit design with VHDL-Pedroni The VHDL Cookbook-Peter J.Ashender VHDL AMS-Handbook provided by Xilinx

!! Thank you !!