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Introduction 8051 Interrupt organization Processing Interrupts Program Design Using Interrupts Interrupt Timings

An interrupt is the occurrence of a condition--an event -- that cause a temporary suspension of a program while the event is serviced by another program (Interrupt Service Routine ISR or Interrupt Handler). Interrupt-Driven System-- gives the illusion of doing many things simultaneously, quick response to events, suitable for real-time control application.

Program

Interrupt

Program

Interrupt

Program Interrupt Service Routine

Program

time t

fahr= (cent *

9 ) +32 5

Interrupt

Program
mov R1, cent mul R1, 9 div R1, 5 add R1, 32 mov fahr, R1

time t

Interrupt

Program
mov R1, cent

Program
mul R1, 9

Interrupt Service Routine

mov R1, 0x90 mov sensor, R1 ret

time t

Interrupt

Program
mov R1, cent

Program Save Context Interrupt Service Routine Restore Context

mul R1, 9

time t

Interrupt

Program
mov R1, cent

Program Save Context

eg push R1

Interrupt Service Routine

Restore Context
eg pop R1

mul R1, 9

time t

Interrupt arrives Complete current instruction Save essential register information Vector to ISR Save additional register information Execute body of ISR
Restore other register information Return from interrupt and restore essential registers

Interrupt Latency

Interrupt Termination

Resume task

UBC 104 Embedded Systems

11

Interrupt Latency

Interrupt Response Time= Interrupt Latency + Time in Interrupt Routine

UBC 104 Embedded Systems

12

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5 interrupt sources: 2 external, 2 timer, a serial port 2 programmable interrupt priority levels fixed interrupt polling sequence can be enabled or disabled IE (A8H), IP (B8H) for controlling interrupts

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Bit IE.7 IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0

Symbol Bit Address EA AFH AEH ET2 ADH ES ACH ET1 ABH EX1 AAH ET0 A9H EX0 A8H

Description (1=enable, 0=disable) Global enable/disable Undefined Enable timer 2 interrupt (8052) Enable serial port interrupt Enable timer 1 interrupt Enable external 1 interrupt Enable timer 0 interrupt Enable external 0 interrupt

Two bits must be set to enable any interrupt: the individual enable bit and global enable bit SETB ET1 SETB EA MOV IE,#10001000B

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Bit IP.7 IP.6 IP.5 IP.4 IP.3 IP.2 IP.1 IP.0

Symbol Bit Address PT2 BDH PS BCH PT1 BBH PX1 BAH PT0 B9H PX0 B8H

Description (1=high, 0=low priority) Undefined Undefined Priority for timer 2 interrupt (8052) Priority for serial port interrupt Priority for timer 1 interrupt Priority for external 1 interrupt Priority for timer 0 interrupt Priority for external 0 interrupt

0= lower priority, 1= higher priority, reset IP=00H Lower priority ISR can be interrupted by a high priority interrupt. A high priority ISR can not be interrupted.

Interrupt Flag SFR Register & Bit Position -----------------------------------------------------------------------------External 0 IE0 TCON.1 External 1 IE1 TCON.3 Timer 1 TF1 TCON.7 Timer 0 TF0 TCON.5 Serial port TI SCON.1 Serial Port RI SCON.0 Timer 2 TF2 T2CON.7 (8052) Timer 2 EXF2 T2CON.6 (8052)
The state of all interrupt sources is available through the respective flag bits in the SFRs. If any interrupt is disabled, an interrupt does not occur, but software can still test the interrupt flag.

If two interrupts of the same priority occur simultaneously, a fixed polling sequence determines which is serviced first. The polling sequence is External 0 > Timer 0 >
External 1 > Timer 1 > Serial Port > Timer 2

Level- or edge-triggered

Level-triggered threshold
trigger point
t

Edge-triggered

I/O event handling:

Polling: main program keeps checking the flag, waiting for the occurrence of the event. Inefficients. Interrupt-driven: CPU can handle other things without wasting time waiting for the event. Efficient, prompt if ISR is not so complex. Suitable for control application. I/O processor: dedicated processor to handle most of the I/O job without CPU intervention. Best but most expensive

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Interrupt vector = the address of the start of the ISR. When vectoring to an interrupt, the flag causing the interrupt is automatically cleared by hardware. The exception is RI/TI and TF2/EXF2 which should be determined and cleared by software.
Flag RST IE0 TF0 IE1 TF1 RI or TI TF2 or EXF2 Vector Address 0000H (LJMP 0030H) 0003H 000BH 0013H 001BH 0023H 002BH

Interrupt System Reset External 0 Timer 0 External 1 Timer 1 Serial Port Timer 2

Interrupt INT0 TF0 INT1 TF1 RI/TI TF2

Original 0003H 000BH 0013H 001BH 0023H 002BH

Revectored FFDFH FFE3H FFE7H FFEBH FFF1H FFF5H

MAIN: T0ISR:

ORG LJMP ORG LJMP ORG . . . . RETI

0000H MAIN 000BH T0ISR 0030H

; T0 ISR entry point ;above int vectors

; Timer 0 ISR ;return to main

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MOV PUSH PUSH MOV POP MOVX INC POP MOVX SJMP RETI DPTR,#T2_ISR DPL DPH DPTR,#0FFF5H A @DPTR,A DPTR A @DPTR,A BACK

BACK: T2_ISR:

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