These slides incorporate figures from Digital Design Principles and Practices, third edition, by John F.

Wakerly, Copyright 2000, and are used by permission. NO permission is given to re-use or publish these figures, in either original or modified form, in printed, electronic or any other format.

Slide Set 3 Gates and transistors

Goal: to construct a logic family of gates Families: CMOS (through section 3.8), MOS, TTL, ECL Subfamilies: speed, power, hysteresis (next slide)

Hysteresis

CMOS Inverter:

NAND:

NOR:

NAND vs. NOR

For a given silicon area, PMOS transistors are weaker than NMOS transistors.
NAND NOR

Result: NAND gates are preferred in CMOS.

 CMOS NAND -- more inputs (3)

Fan-in: limited by series transistors nominal: max fan-in = 4 for NOR, 6 for NAND Fan-out: limited by output current (later)

Circumventing fan-in restriction 3-level substitute can be faster than direct 8-input NAND

Analysis (1 to 0 transition): suppose I1 = 0 while I2 = I3 = ... = I8 = 1 NOR inputs are 1 (upper) and 0 (lower), inverter input is 0, OUT is 1 I1 -> 1 Left: upper NAND output discharges through 4 series n-channels, say time t NOR output charges through 2 series p-channels requires time t/2 assuming p-channels are size-compensated inverter output discharges through 1 n-channel, say time t/4 Total time is 7t/4 = 1.75 t Right: NAND output discharges through 8 n-channels Total time is 2t Left structure is slightly faster Speed disparity increases with larger fan-in

 Inherent inversion. Non-inverting buffer:

 2-input AND gate:

CMOS AND-OR-INVERT (AOI) gate

(16 transistors)

Z = 1 iff AB = CD = 0

(8 transistors)

CMOS AND-OR-INVERT (AOI) gate

Z = 1 iff AB = CD = 0
AB = 0 gets power to here

CD = 0 then gets power to here

AB = 0 blocks this path to ground

(8 transistors)

CD = 0 blocks the alternative path to ground

CMOS OR-AND-INVERT (OAI)

(16 transistors)

Z = 0 iff A + B = C + D = 1
(8 transistors)

CMOS OR-AND-INVERT (OAI) Z = 0 iff A + B = C + D = 1

A + B = 1 blocks alternative path to power rail

C + D = 1 blocks this path to power rail

C + D = 1 then gets ground to here A + B = 1 gets ground to here

(8 transistors)

CMOS Electrical Characteristics

Digital analysis works only if circuits are operated in spec:
Power supply voltage Temperature Input-signal quality Output loading

Must do some analog analysis to prove that circuits are operated in spec.
Fanout specs Timing analysis (setup and hold times) Analysis involves only consequences of V = IR (static) and q = CV (dynamic)

input-output voltage curve for CMOS inverter

Manufacturer's data sheet for 74HC00 or 54HC00 (military version) quad NAND gate

high-level noise margin

low-level noise margin

High output current situations (e.g. driving LED or non-CMOS input)

Low output current situations (e.g. driving other CMOS gates)

For high current context, need to analyze resistive load

DC Loading
An output must sink current from a load when the output is in the LOW state. An output must source current to a load when the output is in the HIGH state.

DC Loading
An output must sink current from a load when the output is in the LOW state. An output must source current to a load when the output is in the HIGH state.

Output-voltage drops
Resistance of off transistor is > 1 Megohm, but resistance of on transistor is nonzero,
Voltage drops across on transistor, V = IR

For CMOS loads, current and voltage drop are negligible. For TTL inputs, LEDs, terminations, or other resistive loads, current and voltage drop are significant and must be calculated.

To compute currents, sum voltage drops around loops

65  5i1  10i1  20i1  20i2  70 ! 0 70  20i2  20i1  15i2  10i2 ! 0 35 20 20 i1 5 i ! 70 45 2 20 ! 1175 45
10 15

i1
+ -

20

i2

10

35 D! 20 1 i1 ! D

65

5 20 70 !1 45 5 1 35 i2 ! 20 70 ! 2 D

70

10

15

i1

20

i2

R = 10

65

70

35  20

 20 i1  5 i ! 70 45 2  20 35 D! ! 1175 45  20 35  20  5 !2 70

R  35 aR  b

1 i2 ! D

( aR  b)

c i! aR  b iSC Vout VOC Req i! i! c ! b cR ! Ri ! aR  b c ! Veq ! a VOC b ! ! iSC a c c/a ! aR  b R  (b / a ) Veq R  Req Veq

Thevenins Theorem
Req
R

Example loading calculation

5 2 Veq ! Voc ! (2000) ! (5) ! 3.33 volts 1000  2000 3 5 I sc ! ! 0.005 amps 1000 V 3.33 Req ! oc ! ! 667 ohms I sc 0.005

5v

Thevenin equivalent = ?

Example loading calculation

5 2 Veq ! Voc ! (2000) ! (5) ! 3.33 volts 1000  2000 3 5 I sc ! ! 0.005 amps 1000 V 3.33 Req ! oc ! ! 667 ohms I sc 0.005

5v

Thevenin equivalent

For low input: output is high pull-up (p-channel) conducts, say 200 ohms pull-down (n-channel) blocks, say open circuit

iout !

5.0  3.33 ! 0.00193 200  667

Claim: output falls to 4.61 Why?

Vout ! 5.0  200(0.00193) ! 4.61

For high input: output is low pull-up (p-channel) blocks, say open circuit pull-down (n-channel) conducts, say 100 ohms

iout !

3.33 ! 0.00434 100  667

Claim: output rises to 0.43 Why?

Vout ! 100(0.00434) ! 0.434

Limitation on DC load
If too much load, output voltage will go outside of valid logic-voltage range.

VOHmin, VIHmin VOLmax, VILmax

Output-drive specs
VOLmax and VOHmin are specified for certain output-current values, IOLmax and IOHmax.
No need to know details about the device pull-up and pulldown resistances, only the load.

can source 4 ma with output at 3.84 volts

can sink 4 ma with output at 0.33 volts

For low input: output is high pull-up (p-channel) conducts, low unknown resistance pull-down (n-channel) blocks, open circuit
unknown

Will output remain above 3.84 spec? If output is 3.84 => current is (3.84-3.33)/667 = 0.00076 = 0.76 ma current is less than < 4 ma spec Conclude: ok, output will rise remain than minimum 3.84

Estimate on resistances (for strong inputs): p-channel: (4.5 - 3.84)/0.004 = 165 n-channel: 0.33/0.004 = 82.5

Power - 10%
(conservative, true R likely higher, current lower)

Strong input
(165) I = (5 - 3.33)/(165 + 667) = .002 V = 5 - 165(0.002) = 4.67 (165) (4.67) (1M) (1 M)

Weak input
(300)

i1

(300)

(2.5K) (2.5K)

i2

Strong input
(165) I = (5 - 3.33)/(165 + 667) = .002 V = 5 - 165(0.002) = 4.67 (165) (4.67) (1M) (1 M)

Weak input (pull-up conducting poorly pull-down not completely blocked

(300)

i1

(300)

(2.5K) (2.5K)

i2

Strong input
(165) I = (5 - 3.33)/(165 + 667) = .002 V = 5 - 165(0.002) = 4.67 (165) (4.67) (1M) (1 M)

Weak input

(300)

i1

(300)

(2.5K) (2.5K)

i2

5.0  300i1  2500(i1  i2 ) ! 0 3.33  667i2  2500(i1  i2 ) ! 0

i1 ! 0.0029 i2 ! 0.0012

VOUT ! 5  300(0.0029) ! 3  667( 0.0012) ! 4.13

Claim: output falls to 4.13 Why?

Weak input

(300)

i1

(300) (4.13)

(2.5K) (2.5K)

i2

Full analysis considers (small) load associated with driving other gates:

Each gate input requires a certain amount of current to drive it in the LOW state and in the HIGH state.
IIL and IIH (normally very small for CMOS) These amounts are specified by the manufacturer.

Fanout calculation
(LOW state) The sum of the IIL values of the driven inputs may not exceed IOLmax of the driving output. (HIGH state) The sum of the IIH values of the driven inputs may not exceed IOHmax of the driving output. Need to do Thevenin-equivalent calculation for non-gate loads (LEDs, termination resistors, etc.)

Fanout (DC): low output: 0.000020/0.000001 = 20

Fanout (DC): high output: 0.000020/0.000001 = 20

AC Loading
AC loading has become a critical design factor as industry has moved to pure CMOS systems.
CMOS inputs have very high impedance, DC loading is frequently negligible (low fanouts). CMOS inputs and related packaging and wiring have significant capacitance. Time to charge and discharge capacitance is a major component of delay.

Transition times

Circuit for transition-time analysis

Assume zero voltage, infinite resistance for CMOS loads

Main determinants: on resistance and stray capacitance

HIGH-to-LOW transition

q(t ) ! CV (t )
dq dV i! ! C dt dt dV V ! iR !  RC dt dV 1  V ! 0 dt RC

V (t ) ! Ke

 t / RC

V (0) ! 5.0 !!" K ! 5 V (t ) ! 5.0e  t / RC

Exponential fall time

V ( t ) ! 5 .0 e

 t / RC

V ! 5.0e

 t / RC  t1 /(100*100*1012 )

3.5 ! 5.0e

1.5 ! 5.0e 8 t1 ! (10 )ln(3.5 / 5.0) ! 3.57 nanoseconds t2 ! 12.04 nanoseconds t2  t1 ! 8.47 nanoseconds
Note: RC ! 100(100)(10
12

 t2 /(100*100*1012 )

) ! 10 ! 10 nanoseconds

8

LOW-to-HIGH transition

q(t ) ! CV (t ) dq dV i! !C dt dt dV V ! 5.0  iR ! 5.0  RC dt dV 1  (V  5.0) ! 0 dt RC

d(V  5.0) 1  (V  5.0) ! 0 dt RC

V (t )  5.0 ! Ke  t / RC V (0) ! 0.0 !!" K ! 5.0 V (t ) ! 5.0(1  e  t / RC )

Exponential rise time

V (t ) ! 5.0(1  e  t / RC )

V ! 5.0(1  e

 t / RC

) ) )

1.5 ! 5.0(1  e

 t1 /(200*100*1012 )

3.5 ! 5.0(1  e

 t2 /(200*100*1012 )

t1 ! 7.13 nanoseconds t2 ! 24.08 nanoseconds t2  t1 ! 16.95 nanoseconds

Note: RC ! 200(100)(10
12

) ! 2(10 ) ! 20 nanoseconds

8

Other timing parameters Propagation delay...across one or many gates

assuming zero rise and fall times

measuring from transition midpoints

Timing parameters sometimes measured from logic levels

e.g.

gives minimum pulse width for a latch (measured from rising high crossing to falling high crossing)

Transition-time considerations
Higher capacitance ==> more delay Higher on-resistance ==> more delay Lower on-resistance requires bigger transistors Slower transition times ==> more power dissipation (output stage partially shorted) Faster transition times ==> worse transmission-line effects (Chapter 11) Higher capacitance ==> more power dissipation (CV2f power), regardless of rise and fall time

CMOS structures beyond logic gates:

Transmission gate

Suppose want to pass a zero from A to B, which is now one p-channel source is B (the more positive) Start transmission by placing zero on EN_L Gate is far below source, charge flows from B to A Voltage at B drops; gate is no longer so far below source (B) charge flow decreases When B gets to a certain threshold (about 0.5 volt) charge flow ceases Result: a weak zero on B Suppose want to pass a one from A to B, which is now zero p-channel source is A (the more positive) Start transmission by placing zero on EN_L Gate is far below source, charge flows from A to B Voltage at B rises; gate remains far below source (A); charge flow remains strong Voltage at B rises to full value at A Result: a strong one at B

Similar analysis for n-channel:

Suppose want to pass a zero from A to B, which is now one p-channel source is A (the less positive) Start transmission by placing one on EN Gate is far above source, charge flows from B to A Voltage at B drops; gate remains far above source (A); charge flow remains strong Voltage at B falls to value at A (nominally zero) Result: a strong zero at B Suppose want to pass a one from A to B, which is now zero p-channel source is B (the less positive) Start transmission by placing one on EN Gate is far above source, charge flows from A to B Voltage at B rises; gate not so far above source (B); charge flow drops off When B gets within a certain threshold of the gate, say 4.5 volts, the charge flow ceases Result: a weak one at B

CMOS structures beyond logic gates:

Multiplexer S=0: Z = X S=1: Z = Y

Schmitt trigger hysteresis

without hystersis:

with hystersis:

Tri-state outputs allows multiple bus drivers

When EN = 1, NAND and NOR both act like inverters ==> A appears on output When EN = 0, NAND output is 1 regardless of A NOR output is 0 regardless of A ==> both output transistors are off ==> output is isolated from both ground and power rail

Open-drain outputs
No PMOS transistor path... use resistor pull-up

Using open-drain devices to drive a common bus only one Enable-x signal is high at any given time

Problem: Want small R for fast rise time Want large R to permit an n-channel to establish a zero Compromise of size of R?

Open-drain transition times

Estimate: (assuming RC as time constant) Assume data sheet similar to normal NAND (74x00) logical zero threshold = 0.33 volt max sinking current 4 ma ==> pull-down "on" resistance is about 0.33/0.004 = 82.5 pull-up resistance must be such that 5[82.5/(82.5 + R)]<0.33 ==> R >1168 pull-up resistance is 1168/82.5 = 14 times the pull-down resistance RC for pull-up is 14 times RC for pull-down

3.84

0.33

Driving LEDs with open drains:

from LED specs

1.6 v

open drain device specs device must sink 10 ma

R=? R = [5.0 - (0.37 + 1.6)]/0.01 = 303 ohms

Driving LEDs with conventional gates:

A and B high ==> on

A or B low ==> on

Driving LEDs with conventional gates:

A and B high ==> on

A or B low ==> on

Wired-AND: Z = 1 iff (AB = 0) and (CD = 0) and (EF = 0)

want 0.4 or less in low state

100 ohm n-channel with one n-channel on: with all three n-channels on:

100(5 /( R  100)) 0.4 R " 1150

33.3(5 /( R  33.3)) 0.4 R " 383

Current-drawing load adds complications

To maintain valid low:

(worst case --- one NAND pulls low)

R " (5.0  0.4) / 0.0032 ! 1437

Compare no-load calculation:

R " (5.0  0.4) / 0.004 ! 1150

High state...still have leakage currents and load puts upper limit on R all NANDs abandon pull-down, but draw 4 x 5 = 20 micro-amps leakage load draws 20 + 20 = 40 micro-amps with high inputs total of 60 micro-amps

R (5.0  2.4) / 0.00006 ! 43333

Avoid this configuration