Digital ASIC Design Flows for WG73/58

RSSI and DCOC digital Ping Chen RFPBU Design Offsite June, 2011

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Benefits of Digital Circuits

 Area/Power/Speed scaling with

technology and fast process migration  More reliable and less sensitive to PVT  FPGA validation before expensive tapeout  Analog impairment correction by digital algorithms/calibrations  Fast design cycle: e.g. 30 working days for dcoc/rssi type of design from rtl design to gds
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Digital ASIC Frontend Flow

Specification Simulation Cases/Bench RTL Coding Formal Verification Static Timing Analysis
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Digital ASIC Backend Flow

Place & Rout LVS & DRC Formal Verification & Static Timing ATPG and DFT simulation
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Specification Format

 Waveforms

 Text Description of Functions  State Transition Diagram/Table

Simulation Test-bench
Randomized Stimulus Gen.

DUT

Assertion based checker

 Test case definitions based on spec.  Simulation stimulus (random)  Checkers (automation)  Fail/Pass assertion to guarantee no
wrong behavior  Language: Verilog or SystemVerilog
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RTL Design

 Benefit: verilog code is the format of

digital reusable IP  HW implementation, not SW algorithm  RTL coding rules and synchronous design  Simulation with Cadence nc-verilog
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Synthesis
 Benefit: Make process migration fast and easy  Input: RTL code and .lib library  Output: verilog gate netlist, .sdc for Static     

Timing Analysis Tools: Synopsys DC or Candece RC Setup time: clock period > path delay + setup time clock skew + 2 x clock jitter Hold time: clock skew > path delay 2 x jitter Scan chain insertion and DFT rules Synopsys DFT Compiler or Mentor Graphics DFT Advisor
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Formal Verification

 Benefit: Guarantee the logic equivalent

to save functional gate simulation time and fast run time  Input: verilog standard cell library  Input: verilog source code  Input: verilog gate netlist  Output: pass / fail information  Tools: Cadence Conformal
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Static Timing Analysis

 Benefit: Guarantee the correct timing to

save gate simulation and fast run time  Input: verilog netlist and library  Input: .sdc constrain file from DC/RC  Output: timing reports  Tools: Synopsys PrimeTime/Cadence ets  Pre-layout and post-layout sign off  Generate .sdf for gate simulation
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Encounter P & R
       
Benefit: fast Input: verilog gate netlist Input: .lef technology and standard cell files Input: .sdc constrain for timing driven placement Output: .gds, gate netlist for Formal Verification Floor-planning: aspect ratio or rectilinear, input/output pin locations, Placement: pre-placement opt., in-place optimization opt., scan chain re-ordering CTS and routing

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Back to Virtuoso

 Stream-in gds for layout view  Import gate verilog for schematic view  DRC/LVS clean up by mask engineer  Generating .spef for final PT sign-off run  PT generating final .sdf for DFT
simulation

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Automatic Test Pattern Generation (ATPG)

 Benefit: high test coverage e.g. >95% for

Stuck-At faults  Input: .v gate netlist and .atpg library  Input: procedure scripts  Output: test bench and vectors  Tools: Mentor Graphics FastScan or Synopsys Tetramax  nc-verilog simulation with sdf backannotation for scan chain verification and .vcd dump
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Summary

 Digital ASIC Design Tasks

Specification Format Simulation cases and automatic testbench RTL coding Synthesize with scan chain insertion Static Timing Analysis and Formal Verification sign off Place & Route (P&R) Automatic Test Pattern Generation (ATPG)

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Acknowledgements

 Special thanks to
Joel King Ari Vauhkonen William Yan Alexei Shatalov James Marsh Faye Jun Ricardo Badua Julian Lin
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Questions and Answers

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