ENG241 Comb Logic Design PartB Week4

ENG241 Digital Design
Week #4 Combinational Logic Design Part B
Resources
Chapter #4, Mano Sections

4.1 4.3 4.4 4.5 4.6
Combinational Circuits Decoding Encoding Multiplexers Comb Function Implementations
Fall 2010
ENG241/Digital Design
Week #4 Topics
Decoders
Combinational circuit Implementation Priority Encoders Combinational Circuit Implementation
Encoders
Multiplexers
Demultiplexers
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Decoders
Typically n inputs and 2n outputs Drives high the output corresponding to binary code of input
Example: Binary to Octal, Binary to Hex, e.t.c
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2-to-4 Line Decoder
Notice they are minterms

Fall 2010 ENG241/Digital Design 5
Truth Table, 3-to-8 Decoder
Notice they are minterms

ENG241/Digital Design 6
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3-to-8 Line Decoder Schematic
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2-to-4 with Enable
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Enable Used for Expansion
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VHDL Design Styles

VHDL Design Styles
dataflow
Concurrent statements
structural
Components and interconnects
behavioral (algorithmic)
Sequential statements Registers State machines Test benches
Subset most suitable for synthesis

Decoder: Data Flow

Example: 2-to-4 decoder
entity dec_2_to_4 is port ( A0, A1: in std_logic; D0, D1, D2, D3: out std_logic); end entity decoder_2_to_4;
Interface
D3 A(1) D2 D1
A(0)
D0
architecture dataflow1 of dec_2_to_4 is Signal A0_n, A1_n: std_logic; begin A0_n <= not A0; A1_n <= not A1; D0 <= A0_n and A1_n; D1 <= A0 and A1_n; D2 <= A0_n and A1; D3 <= A0 and A1; end architecture dataflow1;
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Functionality
A0_n
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When Else Statement
zmux: z <= d0 when sel1 = 0 and sel0 = 0 else d1 when sel1 = 0 and sel0 = 1 else d2 when sel1 = 1 and sel0 = 0 else d3;
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Decoder: Data Flow #2

Example: 2-to-4 decoder
entity dec_2_to_4 is port ( A : in std_logic_vector(1 downto 0); D : out std_logic_vector(3 downto 0) ); end entity dec_2_to_4;
Interface
D(3) A(1) D(2) D(1)
A(0)
D(0)
Functionality
architecture dataflow2 of dec_2_to_4 is begin D <= "0001" when A = "00" else "0010" when A = "01" else "0100" when A = "10" else "1000" when A = "11" else "XXXX"; end architecture dataflow2;
A(1..0) 0 0 1 1 0 1 0 1 0 0 0 1
D(3..0) 0 0 1 0 0 1 0 0 1 0 0 0
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Structural VHDL Description of 2-to-4 Line Decoder
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Structural VHDL Description (Entity Declaration)

-- 2-to-4 Line Decoder; structural VHDL Description library ieee; use ieee.std_logic_1164.all entity decoder_2_4_w_enable is port (EN, A0, A1 : in std_logic; D0, D1, D2, D3 : out std_logic); end decoder_2_to_4_w_enable;
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Structural VHDL Description (Signals)

A1_n A0_n N0 N1 N2
N3
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Structural VHDL Description (Components)

architecture structural1_1 of decoder_2_to_4_w_enable is component NOT1 port(in1: in std_logic; out1: out std_logic); end component; component AND2 port(in1, in2: in std_logic; out1: out std_logic); end component;
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Structural VHDL Description (Connecting components)

architecture structural1_1 of decoder_2_to_4_w_enable is -- component NOT1 declaration -- component NAND2 signal A0_n, A1_n, N0, N1, N2, N3: std_logic; begin g0: NOT1 port map (in1 => A0, out1 => A0_n); g1: NOT1 port map (in1 => A1, out1 => A1_n); g2: AND2 port map (in1 => A0_n, in2 => A1_n, out1 => N0); g3: AND2 port map (in1 => A0, in2 => A1_n, out1 => N1); g4: AND2 port map (in1 => A0_n, in2 => A1_n, out1 => N2); g5: AND2 port map (in1 => A0, in2 => A1, out1 => N3); g6: AND2 port map (in1 =>EN, in2 => N0, out1 => D0); g7: AND2 port map (in1 => EN, in2 => N1, out1 => D1); g8: AND2 port map (in1 => EN, in2 => N2, out1 => D2); g9: AND2 port map (in1 => EN, in2 => N3, out1 => D3); end structural_1;
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Cont .. Structural VHDL Description of 2-to-4 Line Decoder

A1_n
A0_n
architecture structural1_1 of decoder_2_to_4_w_enable is -- component NOT1 declaration -- component NAND2 signal A0_n, A1_n, N0, N1, N2, N3: std_logic; begin g0: NOT1 port map (in1 => A0, out1 => A0_n); g1: NOT1 port map (in1 => A1, out1 => A1_n); g2: AND2 port map (in1 => A0_n, in2 => A1_n, out1 => N0); g3: AND2 port map (in1 => A0, in2 => A1_n, out1 => N1); g4: AND2 port map (in1 => A0_n, in2 => A1_n, out1 => N2); g5: AND2 port map (in1 => A0, in2 => A1, out1 => N3); g6: AND2 port map (in1 =>EN, in2 => N0, out1 => D0); g7: AND2 port map (in1 => EN, in2 => N1, out1 => D1); g8: AND2 port map (in1 => EN, in2 => N2, out1 => D2); g9: AND2 port map (in1 => EN, in2 => N3, out1 => D3); end structural_1;
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Usage for Decoders
Implement logic circuits! Memory address lines Decoders are used in Micro Computer Interfacing for Keyboard and Display applications.
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Decoders as General-purpose Logic
n:2n decoder implements any function of n variables

With the variables used as control inputs Enable inputs tied to 1 and Appropriate minterms summed to form the function
Decoder generates appropriate minterm based on control signals (it "decodes" control signals)
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Decoders as General-purpose Logic
Example: Implement the following boolean functions

1. 2.
S(A2,A1,A0) = SUM(m(1,2,4,7))
C(A2,A1,A0) = SUM(m(3,5,6,7))
1.
Since there are three inputs, we need a 3-to-8 line decoder. The decoder generates the eight minterms for inputs A0,A1,A2 An OR GATE forms the logical sum minterms required.
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2.
3.
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Example
F1 = A' B C' D + A' B' C D + A B C D

0 1 2 3 4 5 6 4:16 7 DEC 8 9 10 11 12 13 14 15 A B C D A'B'C'D' A'B'C'D A'B'CD' A'B'CD A'BC'D' A'BC'D A'BCD' A'BCD AB'C'D' AB'C'D AB'CD' AB'CD ABC'D' ABC'D ABCD' ABCD
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F1
Enable
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Encoder
Encoder is the opposite of decoder 2n inputs (or less maybe BCD in) n outputs Examples:

Octal to binary Hexadecimal to binary
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Truth Table (Octal to binary)
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Inputs are Minterms

A0 = D1 + D3 + D5 + D7
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Whats the Problem?
What if D3 and D6 both high? Simple OR circuit will set A to 111 Solution?
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Priority Encoder
Chooses one with highest priority
Largest number, usually
Note dont cares
What if all inputs are zero?

Need Another Output!
A Valid Output!
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Valid is OR of all inputs
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Multiplexer (or Mux)
Selects one of a set of inputs to pass on to output Binary control code, n lines
Choose from 2n inputs
74153
Useful for choosing from sets of data
Memory or register to ALU
Very common
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Two Input Multiplexer
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4-to-1 Line Multiplexer
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Logic is Decoder Plus .
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Compare the two Diagrams!
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Dataflow VHDL Description of 4-to-1 Multiplexer

-- 4-to-1 Line Mux; Conditional Dataflow VHDL Descrip library ieee; use ieee.std_logic_1164.all entity multiplexer_4_to_1_we is port (S: in std_logic_vector(1 downto 0); I: in std_logic_vector(3 downto 0); Y: out std_logic; end multiplexer_4_to_1_we;
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Cont .. Dataflow VHDL Description

architecture function_table of multiplexer_4_to_1_we is -- Using When Else Begin Y <= I(0) when S = 00 else I(1) when S = 01 else I(2) when S = 10 else I(3) when S = 11 else `X; end function_table;
Quad 2-to-4 Line Mux
Select one set of 4 lines
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Muxes as General-purpose Logic
2n:1 multiplexer implements any function of n variables 1. With the variables used as control inputs and 2. Data inputs tied to 0 or 1 3. In essence, a lookup table Example: F(A,B,C) = m0 + m2 + m6 + m7
= A'B'C' + A'BC' + ABC' + ABC

1 0 1 0 0 0 1 1
0 1 2 3 4 8:1 MUX 5 6 7 S2 S1 S0 A B
C
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Multiplexers as General-purpose Logic (contd)
2n-1:1 mux can implement any function of n variables With n-1 variables used as control inputs and Data inputs tied to the last variable or its complement Example: F(A,B,C) = m0 + m2 + m6 + m7 = A'B'C' + A'BC' + ABC' + ABC
1 0 1 0 0 0 1 1
0 1 2 3 4 8:1 MUX 5 6 7 S2 S1 S0 A B
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
F 1 0 1 0 0 0 1 1
C' C' 0 1
C' C' 0 1
0 1 4:1 MUX 2 3 S1 S0 A B
C
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Demultiplexer
Takes one input Out to one of 2n possible outputs
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Demux is a Decoder
With an enable
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Decoder Expansion

A 2-to-4 Line decoder requires 4 (2-input) AND gates A 3-to-8 line decoder requires 8 (3-input) AND gates If we want to design a 6-to-64 line decoder then we will need? 64 (6-input) AND gates! Unfortunately, as decoders become larger, this approach gives a high gate input count! Instead we will resort to a procedure that uses design hierarchy to construct any decoder with n inputs and 2n outputs. The resulting decoder should have the same or a lower gate input count than the one constructed simply enlarging each AND gate.
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Decoder Expansion
To design a 3-to-8 line decoder (n=3) we can use a 2-to-4 line decoder and 1to-2 line decoder feeding eight 2-input AND gates to form the minterms instead of using eight 3input AND gates!
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General Procedure
1. 2. 3.
4. 5.
1.
2.
Let k=n. If k is even, divide k by 2 to obtain k/2. Use 2k AND gates driven by two decoders of output size 2k/2. If k is odd, obtain (k+1)/2 and (k-1)/2. Use 2k AND gates driven by a decoder of output size 2(k+1)/2 and a decoder of output size 2(k-1)/2 For each decoder resulting from step (2-3) (4-5), repeat with values obtained in step 2 until k=1. For k=1, use a 1-to-2 decoder.
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Decoder Expansion - Example 1
3-to-8-line decoder Number of output ANDs = 8 Number of inputs to decoders driving output ANDs = 3 Closest possible split to equal (k+1)/2 2-to-4-line decoder (k-1)/ 2 1-to-2-line decoder 2-to-4-line decoder Number of output ANDs = 4 Number of inputs to decoders driving output ANDs = 2 Closest possible split to equal Two 1-to-2-line decoders See next slide for result
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Decoder Expansion - Example 1
Result
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Multi-Level 6-to-64
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Aside: K Map for A0
X on input means we must satisfy for both possibilities: 0, 1
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Variations
At right
Enable not Inverted outputs

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Variations
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Structural VHDL Description of 4-to-1 Line Multiplexer

S_n(0:1) D(0:3) N(0:3)
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Cont .. Structural VHDL Description of 4-to-1 Multiplexer

-- 4-to-1 Line Multiplexer; structural VHDL Description library ieee; use ieee.std_logic_1164.all entity multiplexer_4_to_1_st is port (S: in std_logic_vector(0 to 1); I: in std_logic_vector(0 to 3); Y: out std_logic; end multiplexer_4_to_1_st;
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architecture structural_2 of multiplexer_4_to_1_st is component NOT1 port(in1: in std_logic; out1: out std_logic); end component; component AND2 port(in1, in2: in std_logic; out1: out std_logic); end component; component OR4 port(in1, in2, in3, in4: in std_logic; out1: out std_logic); end component;
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architecture structural_2 of multiplexer_4_to_1_st is -- component NOT1 AND2 OR4 declarations signal S_n : std_logic(0 to 1); signal D, N : std_logic_vector(0 to 3); begin g0: NOT1 port map (S(0), S_n(0)); g1: NOT1 port map (S(1), S_n(1)); g2: AND2 port map (S_n(1), S_n(0), D(0)); g3: AND2 port map (S_n(1),S(0), D(1)); g4: AND2 port map (S(1),S(0), D(3)); g5: AND2 port map (S(1), S(0), D(3)); g6: AND2 port map (D(0), I(0), N(0)); g7: AND2 port map (D(1),I(1), N(1)); g8: AND2 port map (D(2),I(2),N(2)); g9: AND2 port map (D(3),I(3), N(3)); g10: OR4 port map (N(0), N(1), N(2), N(3), Y); end structural_2;

ENG241 Comb Logic Design PartB Week4

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ENG241 Digital Design

Week #4 Combinational Logic Design Part B

Chapter #4, Mano Sections

4.1 4.3 4.4 4.5 4.6

Combinational Circuits Decoding Encoding Multiplexers Comb Function Implementations

Combinational circuit Implementation Priority Encoders Combinational Circuit Implementation

Example: Binary to Octal, Binary to Hex, e.t.c

2-to-4 Line Decoder

Notice they are minterms

Truth Table, 3-to-8 Decoder

Notice they are minterms

3-to-8 Line Decoder Schematic

2-to-4 with Enable

Enable Used for Expansion

VHDL Design Styles

Subset most suitable for synthesis

Decoder: Data Flow

When Else Statement

Decoder: Data Flow #2

D(3) A(1) D(2) D(1)

Structural VHDL Description of 2-to-4 Line Decoder

Structural VHDL Description (Entity Declaration)

Structural VHDL Description (Signals)

Structural VHDL Description (Components)

Structural VHDL Description (Connecting components)

Cont .. Structural VHDL Description of 2-to-4 Line Decoder

Usage for Decoders

Decoders as General-purpose Logic

n:2n decoder implements any function of n variables

Decoders as General-purpose Logic

Example: Implement the following boolean functions

F1 = A' B C' D + A' B' C D + A B C D

Octal to binary Hexadecimal to binary

Truth Table (Octal to binary)

Inputs are Minterms

Whats the Problem?

Chooses one with highest priority

Largest number, usually

Note dont cares

What if all inputs are zero?

Need Another Output!

Valid is OR of all inputs

Multiplexer (or Mux)

Choose from 2n inputs

Useful for choosing from sets of data

Memory or register to ALU

Two Input Multiplexer

4-to-1 Line Multiplexer

Logic is Decoder Plus .

Compare the two Diagrams!

Dataflow VHDL Description of 4-to-1 Multiplexer

Cont .. Dataflow VHDL Description

Quad 2-to-4 Line Mux

Select one set of 4 lines

Muxes as General-purpose Logic

= A'B'C' + A'BC' + ABC' + ABC

Multiplexers as General-purpose Logic (contd)

Takes one input Out to one of 2n possible outputs

Decoder Expansion - Example 1

Decoder Expansion - Example 1

Aside: K Map for A0

X on input means we must satisfy for both possibilities: 0, 1

Enable not Inverted outputs