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4-bit Carry Look Ahead Adder

Samira Sharma Suneera Sharma Advisor: Dave Parent 12/6/04


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Agenda
Abstract Introduction
Why Simple Theory

Summary of Results Project (Experimental) Details Results Cost Analysis Conclusions


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Abstract
We designed an 4-bit carry look ahead adder that operated at 200 MHz and used 16mW of Power and occupied an area of 420x440m2

Introduction
Why is a Carry Look Ahead Adder important? - The CLA is used in most ALU designs - It is faster compared to ripple carry logic adders or full adders especially when adding a large number of bits. The Carry Look Ahead Adder is able to generate carries before the sum is produced using the propage and generate logic to make addition much faster.
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Equations for Logic of 4-bit CLA


Gi = Ai.Bi Pi = (Ai Bi) C1 = G0 + P0.C0 C2 = G1 + P1.C1 = G1 + P1.G0 + P1.P0.C0 C3 = G2 + P2.G1 + P2.P1.G0 + P2.P1.P0.C0 C4 = G3 + P3.G2 + P3.P2.G1 + P3P2.P1.G0 + P3P2.P1.P0.C0 Si = Ai Bi Ci = Pi Ci.

4-Bit Carry Look Ahead Adder Gate Level Design

Project Summary
We used the gate design methodology instead the AOI design method for Carry logic because of its lesser drain caps we were able to meet timing specifications, also, made hand calculations easier to do. We used a less complicated design and created separate cells in order make debugging easier and also allow for a neater layout.
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Design Flow
Functions and Specs Designing For Logic Hand Calculations

Initial Sizing

Stick Diagrams Layout

DRC & Extraction Post Extraction LVS


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Longest Path Calculations


L o g i c L e Gv a tl e C g t o DNr S v Ne e i 1 X O1R 11 1 1 IN V 11 1 1 O1 R 11 1 1 O1 R 11 1 1 A N1D 11 1 1 X O1R 11 1 1 A N1D 11 1 .

N S P N M W N ( H . C ) ( W . N )WS P (W )N ( W ) P W P H C ( ) S L 1 1 1 1 11 1 11 1 11 1 1 1 11 1 1 . . . . . . 1 1 1 1 11 1 11 1 11 1 11 1 11 1 11 . . . . . . 1 1 11 1 11 11 111 1 1 1 1 1 . . . . 1 1 1 1 11 1 11 1 1 1 1 1 1 . . . . 1 1 1 1 11 1 11 1 1 1 11 1 1 1 11 . . . . . . 1 1 1 1 11 1 1 1 1 1 1 1 1 1 1 . . . . . . 1 1 1 1 11 1 11 1 1 1 11 1 1 1 11 . . . . . .
Note: All widths are in microns and capacitances in fF
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tPHL = 5ns/11 = 0.45ns

Schematic: DFF

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Schematic: Generate and Propagate

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Schematic: Carry Generator

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Schematic: Sum Generator

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Final Schematic

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Schematic TB

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Final Simulation
Test Vectors A=1 B=0 Cin= 1111 +0000 1111 1 1111 0000 10000
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Final Layout

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LVS Verification
Net-lists match!

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Cost Analysis
verifying logic = 10 hours verifying timing = 20 hours Layout = 50 hours post extracted timing = 5 hours

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Lessons Learned
Learn the tradeoffs of AOI vs. Gate Design Methodology -Area Constraints -Timing Constraints Develop Good testing and debugging skills. Have Fun!

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Summary
We met specifications by designing a 4-bit Carry Look Ahead Adder -Rise time= Fall time= 2.65 ns -Total Area= 420x440m2 -Power= 16 mW In the future this circuit design can be designed using less power and operating at a higher frequency.
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Acknowledgements
Thanks to Cadence Design Systems for the VLSI lab Thanks to all our classmates that helped us in the lab Professor David Parent for setting us up for success! Undo, Stretch, Copy, Move and Metal 1,2 and 3!
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