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BATCH NO: A4
INTERNAL GUIDE K.CHIDAMBARA RAO Assoc.Professor Dept. of ECE Presented by: B.RASAZNA (08A51A0417) G.SRIRAM (08A51A0441) I.SIVAJI (08A51A0444) D.PRIYANKA (08A51A0426) B.SRINU (08A51A0418)
Abstract
The main objective is to design and implementation WIFI MAC Transmitter using VHDL. For the wireless communication in RF range IEEE 802.11 is one of the many standards available . IEEE 802.11b defines the Medium Access Control Layer for wire less local area networks.
Wi-Fi MAC transmitter module is divided into 5 blocks I.e.. data unit interface block, controller block, payload data storage block, MAC header register block, data processing block. In this project, we are considering only two blocks i.e. payload data storage block, data processing block
Introduction to WIFI
Wireless Technology is an alternative to Wired Technology, which is commonly used, for connecting devices in wireless mode. Wi-Fi (Wireless Fidelity) is a generic term that refers to the IEEE 802.11 communications standard for Wireless Local Area Networks (WLANs). Wi-Fi Network connect computers to each other, to the internet and to the wired network.
Standard
Speed Range
802.11b
11 Mbps 100-150 feet indoors
802.11a
54 Mbps 27-75 feet indoors
802.11g
54Mbps 100-150 feet indoors
Frequency
Acceptance
802.11g is compatible with the specs for 802.11b, meaning it can be used on a network based on b or g versions.
Wi-Fi cards -
Safeguards -
Explanation:
The architecture contains five blocks 1.MAC Header 2.Data unit interface block 3.Data Processing block 4.Pay Load Data storage block 5.Controller block
MAC Header:
Duration /ID: The Duration ID is 16 bits length. It carries the association identity of the station that transmitted the frame . Address1: Always receiver address (i.e. the station on the BSS who is the immediate receiver of the packet).
Control Block:
It control the functioning of all the blocks in the architecture.
FIFO:
Sys clk Sys rst FIFO Data FULL FIFO EMPTY
Data in
FIFO ENA
Data length counter module acts as counter.it simply accepts a Max Number and counts the data being transmitted .
S bit
sysrst srena data Serializer eoc
HEC Module:
clk rst S bit hEC calena HEC HECover HEC out
This module produces the Head Error Check bits. It is the 16-bit error check bit.the HEC is calculated when the HRCCalEna is high
CRC Module:
clk CRCout
rst
S bit CRC calena CRC CRC over
Figure shows CRC module the CRC is 32bit field contain the 32 bit cyclic Redundancy check.
ABOUT VHDL
What is the scope of VHDL? Why VHDL is used? Power and flexibility Devices- independent design ASIC Migration Benchmarking capability Quick Time-to-Market and low cost
ABOUT XILINX
Advantages
Mobility Ease of Installation Flexibility Cost Reliability Security Use unlicensed part of the radio spectrum Speed Low power consumption
Limitations
Interference Degradation in performance Limited range
Conclusion
Various individual modules of Wi-Fi Transmitter have been designed, verified functionally using VHDL -simulator, synthesized by the synthesis tool . This design of the WiFi transmitter is capable of transmitting the frame formats. The transmitter is also capable of generating errorchecking codes like HEC and CRC. It can handle variable data transfer