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Counter Competencies
29. Given the schematic diagram of a counter circuit, the student will determine if this counter is synchronous or asynchronous. 30. Given a schematic of an asynchronous counter, the student will identify the LSB flip-flop.
31. Given a schematic of a synchronous counter, the student will identify the LSB flip-flop. 32. Given the schematic of a counter and the value currently on the counter, the student will determine the new counter value if an instructor specified number of pulses are applied to the counter
Counter Competencies
33. Given a modulus number from 16 to 32, the student will draw a schematic of flip-flops and NAND gates that will count this modulus starting with zero. 34. Given the schematic diagram of a synchronous counter circuit, the student will determine the modulus of the counter. 35. Given the schematic diagram of a synchronous counter circuit, the student will determine the counting sequence and list the sequence in decimal. 36. Given the schematic diagram of a counter and the clock input frequency, the student will determine the output frequency of the counter.
COUNTER UNIT
Asynchronous up and down counters Asynchronous modulus counters Seven segment displays/ BCD coding Synchronous Counters Pre-settable Counters Ring Counters
COUNTERS CHARACTERISTICS
1. MODULUS- number of counts in one cycle 2. Up or down count 3. Asynchronous or synchronous operation 4. Free running or self stopping
ASYNCHRONOUS COUNTERS
Only LSB flip-flop controlled by the clock input Also known as a RIPPLE COUNTER Two or more T flip-flops interconnected, output of each flip-flop connected to clock input of the next. Modulus- number of stable states in each flip-flop cycle Modulus =
N= number of flip-flops
N 1
C
C CLK K 1 J 1
B
B CLK B K 1 J 1
A
A CLK A K 1 J 1
TEST
1. What is the term for the number of counts in one counter cycle? Modulus of the counter 2. How is the modulus determined? 2 N N = number of flip flops 3. Since only the first flip-flop of a ripple counter is controlled by a clock, the counter is ____________________? Asynchronous 4. What is the mod number of a counter containing 5 flip-flops? 32 5. What is the highest count of a four bit counter? 31
B
B CLK K 1 J 1
A
A CLK A K 1 J 1
INPUT CLK 0 1 2 3 4 5 6 7 C 0 0 0 0 1 1 1 B 0 0 1 1 0 0 1 A 0 1 0 1 0 1 0
B C
m a s te r re s e t
UNSTABLE STATE
3. Determine which FFs will be high at count = X Connect the Q outputs of these FFs to NAND gate inputs
2 = 8 and 2 = 16
3 4
2. Connect a NAND gate to asynchronous clears of all FFs 3. Determine which FFs will be high at count = X Connect the Q outputs of these FFs to NAND gate inputs 1 1 0 0
D
D CLK D K 1 C J 1
C
C CLK K 1 J 1
B
B CLK B K 1 J 1
A
A CLK A K 1 J 1
SELF-STOPPING COUNTER
Counters may be made to stop counting after any desired count by using a gate to inhibit the clock. Stop at desired count:
0
C CLK K 1 J 1
1
B CLK B K 1 J 1
0
A CLK A K 1 J 1
D C B A
1
D CLK D K 1 J 1
1
C CLK C K 1 J 1
0
B CLK B K 1 J 1
0
A CLK A K J
C D
COUNTER PROBLEM
1. What is the value of the last usable state before the NAND gate resets the circuitry? 1101= 13 2 10 2. What value does the NAND gate reset the value to? 1000 2 = 810 3. What is the modulus of this counter?
4. If count starts at decimal 11 and receives seven clock pulses, what is the new value on the counter? 1210 5. What is the unstable state of the counter? 1110 2 = 1410
A B C D
0V
S J Q CP K QN R
S J Q CP K QN R
S J Q CP K QN R
S J Q CP K QN R
COUNTER PROBLEM
1. What is the value of the unstable state, in decimal?
111= 710 2
2. At what value does the NAND gate set the counter to? QC= 1 QB= 0 QA= 0
0112 = 310
3. If QA=1, QB=1, and QC=0, and 5 clock pulses are applied: 4. What is the modulus of this counter? 4
1 A
+V 0V S J Q CP K QN +V R +V S J Q CP K QN R
2 B
+V S J Q CP K QN R
4 C
IC ASYNCHRONOUS COUNTERS
Logic Diagram for 7493
___ CPo ___ CP1 MR1 MR2 Qo (L S B ) Q1 Q2
*All J, K inputs internally connected HIGH J Q CP K QN R J Q CP K QN R J Q CP K QN R J Q CP K QN R
Q3 (M S B )
Q3 (M S B )
7493
Q Q Q Q
10 kH z
MR
MR
F = 1 0 k H z /1 6 = 6 2 5 H z
TEST
Build a MOD 10 counter with a 7493 Logic Diagram for 7493
___ CPo ___ CP1 MR1 MR2 Qo (L S B ) Q1 Q2
*All J, K inputs internally connected HIGH J Q CP K QN R J Q CP K QN R J Q CP K QN R J Q CP K QN R
Q3 (M S B )
7493
Q Q Q Q
10 kH z
MR
MR
F = 1 0 k H z /1 0 = 1 K H z
BCD COUNTER
Binary counter that counts from 0000 to 1001 before it recycles (MOD-10). Widespread applications where pulses or events are to be counted and the results displayed on a decimal numerical read-out. Also used for dividing a pulse frequency exactly by 10.
MOD-60 COUNTER
M O D 6 M O D 10
7493
Q Q Q Q
7493
Q Q Q Q
f in
MR
no t used
MR
MR
f o u t = fin / 6 0
f in / 1 0
DIGITAL CLOCK
COUNTERS
ASYNCHRONOUS
J Q CP K QN R S J Q CP K QN R S J Q CP K QN R S S J Q CP K QN R
SYNCHRONOUS
D S Q D S Q D S Q D S Q
CP QN R
CP QN R
CP QN R
CP QN R
SYNCHRONOUS COUNTERS
Two or more FFs connected as T FFs. All FFs in the counter are clocked at the same time. Advantage over the ripple counter is speed and accuracy but more complex.
5V S S S S
5V +V Q J CP QN K R Q J CP QN K R Q J CP QN K R Q J CP QN K R 0V
5V
J CP QN K R
J CP QN K R
J CP QN K R
J CP QN K R 0V
5V
5V
PRESETTABLE COUNTERS
Can be preset to any desired count. To operate: 1. Apply desired count to parallel data inputs P2, P1, P0. 2. Apply a low pulse to the parallel load input PL.
P2 P1 Po P A R A LLE L D A T A IN P U T S
5V +V Q J CP QN K R S Q J CP QN K R S Q J CP QN K R 5V S
C LOC K P A R A LLE L _L _O A D PL
COUNTER TYPES
Asynchronous Counter (a.k.a. Ripple or Serial Counter): each FF is triggered one at a time with output of one FF serving as clock input of next FF in the chain. Synchronous Counter (a.k.a. Parallel Counter): all the FFs in the counter are clocked at the same time. Up Counter: counter counts from zero to a maximum count. Down Counter: counter counts from a maximum count down to zero. BCD Counter: counter counts from 0000 to 1001 before it recycles. Pre-settable Counter: counter that can be preset to any starting count either synchronously or asynchronously Ring Counter: shift register in which the output of the last FF is connected back to the input of the first FF. Johnson Counter: shift register in which the inverted output of the last FF is connected to the input of the first FF.
74193 COUNTER
MOD-16 PRESETTABLE UP/DOWN COUNTER
RING COUNTER
Shift register counter with feedback from Q of last FF back to first FF input
RING COUNTER
5V S S S
D 5V 0V
CP QN R
CP QN R
CP QN R
CP QN R
clk
JOHNSON COUNTER
Shift register in which the inverted output of the last FF is fed back to the input of the first FF.
5V S S S
D 0V 0V
CP QN R
CP QN R
CP QN R
CP QN R
clk
Lab 18.
A PROGRAMMABLE COUNTER
Design a four-bit counter controlled by two control lines X and Y that behaves according to the truth table.
PROGRAM SWITCH X Y 0 0 0 1 1 0 1 1
Lab 18.
A PROGRAMMABLE COUNTER
5V Q1 CP1 Q2 CP2 S S S S
J CP QN K R
J CP QN K R
J CP QN K R
J CP QN K R
_ XYAC _ XYBD
XYCD
X
1 0 0 X
Y
P S R O W
M O D 1 2 1 0
M O D 5
N O
M O D
C O U N T E
M O D E
G R A
IT C H
C O U N T
RIPPLE COUNTER
Binary Output Clock Input
1 1 1 1 0 0 0 0
Pulse 2 8 7 6 4 3 5 1
PS the next clock pulse states and Thisand CLR input has 16 (8) all FFs On 4-bit counter All J-K flip-flops will count are because each in the will toggle from binary 0000 will receive through 1111 INACTIVE TOGGLE MODE a H-to-L pulse- one after another. and then reset back to 0000. Watch the counthas a modulus of 16. The counter ripple thru the counter.
0 1 0 1 0 1 0
Pulse 2 4 3 5 1
Clock input FFs triggered on 1s output H-to-L pulse. CLK toggles 1s FF. 1s FF toggles 2s FF. output 2s 2s FF toggles 4s FF. 4s output
DECADE COUNTER
Binary Output Clock Input
11 at 0 unt l co ia Init
0 1 1 1 1 0 0 0
Short negative pulse
Pulse 2 8 7 6 4 3 5 1
DOWN COUNTER
0 1 1 1 0 0
unt l co a Initi t at se 111 nary bi
4 1 Pulse 2 3 5
Changes from Ripple Up Counter are wiring from Q outputs (instead of Q outputs) to the CLK input of the next FF.
0 1 1 1 0 0
4 3 Pulse 2 8 6 5 1 7
This is a 3-bit down counter. The 1s FF is in TOGGLE mode when counting (J & K = 1). The 1s FF switches to HOLD mode when the J and K inputs are forced LOW by the OR gate when the count decrements to 000. The count stops at 000.
200 Hz 100 Hz
4 400 Hz 2
800 Hz
MAGNITUDE COMPARATOR
A magnitude comparator is a combinational logic device that compares the value of two binary numbers and responds with one of three outputs (A=B or A>B or A<B).
A(0) A(1)
Input binary 0111 Input binary 1111 Input binary 0001
A(2) A(3 )
B(0) B(1)
Input binary 0111 Input binary 1100 0110
A = B A < B
B(2) B(3 )
TROUBLESHOOTING EQUIPMENT Logic Probe Logic Pulser Logic Clip (logic monitor) Digital IC Tester DMM/Logic Probe DMM or VOM Dual-trace Oscilloscope Logic Analyzer