Why Need HW/SW Co-design?

IC design has ushered in a new era SoC

System on a Chip

Why Need HW/SW Co-design?

What is SoC?

Why Need HW/SW Co-design?

What is our first step?

Processor? Memory? Operating System? Peripheral Interface? CAD Tools? What else?

What is our first step?

Core IP (Processor)

PC && Workstation

Intel Pentium Ultra SPARC MIPS 8051 TI,

Micro-Controller

DSP

SoC

ARM Power PC Configurable Tensilica Processor

SOPC

Altera Nios Xillinx Micro-Blaze

Is there any opportunity for us in this area?

 Memories Design is our chance?

What is our first step?

Process? PC & Workstation

Operating System is another opportunity?

Windows Unix Solaris, HP-Unix Linux eCos Micrium uC/OSII Shugyo Design KROS Accelerated Technology Nucleus Plus VxWork
Windows CE uCLinux

RTOS

Embedded System

What is our first step?

Peripheral IP Design is one way for us?

PrimeCell ARM Synopsys FPGA Vendor -Open Core Web Site www.opencores.org ... Cadence Synopsys Mentor

EDA CAD Tool?

What is our first step?

Can We Find Our Way in SoC or HW/SW Codesign Era?

Master in applications

ASIC SW

Time to Market is another important thing

Use Well-Design IP Embedded Linux, RTOS

Integration
System is the keyword of SoC How to transition from on-board design to on-chip design?

What else?

AMBA Bus (One Important Issue)

Advanced Microcontroller Bus Architecture

AMBA BUS

AMBA BUS

AMBA BUS

AMBA Buses

Advanced System Bus (ASB) Advanced High-Performance Bus (AHB)

Processors On-Chip Memory Off-Chip External Memory with low power peripheral macrocell Bridge : to APB High Speed ASIC Your Design

Advanced Peripheral Bus (APB)

Peripheral Interface

UART Timer Low Speed ASIC Your Design

AMBA BUS

Advanced High-Performance Bus : AHB

AMBA BUS

Advanced High-Performance Bus : AHB

AMBA BUS AHB

Advanced High-Performance Bus : AHB

AHB master is able to initiate read and write operations by providing an address and control information. Only one bus master is allowed to actively use the bus at any one time.(max. 16) AHB slave responds to a read or write operation within a given address-space range. The bus slave signals back to the active master the success, failure or waiting of the data transfer. AHB arbiter ensures that only one bus master at a time is allowed to initiate data transfers. AHB decoder is used to decode the address of each transfer and provide a select signal for the slave that is involved in the transfer. A single centralized decoder is required in all AHB

AMBA BUS AHB

AMBA BUS AHB

AMBA BUS AHB

Basic Transfer of AHB

AMBA BUS AHB

Transfer Types of AHB

AMBA BUS AHB

Burst Operation of AHB

AMBA BUS

AMBA BUS

AMBA BUS AHB

Incrementing bursts access sequential locations and the address of each transfer in the burst is just an increment of the previous address.
An incrementing burst can be of any length, but the upper limit is set by the fact that the address must not cross a 1kB boundary

For wrapping bursts, if the start address of the transfer is not aligned to the total number of bytes in the burst (size x beats) then the address of the transfers in the burst will wrap when the boundary is reached. For example, a four-beat wrapping burst of word (4-byte) accesses will wrap at 16-byte boundaries. Therefore, if the start address of the transfer is 0x34, then it consists of four transfers to

AMBA BUS AHB

There are certain circumstances when a burst will not be allowed to complete and therefore it is important that any slave design which makes use of the burst information can take the correct course of action if the burst is terminated early. The slave can determine when a burst has terminated early by monitoring the HTRANS signals and ensuring that after the start of the burst every transfer is labelled as SEQUENTIAL or BUSY. If a NONSEQUENTIAL or IDLE transfer occurs then this indicates that a new burst has started and therefore the previous one must have been

AMBA BUS AHB

AMBA BUS AHB

AMBA BUS AHB

HSIZE[2:0] of AHB

AMBA BUS AHB

The protection control signals, HPROT[3:0] of AHB

AMBA BUS AHB

AHB Bus Slave

AMBA BUS AHB

AHB Bus Master

AMBA BUS AHB

AHB Arbiter

AMBA BUS AHB

AHB Decoder

AMBA BUS APB

Advanced Peripheral Bus : APB

The AMBA APB should be used to interface to any peripherals which are lowbandwidth and do not require the high performance of a pipelined bus interface.