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Design and Implementation Of a Parallel Wallace Tree Multiplier using Verilog HDL

Submitted By Biswabrata Guha Roy Debarshi Chakraborty Anup Nayak Rakesh Ghosh
Branch: Btech in Electronics And Communication Engineering

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Guided By: Mr. Mayur De


Click to edit Master subtitle style

Future Institute Of Engineering And Management

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What is a multiplier?

A multiplication circuit is usually referred to as a multiplier.

A multiplier takes two binary operands to generate a product. It is built using binary adders.

A variety ofcomputer arithmetictechniques can be used to implement a digital multiplier.

Most techniques involve computing a set ofpartial products, and then summing the partial products together.

This process is similar to the method taught to primary schoolchildren for conducting long multiplication on base-10 integers.

Classification of multipliers

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Multiplication Operation Of Wallace Tree Multiplier


Multiplier Multiplican d
a3 a3 b3 b2 a2 b3 a3 a2 a2 a1 a0 b2 P P P P5 P4 P3 2 1 0 a1 a1 a0 a0 a0

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x b3
a3 b0 a3 b1 a2 b2 a1 b3 a0 b3 P6 a2 b1 a1 b2

b2 b1 b0 b0 b0 b0 b1 b1

Partial product1 Partial product2 Partial product3 Partial product4

Binary Multipliers

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Multiplication Example:15x7
Multiplicand: Multiplier: 11 11 0111 _________ 1111 1111 partial products 1111 0000 ______________ 4 15 7

What is Wallace tree?


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AWallace treeis anefficientimplementation of a digital circuit that multiplies two integers. This method was devised by an Australian Computer ScientistChris Wallacein 1964.

Structure: The structure consists of AND gates and adders arranged in a tree structure. A 4*4 bit Wallace tree multiplier is constructed with 8 full adders ,4 half adders and 16 AND gates. Performance : The Wallace Tree Multiplier performs well for unsigned operands in terms of speed, power and area. Besides it has a simple and regular structure as compared to other multiplier schemes.

Multplier Implementation Block Diagram


A B Partial product generator

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Wallace tree structure S C Ordinary adder Multiplier output

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ALGORITHM

The Wallace tree has three steps:

(1)

the bit products(partial products) are formed.

(2) the bit product matrix is reduced to a two row matrix by using a carry- save adders (known as Wallace Tree). (3) the remaining two rows are summed using a fast carry-propagate adder or ripple carry adder to produce the product.

Implementation using Carry Save Adder(CSA) addition of m numbers in lesser duration CSA performs the

compared to the simple addition. It takes three numbers (a + b + c) to add together and ouputs two numbers, sum and carry (s + c). The carry-save addition is carried out in three steps. In the first step, it computes sum without considering carries as shown below. i: 1 2 3 7 9 j: 3 3 9 0 1 k: 0 4 1 1 1 In the second step, compute the carry on each column ignoring s: 4 9 3 8 1 sum as shown below. The important thing to note is that the carry calculated for one column is the carry obtained from adding the digits in the previous column. i: 1 2 3 7 9 j: 3 3 9 0 1 k: 0 4 1 1 1 c: 0 1 0 1

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In the final step, add both sum and carry to obtain the final result. In this last step, the ordinary addition is carried out as shown below.

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s: 4 9 3 8 1 c: 0 1 0 1 sum: 5 0 3 9 1 Since carry c and sum s can be computed independently, this achieves the goal of converting the duration required for the addition of three numbers into the duration required for addition of two numbers duration. The same concept can be applied to addition of binary numbers. For example,

i: 1 0 1 1 j: 0 1 0 0 k: 0 0 0 1 s: 1 1 1 0 c: 0 0 1 0 sum: 1 0 0 0 0

The Carry Save Adder: Add Operation

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Balanced and overturned-stairs have regular structure - can be designed in a systematic way

Generation of Partial Products using AND gates

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Circuit Implementation of Wallace Tree with AND gate & ADDERS

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Partial Product Generation: 1 1 1 0 1 0 0 1 0 1 1 1 0 0 0 1 1 0 1 0 0 0 0 0 1 0 0 0 0 01 1 1 1 (PP0) Partial Product number (P (P P1 (P P2 (P ) P3 ) (P P4 ) (Su P5 ) m) ) CSA P 0 0 0 00 01 P 1 1 0 0 P P 1 1 0 0 10 P 3: S 10 1 0 11 P 11 4: C 1 1 0 0 01 0 0 0 5: 0 0 1 1: - No : Adder - Half Adder - Full Adder (Ordinary Addition) P P P P 4 5 C S C A 0 1

1 0 0 1 1 11 0 1 01 1 1 1 1 Wallace Tree Implementation: CSA P 11 10 0 00 P 00 00 0 P P 10 1 0 0 1 1 P 0: S 11 01 11 0 P 11 00 0 1: C 0 0 1 2: 0 0 CSA 0: 0: S 1 10 C 0 0 S 10 1 0 0 CSA S 10 0 0 0 0: C : 20 1 01 1 1 1 C 1 0 1 0 Ad S 01 1 0 : 00 0 0: C 1 01 : der 0 1: Su 1 0 00 1 1 2: m 1 2: : P P P P P P 0 1 2 C S S C 0 A 0 0 0C S S C 1 A 1 0 0C SC S A 2 C2 0 S0 A

0 1 0 0 0 1

01 10 1
F ARE_ P PRE_ HA POST_ NA HA POST_ NA

1 1 0 0 0 0 0 1 1

0 0 1 1 1 0 0 0 0

1 11 0 0 0 1 01 0 11 0 0 0 01 01 10 01 01 10 1 P P 3 S 0 1

Wallace Tree Method S U M

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ADVANTAGES
A Wallace tree multiplier is considerably fast. Min. propagation delay. Wallace tree multiplier uses significantly less power of bit widths between 8 and 32, with the advantage of Wallace tree growing as word length increases.

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Future Work

The

final objective of the project is that it is to be verified and implemented in a FPGA kit. we will be using Verilog HDL.

Here

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Reference

CMOS VLSI Design by Neil H.E. Heste, David Harris & Ayan Banerjee. FPGA Based System Design by Wayne Wolf. Websites: www.wikipedia.com www.google.com

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K N A H U T O Y

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