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2 :

1. ;
2. .

- ;
;
;
;
;
.
() -
, .
, .
, -, .
,
. .
2 :
1. ;
2. .
.
, , .
,
. (
).
(). :

.
, .
, .


:
1. : , , n-, , , 2.
2. .
3. .
.
4. .
5. :
, ;

.
2 :
1.

.
2.

, .. .
1971 Intel (4-). 1973 8-
Intel i4004.
Intel: i8008, i8080, i8085.


.
(Intel, Motorola, Zilog):
1) Intel i8080A, i8085A ( 58080);
2) Intel i80C85A ( 182185) 8- ;
3) Intel i8086 ( 181086), i80186, i80286 16- ;
4) i80386, i80486 32-;
5) Pentium (589 ; 1800 ; 1801, 1804 ).


1.
2.
3.

.
.
.

,
( , - ..).
2


( ) , ,
.
3 :
1) ;
2) ;
3) .
.
. .
.

, .
3- :
() , , -;
, ;
, .
:
1.
(015).
2.
(07).
3.
.
3- .
.
(/) ().
. .
( ),
.
3- :

;
- (, );
;
( );
.

, 3-
7 :
1. .
2. .
3. .
4. .
5. .
6. .
7. .
. 3-
, 3 .
:
1. MEMW ( , );
2. MEMR ;
3. IOW ( );
4. IOR .
U

MEMR


( )

3- :
L ;
H ;
Z .
Z

C S
IOW

OUT


, ,
, .

MEMW


,
,
, .

MEMR

()

IOW

()

IOR


ISR .
, .
.
:
;
;
.
,
.
().
IRQ1 IRQ2
INT

INT A

IRQ1, IRQ2 ;
INTA ;
INT .
IRQ
INT

INTA



.
.

.
- , .

58080 (80)
i8080. n-
3 2. DIP-.
:
8- ;
16- ( 65536 );
fT = 0,52,5 ( 2 ;
400 . ;
3- : +5 ; +12 5;
200 .

0
1

READY
RESET

15

A0 A15

INT

INTE
HLDA
D
DBIN

F1
F2

HOLD
D

0
1

CPU

WAIT

SYNC
UCC
D0 D7
7
UBS
GND
UCS
F1 F2 2- , fT;
7

READY (1 , 0
);
RESET ();
INT ;
HOLD ( );
D0 D7 ( 3 );
GND ();
A0 A15 ;
INTE (1 , 0 );
HLDA ;
DBIN (1 , 0
);
WR ( );
WAIT 1 , 0 ;
SYNC ;
UCC +5 ;
UBS +12 ;
UCS 5 .


:
1. - (, ),
.
2. (: W, Z, B, C, D, E, H, L; -; SP
);
3. ;
4. ( );
5. .
T, W, Z , (
), .
07

DA

SP
16
015

16

./.

T . ;
- ;
F ;
A ;
DA .


,
.
1.
2.
3. -
:
A [8]

F [8]

B [8]

C [8]

D [8]

E [8]

H [8]

L [8]

PC [16]

SP [16]
INTE [1]

AC

CY

5, 3, 1 .
1, , 0, .
S (1 , 0 ).
Z (1 = 0, 0
).
AC (1 3 4 , 0
).
P () (1 , 0 ).
CY (1
()).
.
SP . ,
.
INTE (1 , 0
).


8- , .
. (m
, 2 m ).
80 m = 16, 216 = 65536 = 64 , = 1024.
0000H

[8]

0001H

[8]

0002H

[8]

0003H

[8]

FFFEH
FFFFH
H

[8]
[8]

2 :
,
, .
.
, .
.

.
0000

03FF
0400

( )

64

07FF
0800
0BFF
0C00

FFFF

-
-
8- .
- ,
( 8 ). 28 = 256.

00
01

[8]

FE
FF

[8]

[8]

[8]

00
01

[8]

FE
FF

[8]

[8]

[8]

- 512. .
10

80
,
-:

0000



.
. F1 F2.
:
1. : 8 12 .;
2. F1 F2 ;
3. : 0,5 2,5 .
:
F1

58024

F2

>50

>10

>70

t
>220

= 1/fT
,
. .

11

,
. 1 5 .
:
1
1 2
1 2 3
1 2 3 4
1 2 3 4 5
10 ( 80):
1. ;
2. ;
3. ;
4. ;
5. ;
6. ;
7. ;
8. ;
9. ;
10. .
1- .
3 5 .
: 3- ; 4- 5-
.

1 2 3
1 2 3 4
1 2 3 4 5

MOV r1, r2 .
1
1

MOV r, M ( );
MOV M, r
1
1

2
3

HL

12


80 2 :
WR ;
DBIN ( ).
( ):
,
. ,
.
, .
.
.
CPU

D0-D7

D0
DI

D1
D2
RG

D3

D4
D5
S T,STB

SYNC

F1

D6
C

D7

T1

T2

T3

F1
F2
SYNC

D0D7

ST, STB

F2
, SYNC .
1 .
, ST, STB .
.
:
13


D0
D1
D2
D3
D4
D5
D6
D7


INTA
WO
STACK
HLTA
OUT
M1
INP
MEMR

INTA = INTA DBIN = D0 DBIN


MEMR = MEMR DBIN = D7 DBIN
MEMW = WO WR = D1 WR
IOR = INP DBIN = D6 DBIN
IOW = OUT WR = D4 WR

.
:
`
+5
.

1558

INTA
D0
D1
D4
D6

WO

&

WO

INTA
1

OUT

&

INP

MEMR

&

D7

3
CPU
D
DBIN

&

DBIN

4
&

WR

MEMR
MEMW
IOR
IOW


F1
, . .
F2 SYNC
. . 2-
F2
. F1 3.
DBIN . MEMR .
4 , .
14

, 5- . 4-
.
2- F2 READY
HOLD. READY = 0 , HOLD = 1
.
T2

T1

T3

T4

F1
F2

SYNC

DBIN
MEMR


1. () .
, ,
, . RESET .
RESET
t 3
0

= 1/fT

:
1. 0: (PC)0000H.
2. :

3. 0: (HLDA)0.

(INTE)0,

RESET = 0 :
0- ( ).
2. READY = 1. 2-
READY.
F2 READY = 0, .
. WAIT = 1.
READY,
.
.

15

3.
.
HOLD = 1 . 2- 1,
, Z .
HOLD 0 .
4.
. INTE, INTE = 1 ,
INTE = 0 . EI,
DI.
INT:
INT

INTE = 1, 0
INTE. ,
. :
1. ,
;
2. INTA.
RST N (N = 0, 1,,7).
.
3. , .
4. RET.

.

RST N
RST N
RST 0
RST 1
RST 2
RST 3
RST 4
RST 5
RST 6
RST 7

VVV
000
001
010
011
100
101
110
111

ISR, HEX
0000
0008
0010
0018
0020
0028
0030
0038

16

0000

RST 0

0008

RST 1

0010

RST 2

0018

RST 3

0020

RST 4

T2

T1

T3

T4

T5

F1
F2

RST

INTA

INTA. RST N.
5. HLT,
, ,
3- , WAIT = 1.
. 2- :
1. INT (INTE = 1),
,
, .
2. RESET
. .


;
;
-;
.
,
( 580 58085).
: ,
. . 3 80
:
1. 2
12 .
2. : I0 2 , I1 50 .
17

U
I

I0 1,6
I1 40

.
. ( ).
.
3. 80 .
.

16
015

F1
F2

D0D7

DBIN
WR

16

015

D0D7

.
58085 ;
58024 ;
58086 2- 8- (
I0 32 );
58028(38) , 2 8- :
1. ;
2. ;
3. .
5 (. . ).
.
BUSEN ( );
TF (TF = 1, ; TF = 0, ).

18

DD1 58024

+5
ZQ1

R1

DD2 58080

0
CPU
F1
1

X1

F1

X2

F2

F2

Ready

READY

Ready

R2

F2 Reset

DD3 58028

15
8
D0D7

A
0
1
7

SB1

C1

Reset

Reset

Sync

F2

RESET

HLDA
INTE
WAIT
D
DBIN

INT
HOLD

HOLD

DBIN
WR
BUSEN

SYNC

B
0
1
7

D0
D1

D
D7

SC MEMR
MEMW
IOR
IOW

INTA

DD4 58086
0
1

A
B

1
F

0
1

1
7

7
7

+5

TF
OE

DD5 58086

8
9

A
B

1
F

15

1
15

7
+5

7
TF
OE

R1 10 , 1 10 , t > 1/f
: () .
.
.
()
().
, . ,
.
2:
;
.
(ROM):
1. -,
.
19

2. () ,
. .
.
3. () :
.


1. ,
[] N.
:
n

n-1

2
3

m-1
m

N = n m, n (4, 8, 16); m . N
.
N = 4096
N = 1 4
N = 512 8

.

0
1

CS
OE

D0 D1
OE

Dn

:
= 1, Z .
.
2. t ( t)

OE

CS

20

OE

= 0, ;


CS

t .
t (10 100) .
556, 556:
;
t 10 .;
. . + 5 .

,

5564
256 4

5
512 8

6
2 8

7
2 8

11
256 4

12
1 4

13
1 4

14
2 4

15
2 4

16
8 4

17
512 8

18
2 8

; 3 .
55611 (. 1) 5566 (.2 ):

PROM

D0
0
1
2
3

CS1

Ucc

CS2

GND

1K

0
1

. 1

PROM

16K

D0
0
1

9
10

CS1
CS2
CS3

GND

Ucc

. 2

573 573 ( , ).

,
,
5731
1 8
+ 5, 5, + 12
2
2 8
+5
3
4 16
+5
4
8 8
+5
5735
2 8
+5
6
8 8
+5
7
32 8
+5
9
128 8
+5
5735:

21


0
1

EPROM

16K

9
10

CS
OE
UPR

.
(
+ 5 )

D0
0
1

Ucc
GND

OE = 1, D0 Z-;
OE = 0, D0 Z-.
:
1.
2.

, . : ,
,
. : ,
.
(
), ().
,
.
+ U
R

R 1012 ; C 1 2 ; t 3 4 .
.
.
.
:
1. ;
2. , ;
3. .
:
1. ;
2. .
.
,
.
.
.
.
132 , 541 2, 537 (537) :
22

1. (I 10 );
2. ;
3. .
2 - :

-;

() - .

,
-
5371
1 1

2
4 1
//
3
4 1
//
6
4 1
//
5378
2 8

9
2 8
//
10
2 8
//
13
1 4
//
14
4 1

17
8 8

5373 ( -):

0
1

RAM
4K

D0

10
11
DI
CS
WE

Ucc

W/R

GND

WE ( WE = 0 ; WE = 1 ).
W/ R = 0 , W/ R = 1 .
DI
DO

CS
WE
1

0
0
DI
Z

0
1

DO

53710 ( -):

0
1

RAM
16K

DIO

0
1

9
10

CS
WE
OE

GND

Ucc

DIO .
OE .
DIO

CS
WE
OE
1

0
0

DI

0
1
1
Z

0
1
0
DO

23



. .
, . . .
: AS.
( ).
15 14 13 12 11 10 9 8 7 6 1 0

2 = 64 , 1024 = 1 .
.

16

6
10

AS

AS

CS

M EM W

M E M R CS

A0A9
(18)
DO
8

M EM R

.
8

10

CS
CS
A0A9
(18)
DI
DO

-
DIO
8

15 14 13 12 11 10
9 8 1 0
HEX

0 0 0 0 0
0
0 0 0 0
0000
0 0 0 0 0
0
0 0 0 1
0001
0

0 0 0 0 0
0
1 1 1 1
03FF
0 0 0 0 0
1
0 0 0 0
0400
1

0 0 0 0 0
1
1 1 1 1
07FF
0 0 0 0 1
0
0 0 0 0
0800
2

0 0 0 0 1
0
1 1 1 1
0BFF
,
.
A

A0

A1

A2

3
4

0
0

DC

5
&

6
7

CS0
CS1
CS2
CS3
CS4
CS5
CS6
CS7

24


:
;
.
OE .
1 ( ,
OE ).

DD1

16

ROM

DD3

D0

CS1

CS

AS
CS2

8
DI

DD2

MEMR
OE

ROM
CS

D0

D0
A

DD1

DD2

CS1
CS2

MEMR

. DD1

. DD2

2 . ,
.
1- :

25

DD1
ROM
8

DD3

CS1as

CS1

1
AS

D0
CS

MEMR
DD4
CS2as

DD2
CS2

ROM
CS

D0

CS1as
CS2as

MEMR

CS1

CS2

. DD1

. DD2

2- : OE ( 573) :

DD1

16

ROM
MEMR
CS1

OE

D0

CS

AS

DD2
CS2
MEMR

ROM
CS
OE
A

26

D0


1. -: 11, 41. : D7,
D6,,D1, D0. OE , ( CS = 0)
.
1- : (5372,
N=41).

DD1
0

11

CS

0
1

RAM
4K

10
11
DI
CS
WE

D0

11

0
1

RAM

10
11
DI
CS
WE

Ucc
GND

4K

DD9

DD2
D0

D1

A
B

D0

D7

D7
7

+5

TF

GND

OE

MEMW

MEMR

D0

D1

N = 48. DD9 , .
MEMW = 0 ;
MEMW = 1 DD1 DD8;
MEMR = 0 .
2- : CS .

MEMW

WE

CSas

CSas
1
0
0

MEMW

MEMR

MEMR

WE
1
0
1

CS

&

CS
1
0
0

27

D1

7
Ucc

D0

MEMW

WE

CSas

MEMR

&

CS

DD1
0

0
1

11

10
11

CS

RAM
4K

D0

DI
CS
WE

DD8

DD2
0

0
1

11

10
11
DI
CS
WE

Ucc
GND

RAM
4K

D0

0
1

11

10
11

RAM
4K

D0

DI
CS
WE

Ucc
GND

Ucc
GND

WE

D0 D1

D0

D1 D7

D7

2. -: OE ( ).
. 5378, 9, 10, 17 (N = 48 = 32 .

A11
A13

CS0

DC

3
4
5

&

+5
5

DD2

DD1

15337

CS1

A0

A10

0
1

RAM
16K

DIO

0
1

9
10

CS
WE
OE

Ucc
GND

D0

D7

A0

A10

0
1

RAM
16K

DIO

0
1

D0
D7

9
10

CS
WE
OE

GND

Ucc

MEMW
MEMR

CS0 = 0 0000H 07FFH


CS1 = 0 0800H 0FFFH
CS2 = 0 1000H 17FFH
: 0800H 17FFH


( ), 1
1 .
.
28

1) 15 ( 15 = 0 , 15 = 1 ).

DD1 5735
A0

A10
A15(11)

0
1

EPROM

16K

D0 D0
0
1

9
10
CS
OE
UPR

DD2 57310
A0
A15(11)

D7

Ucc
GND

MEMR

A10

1
DD3
15331

0
1

RAM
16K

DIO

0
1

9
10

CS
WE
OE

GND

D0

D7

Ucc

MEMW

: 0000 07FFH
: 8000H 87FFH
0000
07FF
0800
0FFF

7FFF
8000

87FF
FFFF

2) 11 ( 11 = 0 , 11 = 1 ).
: 0000 07FFH
: 8000H 0FFFH
0000
07FF
0800
0FFF

FFFF

29

-
-.
,
. 8- .
.
.
.
- 3 :
1. ,
2.
3. .
:
1.
) ;
15

15 14 13 12 11 10 9 8 7 6 1 0
7

64

7 6 1 0

256

256

: (IN port OUT port), (port) = 00H FFH.


: MEMR MEMW .
: IOR IOW .
, . .
-.
2 :
: IN port
(A) (port);
: OUT port (port) (A).
2.
)
, . .
. :

15 14 13 12 11 10 9 8 7 6 1 0

: 15 = 0 ;
15 = 1 .

30

0000

32

32

7FFF
8000

FFFF

.
.

-

15

15 14 13 12 11 10 9 8 7 6 1 0


2 :
1) (
256)
00000000 = 00H
00000001 = 01H

11111111 = FFH
(
), . 1110000 - EO 00000000 = OO

15337
A

A0

A1

A2

3
4

3
4

DC

CS00H
CS01H

5
&

CS06H

CS07H

7 6 5 4 3 2 1 0
HEX
0 0 0 0 0
00H
0 0 0 0 1
01H

0 0 1 1 1
07H
2- :

31

15336

0
1

2
2

3
DC

C S00H

4
5

7
8

0
1

2
2

3
DC

5
6
7

8
9

C S91H

: 0099 ( - ).
.
2) ( 0 1).
7 6 5 4 3 2 1 0
HEX
0 0 0 0 0 0 0 1
01H
0 0 0 0 0 0 1 0
02H
0 0 0 0 0 1 0 0
04H
0 0 0 0 1 0 0 0
08H
0 0 0 1 0 0 0 0
10H
0 0 1 0 0 0 0 0
20H
0 1 0 0 0 0 0 0
40H
1 0 0 0 0 0 0 0
80H
, , 1.

0
1

CS01H

CS02H

CS80H

.

(256), .
, = 8.

32

-
RG

DI

D0

CS

Ucc

IOR

GND

IN Port

CS
IOR

, 3
RG

DI
D0

CS

Ucc

IOW

GND

OUT Port

CS

IO W
D0

() .
8- 58082 , 58083
:
DI

D0
0

STB

Ucc

OE

GND

RG

33

: I0 32 , I1 5 .
8 D- ( )
.
STB ( ), D ( STB = 1, DO = DI;
STB = 0, DI).
( = 1, DO = Z; = 0, DO = 1 0).
1
m

: 0,710-19 || 0,921019
DI
STB
D0
1533

153333

I0 20 mA
I1 2 mA

:
DI
0
1

STB=1

RG
D0
0
1

+5
+

STB
1

0
1

OE

34

0 DI
1
0
1
7

RG
D0
0
1

0
1


153333
7
7 DI
0
1
D0

STB
OE

15331


0 1

CS
IOW

0
1

:
01H
80H 7

15331
+5

0
1

153333
DI
0
1

IOR

RG
D0
0
1

7
1

1
15331

0
1

OE

.
15 = 0, .
15 = 1,
35

IOW

0000

32

32

7FFF
8000

FFFF

58082

DIport
IN

0 port
OUT
D0
1

0
IOW .
IOR
0

1
1
RG
. .: STA, LDA, STAX, LDAX, MOV
7

: MEMR , MEMW
1

7
8001H
7

8003H
STB
15337
0
1
0 A
A151
A14 A13 A122 A11 A10 A9 A8 A2 A1 A0 HEX
+5 B
0
1 2 0
0
03 0
0
0 0
0 0 1
8001
1
1
0
0DC 04 0
0
0 0
0 1 1
8003
2
5
DI
3
RG
6
0
1 &
7
1
15

MEMR

D0
0
1

STB
7

CS8001H

OE

CS8003H

36

MEMW

0
1

8001H LDA 8001H; ( A )( 8001H )


8001H
LXI H, 8001H
MOV C, M; ( C ) ( 8001H )
8003H
STA 8003H; ( 8003H ) ( A )
8003H
LXI H, 8003H
MOV M, ; ( 8003H ) ( )

.
. , .
. ( ISR ).
:
- ( -
INT ).
- :
EI .
DI .
- :
1. , .. RESET.
2. .
,
:
1.)
( , .

. . )
2.)
INTA
.
. . .
2
1. (RST N)
2. . CALL addr.
1 INTA . RST N, .
.
RST N

4 3 2 1
+ + 1 1

RST 0
--RST 1

7
1

6
1

5
+

+ + +
0 0 0
0 0 1
37

0
1

--.
RST 7
1 1 1
-- : N 8

RST N

1
+

1
5
0

14

13

12

11

10

, , RST 1, 111001111 =0008

+5
58082
1
1
1
1

1
1
1

DI
0
1
2
3
4
5
6
7
STB
OE

RG
D0
0
1
2
3
4
5
6
7

0
1
2
3
4
5
6
7


, ISR RET,
, . . RET EI.
,
INT, = 1 .

INTA

38

DI

RG
D0

S
1

D
C

INT

INT INTA

OE

+5 B

&
C1

IRQ
I
INT

R1C1 . . . .
. , . .
,
.
. .
:
- ,
, . .
58059 8 ,
.
80:
1. 3 .
2. 2 ,
12
3. .
39

4. .
i 8085 n
I 80C85 A

182185

85.
DIP
:
1. , +5.
2. . , . . 0,5 3
3.
4.
5.
6. , 80, 2 .
X1
X2

CPU

UCC
GND

RESIN

CLK

READY

SOD

SID

S0
S1
I0 / M

TRAP
RST 7.5
RST 6.5
RST 5.5
INTR

ALE
WR
RD
INTA

HOLD
HLDA
AD
RESOUT
0
1

A
8
.
15

X1, X2 . ( ).
RESIN . . .
RESOUT - . . .
READY .
SID . .
SOD . .
TRAP
RST 7.5
RST 6.5
.
RST 5.5
INTR
HOLD

40

AD0AD7 . .
UCC
+5B
GN
0B
D
CLK .
S0
.
S1
I0 / M . ,
I0 / M = 1
I0 / M = 0
ALE .

WR
RD

INTA
HLDA .
A8A15 . .
16 . . . .
8

A8...A15

8 D0D7 DI
8

815
U
07

RG D0
A0...A7

ALE
C

. . , . . . .
+5 B

X1
X1

ZQ

f 1

X2

X1

X2

L C

X2

FCLK = 0.53
F ZQ =16
41

flk

X1

: . : MOV M, B

T1

T2

T3

CLK

A8 A15

AD0-AD7

A
ALE

1 . . . . 815, 0 7 .
. 1. . ALE .
. . 2 3 0 7 .
WR . IO / M . , . . . .
. .
85.


( ISR)
TRAP
1
0024 H
(01)

RST 7.5
2
003C H
(01)
RST 6.5
3
0034 H

RST 5.5
4
002C H
INTR
5
RST N
2 :
- 01
-
. , . .
. . .
TRAP . . . .
. . . .
. . .
.
42

0000

RST 0

0008H

RST 1

001CH

RST 2

0018H

RST 3

0020H

RST 4

0024H

TRAP

0028H

RST 5

002CH

RST 5.5

0030H

RST 6

0034H

RST 6.5

0038H

RST 7

003CH

RST 7.5

TRAP RST ( . . ).

.
SID
SOD
: RIM SIM.

SID

..

0
x


7 6 5
0 1

7 6
1 x

RIM

..

SOD

SI
M

1 6 . . .
43

SIM :
1. : RST 7.5; RST 6.5; RST 5.5.
2. , . RST 7.5.
3. SOD
.

SOD SOE X RST7.5 MSE M7.5 M6.5 M5.5


(1 )

SOD

(1)

RST 7.5 (1)

: . . RST 7.5 RST 6.5, RST


7.5, . . RST 5.5.
MVI A, 00011001 B
SIM
1 SOD:
MVI A, 11000000 B
SIM
RIM .
SID I7.5 I6.5 I5.5 IE M7.5 M6.5

SID

M5.5

(1 )
(1 - )

: SID.
RIM
ANI 10000000 B; 7 SID.

85.
. .:
1. .
2. .
3. , .
+5 B

ZQ1

R1
10K
VD1

X2
READY
R2 4.7k

+ C1

SB1

X1

10mk
44

RESIN
TRAP
RST7.5
RST6.5
RST5.5
INTR
HOLD

CPU

ZQ1 :
FCLK=1/2 fZQ
FZQ=16
R1, C1, VD1 . . . .
T>
SB1 . . .
VD1 R1 .
R2 - . Ready . . .
,
.
HOLD = 0 . . .
:
4 ( )
80 : RD, WR , IO / M

RD WR
1
MEMR 0
1
0

MEMW
IOR
0
IOW
1

IO / M
0
0

1
0

1
1

1533 ( 74ALS ): I 0 0,2 mA


I !10 mkA
155 ( 74 ):

I 0 1,6 mA
I 1 40 mkA
15331

RD

MEMR

WR
IO/
15331

1
1
1

MEMW

:
1. . 0 7 .
.

IOR

45

2. . ,
, . . .
I 02 mA
I 150 mkA
. .
: 153333
22
I 0 20 mA
I 1100 mkA
. .: 15335
DD1
RG

DI
0
1

8
9

15

D0
0
1
..
7

A8
A9
A15

C
OE
0
1

DI
0
1

ALE

DD2
RG
D0
0
1
..
7

A0
A1
A7

C
OE

DD2 . ,
. .
DD1 . , . .
:
. .
:
15336: I 0 20 mA
I 1 100 mkA
15336

0
1

7
RD

A
0
1

EAB
OE

46

B
0
1
..

0
1

. E:
E = 1,
= 0,
Z :
= 1, Z .
.,
,
( . . RD )
2 . . (
)
:
C 150
, :

, 1533:
C = 10 20
= 50

.
244 . 78.
:
1. .
2. .
3. .
4. .
5. .
. .
16 .
.
:
1
2
3 -
7
0

15

8 7

0
. .

2
47

23 1 16 15

Adr

Adr+1

..

Adr+2

..

:
1. . .
2. , .
.
3. , . .
4. . . ( HL ).
5.
SP.
. . , . . ( .
).
) , , .
) .
) .
. . . ;
., . . .
-



R

(R)

RP

( RP)

( )
( HL )
, . .
D8 d8
8 . . ( 1 . )
D16 d8
16 . . ( 2 . )
16 ADR 16 .
PORT

) MOV, MVI, LXI, LDA, STA, LDAX, STAX, LHLG, SHLD


LHLG, SHLD
XCHG ( HL ) ( DE )
MOV R1, R2 ( R1 ) ( R2 )
R1, R2: A, B, C, D, E, H, L, M
7 6 5 4 3 2 1 0
0 1 D D D S S S

48

0111 1101 = 7DH


MOV A, L
( A ) ( L )
000
001 -
010 - D
011 - E
100 - H
101 - L
110 - M
111 A
.
) . . , . . . .

1007
1008
1009
SP

100

XXXX


: LXI SP, 100A H
. :
PUSH RP .
PUSH H ( HL )
PUSH B ( BE )
PUSH D ( DC )
PUSH PSW ( PSW ) = ( A ), ( F )
:
1
1. : ( SP ) ( SP ) 1 : 1009H
2 . ( SP ) ( H ) ( 1009 H ) (
H)
3. : 1008H.
4. . ( SP ) ( L ) ( 1008H ) ( L )
( HL ) = 5522 H
PUSH PSW
SP
( A ) ( F ) = 33H, 02H
1. ( SP ) ( SP ) 1
2. ( SP ) ( A )

1008 22
1009 55
100

(L)
()

1007H
( 1007H ) ( A )

49

3. ( SP ) ( SP ) 1
4. ( SP ) ( F )

SP

1006H
( 1006H) ( F )

1006
1007

02H
33H

(F)
(A)

POP RP 16 . . .
: PUSH H
PUSH PSW
..
POP PSW
POP H
POP PSW
1. . ( F ) ( SP ):
( F ) (1006H)
2. : ( SP) ( SP ) + 1: 1007H
3. . . . :
( ) ( SP ) : ( A ) ( 1007H )
4. . : 1008H
POP PSW
) :
IN PORT ( A ) ( PORT )
OUT PORT ( PORT ) ( A )
2. A ) 8 . ( ADD, ADC, ADI, ACI )
) 8 . ( SUB, SBB, SBI )
) 16 . DAD
.
DAD H ( HL ) ( HL ) + ( HL )
DAD B ( HL ) ( HL ) + ( BC )
DAD D ( HL ) ( HL ) + ( DE )
DAD SP ( HL ) ( HL ) + ( SP )
) ( INTR, INX )
) ( DCR, DCX )
) ( DAA )
3. A ) . :
ANA ANI - .
ORA, ORI . .
CMA
- .
) . c:
RLC, RRC, RAL, RAR
) .
CMP, CPI:
CMP R . .
CMP M .
CPI . .
0, Z = 1
()(R)=
< 0, CY = 1
> 0, Z = 0 , CY = 0
50

) : STC: (CY) 1 CMC: (CY) ( CY )


3 :
) .
) .
) .
2 :
-
- . , .
.

0
0

( )

Z =1
Z=0
CY = 1
CY = 0
P=0
P=1
S=0
S=1

Z
NZ
C
NC
PE
PO
P
M

:
) : JMP ADR; , :
( PC ) ADR
1

PCHL ; ( PC ) ( HL )
) : Jcond ADR; ( cond : JZ, JNZ, JC, JNC, JPE, JPO, JP, JM)
1. , . , ( PC ) ADR;
, : ( PC ) ( PC ) + 3
:
)
)
.

CALL ADR
1. PUSH
PC
2. PC , JMP ADR
ADR 0000.FFFFH
RST N
N = 0, 1, 2, 3, 4, 5, 6, 7
ADR = N * 8 ( )

..
RST 0
0
0000H
RST 1
8
0008H
51

RST 2
RST 3
RST 4
RST 5
RST 6
RST 7

16
24
32
40
48
56

0010H
0018H
0020H
0028H
0030H
0038H

. Ccond ADR ( cond )


1. , : , . .
, ( ( ) ADR )
3. , :
( PC ) ( PC ) + 3
. . :
)
)
. RET
16 . ,
:
1. ( ) ( SP )
2. ( SP ) ( SP ) + 1
3. ( PCH ) ( SP )
4. ( SP ) ( SP ) + 1
. Rcond ( cond - )
1. , (
)
2. , :
( PC ) ( PC ) + 1
5

EI . . ( . . INT)
EI . INTE 1 ( . . )
DI ( . . .,
INT ), INTE 0
NOP ( ) .
.
HLT Z ., . .
.
:

- .

.
,
, . .
( ). . .

52

(), . .
max ,
.
- .
. ( ).
:

:
-
-
, .
, . .
. . , , 32:
ABBA
ABBA _ ACA
MET1
, . . . . .
.
:
1. .
3. ( )
:
1.
2. . :
10 . 12 12
8 . 12Q
16 . 12 ( 0
0)
ASCII ( ) C
3. .

TEMP
4. , . . +, -, /, *, NOT, AND, OR,
, , ; ,
.

.
. .
ORG, END, EQU, SET, DB, DW, DS, MACRO, ENDM, ORG.
< : > ORG
.
ORG 100H
ORG , . 0000
< : > END

EQU
.
CONST EQU 25H
53

MEM EQU 2000H


EQU
SET
CONST SET 25H
..
CONST SET 45H
.
< : > DB
1 . .
TABLE: DB, 01H, 07H, 0ABH
< : > DW
2 2
< : > DS
, (
)
BASE : DS 100
ORG 1000H
Base : DS 100

1000
BASE
100

DELAY . .
.
. .
NUM + EQU 100
ORG 50H
DELAY : MVI C, NUM
LOOP : NOP
DCR C
JNZ LOOP; ( ) = 0
RET; . .
END;
MACRO ENDM . .
, . .
MACRO
..
ENDM
RCHANGE : MACRO R1, R2
MOV A, R1
MOV R1, R2
MOV R2, A
ENDM
( ) ( ) RCHAHGE B, C
XCHANGE: MACRO X1, X2
PUSH X1
PUSH X2
POP X1
POP X2
54

ENDM
( ) ( DE )
XCHANGE B, D

.
2

:
1.
2. ( )
:

1.
2.
3.
4.
5.
6.
7.
8.

.
.
( ) .
.
.
.
.
.

1 ( ).
.
:
1. .
2. ( )
. .
,
.
( ).

.
.

1
55

:
1.
2.
3. .
, 1 . .
.
1 ,
.
.
: 1 . . . 1 ,
. 2 .
7 6 5 4 3 2 1 0
S
S = 0
S = 1

S=
0

PORT
OPORT1 OPORT2
IN IPORT;

ORA A;
JP MET1; MET1, S = 0
OUT OPORT2;
HLT

MET1: OUT OPORT1;

HLT
. . 1 . . .
.

>

56

N = 1256 . .

MVI C, NUMBER;
LOOP: NOP
NOP
DCR
JNZ LOOP; ( ) 0
N = 165536 . . ( BC, DE, HL )

LXI B, NUMBER; . .
LOOP: NOP
NOP . .
1. 0 . , . :
LXI B, NUMBER
LOOP: NOP
NOP
DCX B
MOV A, B
CPI 0
JNZ LOOP; , ( ) 0
MOV A, C
CPI 0
JNZ LOOP; , ( ) 0
( ) = 000000001
( ) = 100000000
100000001

.
.
, .
.
BASE
0
1
.

BASE
IND -
ADR = BASE + IND
R

ADR = BASE + k * IND


57

. 2 :
. POINTER ( PTR )
, . COUNTER

: max 1 .
LENGTH

.
. HL
. BASE
: ( HL )
( BC ) ( LENGTH )
:
(A)
(B)

BASE

(( HL ))
(B)-1

B=
0

( HL )

( HL ) + 1

(A)<
58 (( HL ))

Y=1

LDA LENGTH; .
MOV B, A ;
.
LXI H, BASE ; HL
NEW MAX: MOV A, M
NEXT: DCR B
JZ DONE;
, () = 0
INX H
CMP M
JC NEWMAX; (CY) = 1
JMP NEXT
DONE: HLT;

( )

PRT
PRT1 + 1

COUNT
LXI H, BASE
SHLD PTR
LXI A, NUMBER
STA COUNT
..
LHLD PTR;
LDA COUNT;
MOV B, A

SHLD PTR;
MOV A, B
STA COUNT

1
/#

(t)

D0
0
1

7
8
9

59

DI
0
1

RG

DI
0
1

RG

D0

D0
0
1

0
1
7

0
1
7

BASE XXXX XXXX . .


0000

00

PTR
PTR+1
COUNT

. .

LXI H, BASE
SHLD PTR;
MVI A, LENGTH;
STA COUNT;

CYCLE: LHLD PTR


IN PORT 1; . .
MOV M, A
INX H
IN PORT 2; . .
ANI 00000011 B, . D1, D0
MOV M, A
INX H
SHLD PTR
LDA COUNT
PCR A
STA COUNT
INZ CYCLE
DONE:

( ) .
2 :
1.
2. .
. . . .
. . . .
. . . . .
( ). :
60

MS DOS, WINDOWS .
.
( ) , . .
.
2 :
1 . . . ,
( ) . .
2 . .
. .

.
, . , .
. . .
. ( ) , .
.
273
:
1. . , .
.
2. . .
3. .
4. . .
:
1. . , . .
. :
CALL SUBR
. ( .
CALL ) .
RET ( 2
. )
, . , . . .
. :
1. . ., .
2. .
. .
SUBR: PUSH PSW; ( A, F )
PUSH B;
( , )

POP B;
( B, C )
POP PSW; ( , F )
RET
SUBR1: .
DCR A
RZ;
, ( ) = 0
INI B
POP D
POP H

RET
SUBR1:
DCR A
61

JZ EXIT;
INX B
EXIT: POP D
POP H
RET

, ( ) = 0

. , .
:
1. . ., . . . , .
2. ., . . .
3. . .
. :
N
1
0
+

...

...

...

Y
; . 2 ( ) 8 * N
; . : , . 1
; HL . 2
; . N
; . : , .
; CY
;
, ., ., . .
. .
:
1. . ( . ).
. .
. ( )
.
2. , . .
.
. .
3. . . .
, . . ., .
. .
LXI H, PARAM1
PUSH H
LXI H, PARAM2
PUSH H
LXI H, PARAM3
PUSH H
CALL SUBR

62

SP

ADR
PARAM3


ADR

ADRRET
ADRRET+1

PARAM2
PARAM1
SUBR : POP H
SHLD ADRRET
POP H; ( HL ) PARAM3
POP H;
( DE ) PARAM2
POP D;
( BC ) PARAM1

LHLD ADRRET
PCHL; .
. .

.
,
. ., . . , . :

n/n-1

n/n-3

n/n-2

n/n-4

n/n-5

1
n/n-6

- 2

.
. . , . . .
1. . 16 . . .

0
1
2

Adr 0

Adr 0

Adr 1

Adr 1

Adr 2

Adr 2

0
NULL
1
NULL
2
NULL

. :
NUUL = 00000000
63

..

-
1

( KEY BORD )
SB1

DI
0

SB2

RG

SB3
2

, . .
SB

/
1
00H
SUBRO
2
01H
SUBR1
..
1. . . ( ) ,
/ .
IN KEYBORD
CPI 00H; SB1
SZ SUBR 0;
CPI 01H; SB2
CZ SUBR 1;

.
2.. . :
SUBR 0

TABLE
64

SUBR 1
SUBR 2

IN KEYBORD
ADD A;
MOV E, A
MVI D, 0 ; ( DE ) ( A )
LXI H, TABLE ; ( HL ) . .
DAD D ; ( HL ) ( HL ) + ( DE )
MOV D, M ; ( D ) . .
INX H
MOV E, M ; ( E ) . .
XCHG ; ( DE ) ( HL )
PCHL ; /
:
a
f

b
g

c
d


HEX
7 6 5 4 3 2 1 0
0 0 1 1 1 1 1 1 3F
0
0 0 0 0 0 1 1 0 06
1
...................................................................
0 1 1 1 1 1 1 1 7F
8
1 0 0 0 0 0 0 0 80
,
00000000 = 00
; /
; 7
; . . . .
; . . 7 .
CONVERT: MOV E, A
MVI D, 0; ( DE ) ( A )
LXI H, TABLECOD
DAD D ; ( HD ) ( HL ) + ( DE )
MOV A, M; .
RET
; . 7 .
65

TABLECOD ; DB 3FH; 0
DB 06H; 1

DB 71H; F
2. :
Y = X2 x = 0, 1, , 10
X
Y
DEC HEX DEC HEX
0
00
0
00
1
01
1
01
2
02
4
04
3
03
9
09
4
04
16
10
5
05
25
19
6
06
36
24
7
07
49
31
8
08
64
40
9
09
81
51
10
0A
100
64
; / Y = X2
; . : .
; . : .
KVADRAT: MVI B, 0; ( BC )
LXI H, TABLE
DAD ; ( HL ) ( HL ) + ( BC )
MOV E, M ;
RET
;
TABLE: DB 00H, 01H, 04H
DB 09H, 10H, 19H
DB 24H, 31H, 40H
DB 51H, 64H
4. :
. . . . / , .
. . CALL Adr
JMP Adr
.
CALL
SUBR 1

CALL
SUBR 2

.
SUBR 1

SUBR 1

JMP
SUBR 1A

JMP
SUBR 2B

SUBR 1A

SUBR 2A

.
:
1.
66

2.
:
-
-
:
-
- ( )
:
- c ( 3 )
- ( )
1, 2, 3, . .

.
7

.
:
[ A ] = [ A ]
. .
: [ A ] = [ A ] + 1
LDA MEM ; MEM .
CMA
STA MEM ; .
INR A
STA MEM ; .
00 = 0
FFH = 255

15

31

Adr

Adr+1

24

23

16

15

3
2
1
0
ADD
SUB
CY
1

- 1 .
- 2 .
67

ADC
:
; / 2
; 8 * N
; N
; . : . , . . . 1
; . HL . . 2
; . N
; . . . .
; CY
ADD8N: MOV D, E; .
PUSH B; 1
XRA A; ( CY ) 0
;
CYCLE : LDAX B ; ( A )
( SBB M ) ADC M ; ( )
STAX B ;
INX B
INX H
DCR E
JNZ CYCLE ; , ( ) 0
;
MOV E, D
POP B
RET
:
1010 -
* 1101 -
1010 -
0000
1010
1010 _
10000010 - ( )
:
8 * 8 = 16
7 * 16 = 24
16 * 16 = 32

.
.
00000100 = 4

00001000 = 8

00010000 = 16
68

2: A. = . * 2N
N
,
00001000 = 8
00000100 = 4
00000010 = 2
. . 2: . = / 2N
00001001 = 9

=*6=4*+2*
= 10 * = 8 * + 2 *
= 6,5 * = 4 * + 2 * + / 2
: . * 6,5
IPORT
SAVE .
IN IPORT ; ( A ) x
MOV C, A ; ( C ) X
RLC
;(A)=2*x
MOV B, A ; ( B ) 2 * x
RLC
;(A)=4*x
ADD B
;(A)=(A)+(B)=6*x
MOV B, A ; ( B ) = 6 * x
ORA A
; ( CY ) 0
MOV A, C ; ( A ) ( C ) = x
RAR
; ( ) = / 2
ADD B
; ( A ) ( A ) + ( B ) = 6.5 * x
STA SAVE ;
255 !
7 6 5 4 3 2 1 0
1 0 0 0 1 0 0 1
.

099

15

0 1 0 0 0 1 0 1
4

1 0 0 0 1 0 0 1
8

Adr

1000

1001

Adr + 1

0100

0101

,
.

.

0 0 0 0 1 0 0 1
69

. . . .
.
. . .

0 0 0 0 1 0 0 1

. .

9
0 0 0 0 1 0 0 0
1

. .

8
1 0 0 0 1 0 0 1
. .

. .

. .

0
1

. .

1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 0 0 1 1 0 0 0 1
. .
9

ADD .
DAA . .

; / .
; . : . . . . 1
; . HL . . . 2
; . N
; . : .
; CY
70

. .
1

ADD10N: MOV D, E
PUSH B
XRA A
; D
CYCLE: LDAX B
ADC M ;
DAA ;
STAX B
INX B
INX H
;
DCR E
JNZ CYCLE ; ( ) 0
;
MOV E, D
POP B
RET
.
. . .
.
. ,
, .

.
. 2 . .
1 0 0 1 1 0 0 1
. .
9

. .
9

0 1 0 1 0 1 0 1

PR 102
. .
. .
10 * . .
10 * . . + . .

; . : . . .
; . : . . .
PR 102 : ; . .
MOV B, A ; . .
71

ANI OFH ; . .
MOV C, A ;
MOV A, B ;
ANI OFOH ; . .
RRC ; . . * 10
MOV B, A ; . . . * 8
RRC
RRC ; . . * 2
ADD B ; . . * 10
ADD C ; . .
RET
. . 0 0 0 0

0 0 0 0

RRC
. . * 8
RRC
RRC
. . + 2

RLC
RLC
RLC
. . * 8

1 .
1 1 1 1 1 1 1 1
0 0 1 1

= FF

0 1 0 1

0 1 0 1

5
; . 2 : . 5
; . : . HL 3 . .
PR810 : LXI H, O
MVI B, 8 ;
;
CYCLE: MOV A, C
RLC
MOV C, A
; . .
MOV A, L
ADC L
DAA
MOV L, A
MOV A, H
ADC H
DAA
MOV H, A
;
DCR CYCLE
RET

!
7 6 5 4 3 2 1 0
S
S = 0 .
72

S = 1 .
1) . , .
0 1 1 1 1 1 1 1 = + 127
1 1 1 1 1 1 1 1 = - 127
2 : . .
2)
S
.
S = 0 . .
S = 1 . =
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1 .
1 0 1 0 1 0 1 0
1 1 0 1 0 1 0 1 .
2 .
3)
S
.
S = 0 . . .
S = 1 [ A ] = [ A.] + 1 = [ A ] + 1
. . ; .
. ( )
[ A ] = [ A ] + 1 = [ A ] + 1
[ A ] = [ [ A ]Adop 1 ] = [ A ] + 1
-1=1 0 0 0

0 1 1 1 1 1
+
0 1 1 1 1 1
1 1 1 1 1 1

0 0 0 1 .
1 0
1
1 1 =
1 1 = FFH

/ . . .
; . : . .
73

; . : . .
DOP : MOV C, A
RLC
JC PREOBR ; S = 1
MOV A, C
RET
PREOBR : MOV A, C
CMA ;
INR A ; ( A ) ( A ) + 1
RET
1
IPORT 1

X(t)

15

2
IPORT 2

S
. .

. .

; / . . .
; . : IPORT 1 . ., IPORT 2 . .
; . HL . . .

POP 2
. .
. .

DOP 2 : IN IPORT 2: . .
74

RLC
JC PREOBR ; S = 1
IN IPORT 1 ; . .
MOV M, A
INX H
IN IPORT 2 ; . .
MOV M, A
RET
PREOBR: IN IPORT 1 : . .
CMA
ADI 1
MOV M, A ;
IN IPORT 2 ; . .
CMA
ACI O
ORI 80 ; S = 1
MOV M, A
RET
1) ,
1

PORT STAS

D7

D7 = 1
D7 = 0
MAIN

PORT
STAS

D7 = 1

DOP 2

()=0

75

. .
BASE

.
S

. .

MAIN : LXI H, BASE


MVI C, 100 ;
WAIT : IN PORTSTAS ;
ANI 1000 0000 B ; D7
JZ WAIT ;
CALL DOP 2 ;
DCR C ;
JNZ WAIT ; , ( ) 0
HLT ;
2) .

INT
RST 7 . : 0038 H
ORG 0000H
JMP MAIN ; .
ORG 0038H ;
CALL DOP 2
DCR E
JNZ NEXT ; ( ) 0
JMP EXIT
NEXT : EI
RET
ORG 0100H
MAIN : LXI H, BASE
MVI E, 100
EI ;
WAIT : JMP WAIT ;
EXIT
7 6 : 5HLT
4 3 2 1 0
1)
, - .
6 5 4 3 2 1 0 ( )
1. 7
2)
2. ( )
-

7 6 5 4 3 2 1 0
3) ,

76
-

> 0
< 1, > 0
( > 1 )
: X = X * RM
: , , R .
. ..
80, 85 :
1
= 2 3
7 6 5 4 3 2 1 0
Sm
.

+ 27 = + 128

- 64

63
- 27 = - 128

0
= + 64
15

127
7

0
. .

. .

. . ( . . 1 )


mx

z = x y = x 2 y 2 my = x y 2 mx + my
x
x
z = = x 2 mx / y 2 my =
2 mx my
y
y

77

MULFL

:
ADDFL


58055 (i8285A)
125 .

78

PIO

PA

0
1

0
1

A0
A1

PB
0
1

CS

RD
WR
RESET

PC
0
1

Ucc
GND

8
D0
D7

A1

PCL

PCH

A0
CS
RD
WD
RESET

PA

PB

(PA0 PA7)

(PC0 PC3)

(PC4 PC7)

(PB0 PB7)

, , . . .
3 .
0, 1 .
RESET .
, . RESET
0.
3- :
0 - . - ;
1 -. , ;
2 -. .
.
, .
2 :
79

1.
.
.
D

. 0
. 1
. 20
0
10
1
(70)

1
0

1
0

(30)

(70)

11

(74)
1

MVI A,
OUT
: : ,
, . . , . . . 0.

IOR

4
1

PIO

PA

0
1

0
1

A0
A1

PB
0
1

CS

RD
WR
RESET

PC
0
1

Reset
IOW

A0
0
0
1
1

A1
0
1
0
1

Ucc
GND

CS = 1 Z ;
80

= 91

CS = 0 .
7 6 5 4 3 2 1 0
1 0 0

04
1 0 1

05
1 1 0

06
1 1 1

07
MVI A, 91H
OUT 07H
;
IN 04H
0

;
0
OUT 05H
0
2. 0
1. .
1
1
10
D
D
D
D
D
D 0D
D
7
6
5
4
3
2
1
0
1
0
1
0

0
1
10
1
0
1
0
1
0
: 1 2- 1
0
: 0000 0101 = 05
1
MVI A, 05H
2
OUT
3
4

5
6
8
8
8

0
11
0
1

7
7

: 1 2-
IN PA
ORI 0000 0100B
81

OUT PA
: 3-
IN PC
XRI 0000 0100B
OUT PC
:
I0 2
I1 40

58051

. (
) .

. .

()
[/]. = /.
, = 1/V , V , = 1/f ,
f
.

D0

D1

D2

D3

D4

D5

:
82

D6

D7

1. 5- ( ). 25 = 32 .
3 : , .
2. ASCII 7-,
7 : 27 = 128. 8-
. .
3. 8 ( 7) .
,
: ()
, . 90 %
.
2 : .

. .

-
-
( 1 2). -. ,
. . . .
- ( ). , ,
.
D0

D1

D2

D3

D4

D5

D6

D7

D8

:
1. .
2. .
:
1. .
2. .
.
(.
)
. ,
.

83

1-

2-

1-

22-

: .
:
1. . .. ,
.
2. .
( ).

58051
.
(USART) - -.
.
. , 28 ,
.
D

SIO

0
1

TxD
TxC
T x RDY

TxE
RxD

CS

R x RDY

RxC

CLK

SYNDET

RD
WR
RESET

DSR
DTR
RTS

Ucc
GND

CTS

C/S (): C/S = 1 ;


C/S = 0 .
CS : CS = 1 ; CS = 0 Z-.

84


8
D0
D7
C/ D

CS
RWRD
CLK
RESET

DTR
DCTSS R
RTS

-
.

-
.

TxD
T x RDY
TxE
TxC
RxD
R x RDY
SYNDET
R xC

RD
WR
CLK ( ) 2
RESET ( . .
)
T x D
T x RDY , (T x RDY = 1 )
T x E , . .
T x C ,
R x D
R x RDY (R x RDY = 1
)
R x C ,
SYNDET ,

51
.
2- : .
,
, . . 1 ().
.
2 : DAN.
C/ D = 1
C/ D = 0 DAN
85

1-

OUT
OUT DAN
IN DAN

2-


1
0
D7
D6

1
1,5
2 0
0
1
10
1
0
11 -

TxD
TxC

1
0
D5

D4

D3

D2

D1

D0
1
0
1:1
0
0 1
0 1:161
5 1
1
1
1:64

0
6 0
1
7 1
1
8

V f [/]
f

f , .
86

1:1, (f = f);
1:16, f = f/16;
1: 64, f = f/64.
1:16 1:64.

1
0

0
0
5
1
0
6 0
1
7 1
1
8

1 . .
0 . .
1
0
1
0


D1 = 1, DTR = 0. ( ).
D7

D6

D5

D4

D3

D2

1
0

D1

D0
1
00
1- - =0 0=1

1 ()
0

1
0

1- =0 0=1
1
0

1- . - 0
0

: :
: 0100 0000 = 40
MVI A, 40H
OUT
: : 2 -,
, 8 , = 16:
: 1111 1110 = FEH
MVI A, FEH
OUT
87

: : 1
7EH = 0111 1110, , , 8 :
: 1011 1100 =
MVI A,
OUT
MVI A, 7
OUT
: ,
;
: IN .

DSR
SYNDET
FE (1 )

OE (1 )

TxRDY ( )
RxRDY ( )

TxE ( , )
PE (1 )

FE, OE, PE .
:
BASE::
88

WAIT: IN
RRC
JNC WAIT
LDA BASE
OUT DAN

;
;
;
; ()
;

:
MEM:
WAIT: IN
RRC
RRC
JNC WAIT
IN DAN
;
STA MEM
;
D

D0

D7

SIO

0
1

f2
IOR
IOW

RESET

..

TxC
T x RDY

TxE

RxD

CS

&

TxD

R x RDY

CLK

RxC

RD

SYNDET

WR

DSR

RESET

DTR

Ucc
GND

RTS
CTS

7 6 A5 A4 A3 A2 A1 A0
HEX
1 1 1 1 1 1 1 1
FF

1 1 1 1 1 1 1 0
FE
DAN
V : 110, 150, 300, 600, 1200, 2400, 4800, 9600, 19200 [/].
= 1:16, V = 1200 [/], fC = 1200 16 = 19200 .
fCLK = 2, = 2000000/19200 = 104,1
.
, ( )
. V = 9600 [/].
,
.
(

).

89

58053 (i8253)

8
D0

OUT 0

D7

0
(0)

CLK 0
GATE 0
OUT 1

A0
A1
CS
RD

1
(1)

2
(2)

WR

CLK 1
GATE 1
OUT 2
CLK 2
GATE 2

24

13

12

16 . +5 . .
, -. OUT.
CLK
GATE
.
, .
CLK0
GATE0

D
D0

D7

0
1
7
OUT0

A0
A1
CS

1
3

PT

IOR

OUT1

RD
WR

OUT2

IO W

CLK0
GATE0

CLK1
GATE1
CLK2
GATE2

fCLK = 0 2

6 :
90

0 ;
1 ();
2 ;
3 ();
4 - ;
5 - .
, :
1
0
0
1
1

0
0
1
0
1

0
1
2



D
D
D
0 7
6
5
1
2
0
0
1
10

1.
0.
.
1 . 0
0
1
1 0
1
0
11

0
0
0
1

1
10
0
1
1

0

00

1
0
1
0
:
1.0

.1 (
);
.2
.3
(N).
.4
.5

7
0
0
0
0

6
0
0
0
0

A5
0
0
0
0

A4 A3
0 0
0 0
0 0
0 0

A2
0
1
1
1

A1
0
0
1
1

A0
1
1
0
1

HEX
04
05
06
07

3-

.
0
1
2

1: 0 1, . 13, .
: 0001 0010 = 12
MVI A, 12H
OUT 07H
MVI A, 13H
OUT 04H
2: , 1513.
91

: 0011 0010 = 32
MVI A, 32H
OUT 07H
MVI A, 13H
OUT 04H
MVI A, 15H
OUT 04H
3: :
0, 5, 1513
1, 1, 06
2, 2, 0

0: 0011 1010 = 3
1: 0101 0010 = 52
3: 1001 0000 = 90
MVI A, 3H
OUT 07H
MVI A, 52H
OUT 07H
MVI A, 90H
OUT 07H
MVI A, 13H
OUT 04H
MVI A, 15H
OUT 04H
MVI A, 06H
OUT 05H
MVI A, 0H
OUT 06H

, . . :
1.
2- :
) CLK
) GATE = 0.
2.
( )
IN CT(0, 1, 2), (0, 1, 2)
, . , .
:
D4, D5 = 1, 0.

fCLK

RG

D0
0
1
2

&

CLK0

OUT0

GATE0

PORT_OTKL

92

MVI A, 00H
OUT PORT_OTKL
IN CT0
MOV C, A
IN CT0
MOV B, A
MVI A, 01H
OUT PORT_OTKL

; D0 = 0
;
; .
; .
; 0

, D4, D5 = 0,
.
: 0, 32 = 0011 0010.
: 0000 0010 = 02
MVI A, 02H
OUT 07H
;
IN 04H
MOV C, A
; .
IN 04H
MOV B, A
; .
:
0
TCLK

CLK
WR

GATE

OUT
t

t = n TCLK
TCLK = 1/fCLK
OUT = 0. OUT = 1.
CLK, 0 OUT = 1.
1
OUT
t

t = n TCLK
01 GATE.
OUT = 1.
2

93

CLK
WR

GATE

0
4

OUT
T

= n TCLK
f = fCLK /n
3
U

t
t

t = t = /2
, , ,
. ,
.

94

TCLK
1)
CLK
n=4
WR

OUT

0
4

TCLK

2)

CLK
n=5
WR

OUT

0
5

4
TCLK

CLK
WR

n=4

GATE=1
4

OUT
t

t = n TCLK
t = TCLK

95

5 () GATE

CLK
n=4

WR

GATE

0
4

OUT
t



:



U(t)

y(t)

x(t)

x(t)
x(t)
U(t)
() . ( ).
:
1.
2. ()
U(t)
.

U(t)
.

(- )
.
(- ) .
96

.
1(t)

.
y2(t)

y1(t)

2(t)

2
.

Y1(t)

X2(t)

Y2(t)

X1(t)


() (
(, , )
( , , ,
):
1.
2.
3.
4.

.
,
- .
+5
R

IPORT
U

DI
0
1
2
3
4
5
6
7

DO
RG

0
1

OPROS

D1

D1 =
1?

97

OPROS: IN IPORT
ANI 0000 0010B ; D1
JZ M2
; D1 = 0
M1:
; D1 = 1

M2:
( )
, .

U

L.

H.


IPORT

+5
R
K

DI
0
1
2
3
4
5
6
7

DO
0
1

RG

WAIT_H

D2

D2 =
1?

98

CALL WAIT_H
WAIT_H: IN IPORT
ANI 0000 0100B ; D2
JZ WAIT_H
;
RET
;
WAIT_L

D2

D2 =
0?

WAIT_L: IN IPORT
ANI 0000 0100B ; D2
JZ WAIT_L
;
RET
;


( )
U(t)

+5
R

U(t)

:
1. RS
R1 4,7 K

SB1

S
R2 4,7 K
+5B

2. :
) .
99

: 20 30 ,
10 , 2 .

IPORT

+5
R

DI
0
1
2
3
4
5
6
7

DO
RG

0
1

) ,
.
DEBOUNCE

. ?

IPORT

+5

t > t

DI
0
1
2
3
4
5
6
7

DO
RG

0
1

WAIT_L: IN IPORT
ANI 0000 0010B
JNZ WAIT_L
; , D1 = 1
CALL DELAY
; / t
RET

OPORT

DI

D0
0
1
2
RG 3
4
5
6
7

(
)

:
1]

100

()

VKL

OTKL

VKL: MVI A, 01H


OUT OPORT ; D0 = 1
OTKL: MVI A, 00H
OUT OPORT ; D0 = 0
OTKL: XRA A
; ()
OUT OPORT ; D0 = 0
2] ( ) (. )



OPORT

1)

DI

DO

RG

DI

DO

RG

IPORT

2) ,
.

RG

D0
0
1
2
3

U1 ()
U2 ()

XRA A
OUT OPORT ;
STA MEM
; MEM

LDA MEM
;
ORI 0000 0001B ; D0 = 1
OUT OPORT ;
STA MEM

101

LDA MEM
ORI 0000 0100B ; D2 = 1
OUT OPORT
;
STA MEM

LDA MEM
ANI 1111 1110 ; D0 = 0
OUT OPORT
;
STA MEM
; ( D2)
LDA MEM
XRI 0000 0100 ; D2 D2
OUT OPORT
STA MEM
3) 55

PIO

PA
0
1
2
3

U1 ()
U2 ()

;
XRA A
OUT PA ;
;
IN PA
;
ORI 0000 0010B ; D1 = 1
OUT PA
2]
U(t)

U(t)
RG
t

XRA A
OUT OPORT
MVI A, 02H
OUT OPORT
CALL DELAY
XRA A
OUT OPORT

t
t

; D1 = 0
; D1 = 1
; t
; D1 = 0

102

D0
0
1
2
3

U(t)

t = t = T/2

MEANDER: MVI A, 02H


OUT OPORT
CALL DELAY
XRA A
OUT OPORT
CALL DELAY
JMP MEANDER
MEANDER: XRI 02H
OUT OPORT
CALL DELAY
JMP MEANDER


1)
DELAY: MVI C, 10
LOOP: NOP
DCR C
JNZ LOOP
RET
: .
: .
, .
.
2) ().
: 10 . 182185,
58053.

103

OUT0

fCLK = 2
TCLK = 0,5

t
D

PT

CPU

0
1
7

RST5,5

A0
A1
CS

1
2

OUT0

CLK

RD
WR
GATE0
CLK0

OPORT

DI
RG
A3

1
IOW

C
OE

D0
0
1
2
3

t = n TCLK
n = 10 /5 = 20103 = 420

: 0 04, 1 05, 2 06, 07


: 0000 1000 = 08
: 0011 0010 = 32
MVI A, 32H
OUT 07H
;
MVI A, 20H
OUT 04H
; . 0
MVI A, 4H
OUT 04H
; . 0
MVI A, 01H
OUT 08H
; 1 D0
EI
;
MVI A, 0EH
SIM
; () , . .

;RST 5.5
ORG 002CH ; RST 5.5
MVI A, 00H
OUT 08H
; 0 D0
RET


:
104

1. (), ,
, .
2. , ,
.
1): 307(, . , ), (, . , )
I 20
U = 13
58082 , 58083
I1 1
I0 32
+ 5 - U
R1 =
150
I
+5
R1
DO
0
1
2
3

RG

0
1

VD1

153333 (23)
I0 20
58055
I1 2
I0 40
:
1

1553 (6)
I 40

1554

+5
R1
PIO

PA
0
1
2

PB
0
1
2
3

PIO

1
0

1
0

PA
0
1
2
3

1
+5
1

VD1
R2
VD2

+5
R4
VD1
R5
VT1

105

+ 5 - U
, . . I = I
I
U - U
R3 =
I
1
U 2,4
U = 0,7
R4 =

Ik

: 9, 10, 22, 32

()

U = 6; 12; 15; 24
I =
R =
RG

DO
0
1
2
3

U
e

K1
VD1
VT1

R1

105, 503
VD
():

RG

+U
DO
0
1
2
3

BA1

&
R1

VT1

U1

R = 48
106

= 0,5; 1; 2;
U = 220
U = 380

EL
RG

D0
0
1
2
3

R1

Uc

VS

:
1.
TV
Uc

-
2. :
I

I = 1520
I = 50200
103(, , ) ,
. .
I

U
U

+5
R
V1

EL
U

107

+5
R
EL

V1

202
210

+5
R

EL

V1
1

VS1

:
+5
R1

EL

V1

VS1

V2
R2
+5

2) :
I
U

519. 10141(1, 2)
, : 1;
3; 10; 20

: 4; 6; 8

U = 100,
3- , :

108

536.301061(2, 1, 2)
, : 10;
20; 40; 80

U
2
EL

KM

: 4; 6; 8;
10; 12

2
EK

HL



. .
2:
1. , n
2. t, (
).

5721
5723
11071
11072
11081
11082
11131

n
12
8
6
8
10(8)
12
10

t,
110150
7,5
0,1
0,1
0,9(0,7)
2,0
30

2 :
1) ;
2) ;
58080: fT = 2 , = 0,5 , fK = 35
, :
1. (Start, ST)
2. (Data Ready, DR)
3. (Data Output, DO)
. .
(Output Enable, OE).
(CLK).
AI .

109

AI
ST

D0
0
1
2
^/#
9

OE

DR

CLK

CLK
a

b
c

ST
DR
t

DO

a
b
b

d


1) n n
8

IOW
IOR
DA

S E L 1

AI
1

ST

OE
DO

SEL2

SEL1
SEL2
: OUT PORT1

PORT1

ST

110

: IN PORT2

PORT2

DO

:
OUT PORT1 ;
IN PORT2
;
.
2) n < n 2 ;
. , . .

RG

IOW
IOR
S E L 1

DA

DI

S E L 2

D0

AI

ST

OE

OE

DO

RG
DI

D0

SEL3

OE

OUT PORT1 ;
IN PORT2 ; . .
IN PORT3 ; . .
11081:
AI

GA
GD
ST
ERD ^/#
SE10/8

D0
0
1
2

9
DR

U1 = +5 , U2 = 5,2 .
AI
GA
GD
ST
111

8
.

ERD
SE10/ 8 0 8-
5,2 10-

DR
0

CLK
ST
DR
t

DO

8-
11081
DD1
15337

A0

A1

A2

1
2

A3

0
0

0
0

0
0

SEL81H

DD2.2
15331

5
&

6
7

7 6 A5 A4 A3 A2 A1 A0
1
1

IOR

DC

SEL80H

0
0

0
1

0
0

GA
GD
ST
ERD ^/#
SE10/8

A4
A7

IOW

DD2.1

AI

0
1

HEX

80
81

DD2.1
DD2.2
OUT 80H;
IN 81H;

112

D0
0
1
2

9
DR

10-
DD4

DA1 11081
DD1
15337

DD2.1

IO W

A0

A1

A2

A3

DC

5
&

SEL 81H

I O R

3
4

A4
A7

DI

SE10/8

DR

-5,2

RG

0
1

7
+5

1
SEL82H

D0

GA
1
GD

ST
7
ERD ^/# 8

SEL 80H

AI

D0
0

7
Ucc

OE

GND

DD5

DD2.3

DI

0
1

+5

OE

RG

D0
0
7
Ucc
GND

DD1: 15337
D2: 11081
DD2: 15331
DD4: 153333 .
DD5: 153333 .
OUT 80H ;
IN 81H
; .
MOV C, A
IN 82H
; .
ANI 0000 0011 ; D1, D0
MOV B, A ;


.
DR (1 ).
1. .
2. DR.
1) :
DR, .
ADCONV

113

11131:
AI

D0
0
1
2

GA
GD
^/#

/
+5

U1

15

U2

DR

/ t 2 .
0

CLK
B/

DO

ADCONV: MVI A, 01H


OUT 80H; D0 1
XRA A
OUT 80H; D0 0 ( )
TEST: IN 82H
ANI 1000 0000B; D7
JNZ TEST; , D7 = 1
IN 81H; .
MOV C, A
IN 82H; .
ANI 0000 0011B; D1, D0
MOV B, A;
DD4

D0

DD2
15332

A
AI

IO W

D0
0
1

^/# 7
8
9
DR

DI

0
1

7
+5

DD1

SEL80H

A0

A1

A2

A3

3
4

A4
A7

DC

5
&

RG

SEL82H

D7

Ucc

OE

GND

DD5
DD3.1

SEL 81H
I O R

D0 D0
0

DI

0
1

1
DD3.2

+5

OE

RG

D0
0
7
Ucc
GND

153333

114

D0

.
D1

1]
DO
0
1
2

7
8
9

U = 10,24 , .
U = 5,12 , .
: 210 = 1024
10,24
U =
= 10 .
1024
28 = 256 U = 28 10 = 2,56 , . . 4 .
2]
DO
0
1
2

7
8
9

U
t

U = 22 U = 4 10 = 40 .
, 4 U.
DO
0
1
2

7
8
9

D0

5
6
7
+5

C
OE

RG

D0
0
1
2
3

fCLK = 2
TCLK = 0,5

ADCONV: MVI A, 01H


OUT 80H
XRA A
OUT 80H
;
CALL DELAY ; 30
IN 81H
;
RET
2) .
, ,
.

115

DR

INT

INT
DR

()

. .


2 :
1. (n)
2. (t, )
.

116

U
()

t
U

:

5721
5722
5941
11081
11181
11182

n
10
12
12
12
8
10

t,
5
15
3,5
0,4
0,02
0,08

,
; , . . t
.

8
4

12

5721 10- :

117

DD3

DD1
15337
A0

A1

A2

A3

DC

DD4
DI

D0

RG

0
1

SEL82H

5
&

OE

IO W

D0
0
1

DI
0
1

IOC
#/^

SEL 81H

A4
A7

RG

0
1

IO W
SEL 80H

DI

DA1

DD2

OE

7
8
9

I1

I2

D0
0
1

DA2

DA2
DD3 . ( 80)
DD4 . ( 81)
( 82).
DACONV /
LXI H, DATA
CALL DACONV
DACONC: MVI A, 01H
OUT 82H
MOV A, M
OUT 80H
INX H
MOV A, M
OUT 81H
XRA A
OUT 82H
RET

;
; .
; .
; .
; .
; D0 0
;


.
: ( )
( )
.
:
1.
2. ()
1) :
118

, ,
.
,
.
.
:


: .
2) (),
:
1

: .
:


:
1.
2.


()

1)

y1

yn

y1

yn

119

:


: .
2)
y1

yn

: .
: .
5902(3, 4, , 8) -.
5906

()

x1
x2

x8
A
0
1
2

SW

U1 = +15
U2 = 15
U = 010
U = 5+5
= 0 (r = 1012 , r 1012 ).
2 1 0
0 0 0
0 0 1

1 1 1

y = x1
y = x2

y = x8

120

.
.
( ).
.
: , .
: .
a
f

g b

e d c h
321(, , )
324(, , )
333(, , )
339(, , )
:
;
.
A
VD
K
a

b
,
()

()
0

:
1.
I.20
I.300 ( t10 , Q10)
2. .
U =23,5
:
1. ( )
5141 ( ) 5142 ( ).
KP5141
R
a
a
0
b
b
1
c
c
2
d
d

x/y
3
e
e

f
f
1 -
E
g
g
R1-R7 ,
0
R1-R7 = 110330 .
121

HG1

KP5142
a
0
b
1
c
2
d
x/y
3
e
f
E
g

a
b
c
d
e
f
g
0

339

2.
.
a
f

g b
1
0 -

e d c h
D7

D6

D5

D4

D3

D2

D1

D0

7 6 5 4 3 2 1 0
0
0
0
0
0
1
1
0
06
1
0
1
0
1
1
0
1
1
5
2
1

80

,
.
;
;
;
5B
HG1
0
5B
CROSSCOD: MOV C,A
339A
0
1
MVI B,00h

1
LXI2 H,TABLECOD1
RGDAD B
(HL) (HL)+(BC)
3
5 B
MOV

A,M

RET
7
1

TABLECOD

DB 3Fh
DB 06h

0
1559
1

DB 71h
0
0
1
2
RG
3

F
+5
HG1
339

R1
1
1

R8 122

1553

.
1.
2. ()
.
.
:
1.
2. .

4 3 2 1
OPORT1
RG

OPORT2
RG

D0
0
1
2
3
4
5
6
D0
7
0
1
2
3
4
5
6
7

0
1
2
3

b
x/y

HG1

1
b
x/y
2

3
g
0

1
b
x/y
2

3
g
0
1
2
3

HG2

HG3

b
x/y

HG4

DATA

123

1
2

DISPLAY
DISPLAY

LXI D,DATA

() 1, 2
HG1, HG2

LDAX D
OUT OPORT1
INX D
LDAX D
OUT OPORT2
RET

() 3, 4
HG3, HG4

OPORT1
RG

D0
0
1
2
3
4
5
6
7

HG1

HG2

OPORT4
RG

D0
0
1
2
3
4
5
6
7

HG3

HG4

OPORT1: HG1
OPORT2: HG2
OPORT3: HG3
OPORT4: HG4

1
2
DATA

124 4

DISPLAY

LXI D,DATA
LDAX D
CALL CROSSCODE
OUT OPORT1
INX D
LDAX D
CALL CROSSCODE
OUT OPORT2

OUT OPORT4
RET


() 1

HG1
2

:
1.
2.
:
1. :
I = I*8*4 = 20*8*4 = 640
2.
n = 8*4+1 = 33
3. 4
().
1 .

Un

Un-1

U1


, :

125

PORT_SEGM
RG

D0
0
1
2

PORT_SN
RG

D0
0
1
2
3
4

HG4
4

HG4
3

D0
D1
D2
D3
:

DATA

C1

HG1

C2

HG2

C3

HG3

C4

HG3

126

HG4
HG4
2
1

DISPLAY

PORT_SEGM

PORT_SCAN

t
Tscan = t 50
D7 D6 D5 D4 D3
0
0
0
0
0

0
0
0
0
0

0
0
0
0
0

0
0
0
0
1

D2 D1 D0
0
0
1
0


DISPLAY XRA A
OUT PORT_SCAN
MVI B,00000001
PUSH B
LXI D,DATA
AGAIN
LDAX D
CALL CROSSCODE
OUT PORT_SEGM
POP B
MOV A,B
OUT PORT_SCAN
CALL DELAY
CPI 00001000
JZ DISPLAY
RLC
MOV B,A
PUSH B
INX D
JMP AGAIN




()


t
,

: .

127

.

, .

()


INT (RST)

t

INIT_DISPLAY
:

XRA A
OUT PORT_SCAN
MVI A,00000001B
PUSH PSW
LXI D,DATA
EI

ORG XXX

.
DISPLAY:
XRA A
OUT PORT_SCAN
LDAX D
CALL CROSSCODE
OUT PORT_SEGM
POP PSW
OUT PORT_SCAN
CPI 00001000B
JZ AGAIN
RLC
PUSH PSW
INX D
EI
RET
AGAIN

XRA A
OUT PORT_SCAN
MVI A,00000001B
PUSH PSW
LXI D,DATA
EI
RET
128



?
,


:
1. .
+5 B

PORT_SEGM

a
1

K1559

h

PORT_SCAN

1
1
K1553

2. .

+5 B


PORT_SEGM

R1
1

R2
300

VT1
KT209
KT503

300
a


PORT_SCAN

R
1

150...300

:
1. .
2. .
3. .

.
I = 1520

:
1.
2. .
129

:
1.
2.
.
,
.
SA1

1
2
3

3
2
1

6
7
8

SA1

SA2

:
:

+5 B

R1
SA1

R2 ...

SA2

SA8

DI
0
1

+5 B
SA1

RG

R8

DI
0
1

R1 R8 1...4,7 kOm

SA1
11111110
00000000
SA2
11111101
00000001
SA3
11111100
00000010

SA8
01111111
00000111
.
1.
2.
130

RG

SA8

.
, :
.
IN IPORT
CMA
CPI
MASK
JZ EXIT
, .
MASK1 EQU 00000001B
MASK2 EQU 00000010B

MASK8 EQU 10000000B


IDENTIF1
:

IN IPORT
CMA
CPI MASK1
JZ EXIT1
CPI MASK2
JZ EXIT2

CPI MASK8
JZ EXIT8
MVI
B,0FFH
RET

EXIT1
EXIT2

EXIT8

MVI B,00H
RET
MVIB,01H
RET

MVI B,07H
.

( ,
= 1).

131

IDENTIF2


() = 8

CY=1?

CY=1?

IDENTIF2 IN IPORT
MVI B,0
MVI C,8
CMA

ORA A
CY
SHIFT
RAR
JC EXIT
INR B
DCR C
JNZ SHIFT
MVI B,OFFH
EXIT
RET
.
,
() 0, .
: .

132

+5
SA1 20 = 1

23 22 21 20
0
0 0 0 0
1
0 0 0 1


9
1 0 0 1

SA2 21 = 2
SA2 22 = 4
SA2 23 = 8

+5
SA1

R1

DI
0
1
2
3
4
5
6
7

R4

R5

SA2

I0 1,6
RG

U0 = 1,6*300 = 0,48
U0max 0.8 B

R8

+5
R1 R8 = 300 Om
Ak
:

, :
1. . ,
, ,
.
KEYBOARD1
WAIT_ON
DELAY
WAIT_OFF
IDENTIF

133

KEYBOARD IN IPORT
CMA
ORA A

JZ KEYBOARD
PUSH PSW
CALL DELAY
WAIT
IN IPORT
CMA
ORA A
JNZ WAIT

CALL IDENTIF
RET
IDENTIF

POP PSW

: .
2. ,
, 10 .
KEYBOARD2

CY=1?

() = 8

.
3. :
+5 B
DI
0
1

SB1
SB2

SB8

RG

7
& 134

KEYBOARD3

DELAY
WAIT_OFF
IDENTIF
RET
.
.
.
.
,
.

:
( 0),
1, 0, .

58079 .
:
( )

135

( ):
; FIFO.
.
( ).

RL0
RL1

RL7
SHIFT
CTRL/
SL0

SL3
DSPA0

DSPA3
DSPB0

DSPB3
BD
IRQ

0
1

A0
CS

PKDC

RD
WR
CLK
RESET
Ucc
GND

;
;
S ;
RD ;
WR ;
LK fmax = 2 m;
RESET 1 - 0;
Ucc +5 ;
SND ;
RL0 ... RL7 ( );
SHIFT ;
CTRL/ S T B - ;
SL0 ... SL3 - ( );
DSPA0 ... DSPA3 ;
DSPB0 ... DSPB3 - ;
BD ( );
IRQ .

58079.
:
0 = 1

0 = 0

1
136

0000
0001

0
1

1
2

/

8

1111
15
:
1. ( );
2. ;
3. ( ).

000
001

111



.


.
( )
.


(
)

.
7 6 5
0 0 0

0
1
0
1

0
0
1
1

245 :
2 2

4 2 4

5 2 4 5
245 :

2 2

2 4 4
2 4 5 5

0
0
0
0

0
0
1
1

0
1
0
1





137

SL0 SL3
SL0 SL3
SL0 SL3
SL0 SL3

1
1
1
1

0
0
1
1

0
1
0
1

SL0 SL3
SL0 SL3
SL0 SL3
SL0 SL3

( ).

0
1
2

0
1
2
3
4
5
6
7

( 1).
SL0
SL0
SL0
SL0
.
7 6 5 4 3 2 1 0
1 1 0 F 0
F .
0 FIFO, .

0
0
0

0
1
1

0
1

( )

( )

: 20 = 00100000

.
7 6 5 4 3 2 1 0
0 0 1
.
138

f clk

K1 = 100

K2 = 2 ... 31

f scan

:
0 = 1
DAN 0 = 0
: :
, , ,
5 , 2 .
7 6 5 4 3 2 1 0
0 0 0 0 1 0 0 0
fclk 2
f1 = 2000/100 = 20
f2 = fskan = 5
= 4
INIT1 MVI A,001H
OUT
MVI A,008H
OUT
MVI A,24H
OUT
.
7
0

6
1

5
1

4 3 2 1 0
I

7 6 5 4 3 2 1 0

0000
0001
1111

0
1

15

I (
).
139

.
7 6 5 4 3 2 1 0
1 0 0 I
: , .
01100101 = 65
MVI A,65H
OUT
IN DAN ; 0101
: , .
01100010 = 62
MVI A,62H;
OUT ;
IN DAN;
ORI 10000000B ; 7 = 1
MOV C,A;
MVI A,82H; 10000010
OUT ;
MOV A,C;
OUT DAN;
.
:
1. ( ,
).
00
0
00
1
11
1

0
1

7 6 5 4 3 2
0 1 0 I



2. , ( FIFO
; ).
0 1 0
: .
140

MVI A,40H
OUT
IN DAN

.
: IN .
7
6
5 4 3 2 1 0
DU S/E 0 U F N N N
FIFO
( )
F : 1 - FIFO .
U : FIFO/
0 FIFO: FIFO .
S/E .
DU : (
).

.
1. .
2. .
.
(IRQ) 1,
, .
FIFO.
, .

IRQ

VVOD

INT
ORG XXXXH
PUSH PSW
MVI A,40H
OUT
IN DAN
CALL OBR
POP PSW
EI
RET

FIFO

VVOD2 IN

ANI 00001111B
141

JZ VVOD2
MVI A,40H
OUT
IN DAN


()

.
.
: , .
0

D E

Q
1
Q
3
Q
5
Q
7

Q2
Q4
Q6
Q8

5 4 3 2 1 0

HG6
0
1

0
1

HG1

D
0
1

7
A0
CS
RD
WR

&

PCKD

reset RESET
F2 CLK

A7 A6 A5 A4 A3 A2 A1 A0 HEX

1
1
1
1
1
1
1
0
FE
DAN
1
1
1
1
1
1
1
1
FF
, .
RL0
RL1

RL7

SL0
SL1
SL2
SL3

0
0
1
1
2
2 DC 3
4
X
5
6
KP15337

142
0


0 0 0 0 0 0
0 0 0 0 0 0

0 0 0 0 1 0

0 0 0 0 1 1
0 0 0 1 0 0
0 0 0 1 0 0

0 0 0 1 0 1

0 0
0 1
0 0
1 1
0 0
0 1
1 1

0
1

F
Q1
Q2

Q8

R1

R2

+5 B

+5 B

KP58083
DSPB0
DSPB1
DSPB2
DSPB3
DSPA0
DSPA1
DSPA2
DSPA3

IRQ

DI
D0
0
0
1
1
2
2
3
RG
3
4
4
5
5
6
6
7
1 STB
7

HG1
R7

1
2
3
4
5
6
7
8

R14

0
a
b
c
d
e
f
g
h

HG2
1
2
3
4
5
6
7
8

0
a
b
c
d
e
f
g
h

OE

.
:
- ( ).
.
.
:
.
.
:
143

.
.
:
(FORTRAN) .
(ALGON).
(COBOL) .
(BASIC) .
(FOCAL).
(PASCAL) , .
(C) .
++ (-
). -Builder ++ ().
.
:Microsoft Borland International.
:
Turbo C
Turbo C++
Borland C++
:
;
;
Basic : .
.
.
,
.
.
.
Borland C++ :
1. (IDE).
2. .
3. ( ).
4. .
5. .
6. .
Turbo C 3.1. MS DOS, i80386, 1 , 10 .
:
;
;
, , .
:
.
++ .p.
: bc.exe
, .obj.
: link.exe.
, .
.
144

.
/* hello.cpp*/
#include <stdio.h>
main ( )
{
puts (Hello, programmer); //
return 0;
}
1. :
/*
*/
// ++
2. : main ( ) .
3. puts ( ) .
; - ( ).
4. ,
(.h);
include/ #.
Stdio.h .
5. return 0 ( ).
6. { } - .
.
(void main), return .

.
;
.
.
, , , .

, .

,
.


0.

,
0.


, 0 (0)

[].[].

[]| | +| -| []
:
1. ().
2. .
1. #define , .
#define DAYS_IN_WEEK 7
145

`A`, `!`
Hello
25, 56
075
0xfe
0XFE
15., 15.25
4e7, 5.1E-8

#define CHARACTER `A`


#define PHONE 77-25-45
2. const _ _ = ;
const int DAYS_IN_WEEK = 7;

.
1.
2.
3.
4.

int.
char.
float ( ).
.

Int i char .
Unsigned int (char) .
1 10 .

:
,

Char
1
-128127
Unsigned char
1
0255
Int
2
-3276832767
Unsigned int
2
065535
Long
4
-21474836482147483647
Unsigned long
4
04294967295
Float
4
3.4*10-383.4*1038
Unsigned float
8
1.7*10-3081.7*10308
Long double
10
3.4*10-49323.4*104932

.
.
Int i; // .
Float x;
Int i1, i2, i3;
Int i1,i2=45, i3=1245;
( ),
, .
, 32.
.
:
Auto
Do
For
Short
Void
Break
Double
Goto
Signed Volatile
Case
Else
If
Sizeof
Union
Char
Enum
Int
Static
Const
Entry
Long
Struct
Continue Extern Register Switch
Default
Float
Return Typedef
146

.
( ),
\0 ( ).
Char client [10];
Char client [ ] = ;

\0
Char client [5] = ;

\0

:
1. #define:
#define client ;
2. :
Const char client = ;
Escape .
, scape , escape .
Escape \
Escape :

\f


\n


\t

147

.
,
.
().
:

.
:
1.
:
putchar ( ) - .
Getchar ( )
/*putgetch.cpp */
#include <stdio.h>
#define initial H
main ( )
{
char letter = G;
char in_letter;
putchar (initial);
putchar (letter);
putchar (\a);
putchar (\n);
in _letter = getchar ( );
putchar (in_letter);
putchar (n);
return 0;
}
putgetch.exe
HG
_X
_
2.
:
puts ( ) .
Gets ( ) , , ENTER.
/* getsputs.cpp */
#include <stdio.h>
main ( )
{
char name [20];
char full_name [80];
puts ( );
gets (name);
puts ( );
puts (name);
puts ( );
148

gets (full_name);
puts ( );
puts (full_name);
return 0;
}
3.

, ;
Printf ( ) .
Scanf ( ) .
printf ( ) %.
()
%d .
%f .
%c .
%s .
Printf ( ) .
/*print.cpp */
#include <stdio.h>
main ( )
{
int a=5, b=7, c;
c=a+b;
printf ( %d \n,c);
return 0;
}
:

float a=1.2, b=1.44, c;


c=a+b;
printf ( %d \n,c);

: 2.639999
:
Printf ( %2f \n,c);
2 .
/*inout2.cpp */
#include <stdio.h>
main ( )
{
int a,b,c;
printf ( :);
scanf (%d %d,&a, &b);
c=a+b;
printf ( %d \n, c);
return 0;
}

149

scanf,
scanf
. .
Fflush (stdin) , , scanf.
Gets ( ) .
Atoi ( ) int.
Atof ( ) .
stdlib.h
/*inout3.cpp */
#include <stdio.h>
#include <stdlib.h>
main ( )
{
char name [80];
age_str [80];
weight_str [80];
int age;
float weight;
printf ( :);
gets (name);
printf ( %s! \n name);
printf ( ?);
gets (age_str);
age=atoi (age_str);
printf ( ?);
gets (weight_str);
weight = atof (weight_str);
printf ( , - %d, - %2f \n, age, weight);
return 0;
}
gethch ( ) , ENTER ,
char.
, .
puts ( ENTER);
Getch ( ) conio.h.

.
.
, .
:
(1 ).
(2 ).
:
;
;
;
;
.
150

: +, -, /, *, %, ++, -% - .
Int a=5, b=2, c;
C=a%b; //c=1
C=b%a; //c=2
++ - (+1)
-- - (-1)
:
: ++i.
- : i++.
: 1,
. ,
1.
Int a=0, b=1, c, d;
C=a++; // c=0, a=1;
D=++b; // b=2, d=2;
.
& - (AND)
| - (OR)
^ - (XOR)
~ - (NOT)
.
:
<< - ( ).
>> - ( ).
:
.
.
,
.
TRUE -1 FALSE 0.
= = - .
!= - .
< .
> - .
<= - .
>= - .
&& - .
|| - .
! .

var1=15, var2=0;
!var1; //=0
151

!var2; //=1
var1|| var2; //=1
var1&&var2; //=0

.
,
.
: ( ) :
Long double
double
Float
Unsigned long
Long
Unsigned int
Int
Char
: (type).
Int a=8, b=5;
Float var1, var2;
Var1 = a/b; // var1=10
Var2 = (float)a/(float)b; // var2=1,6
: .
:
, .
_1&&(_2 || _3); _1=0, = 0.

.
;
;
.
if.
If ()
_1;
Else
_2;
() _1, _2.
If ()
{
_1;

_12;
}
else
152

_13;
/*ifelse.cpp */
#include <stdio.h>
#include <conio.h>
main ( )
{
char ch;
puts ( ? y/n);
if ((ch=getch ( ) = = n)
puts ( );
else
puts ( );
return 0;
}
switch.
Switch (_)
{
case _1: _1;
break;
case _2: _2;
break;

break;
default: _(n+1)
/*switch.cpp*/
#include <stdio.h>
main ( )
{
int k;
printf ( 1 4 );
scanf (%d,&k);
switch (k)
{
case 1: printf ( 1\n);
break;
case 2: printf ( 2\n);
break;
case 3: printf ( 3\n);
break;
case 4: printf ( 4\n);
break;
default: printf ( \a\n);
}
return 0;
}
.
While ...
Do ... while
153

While :
While () ;
, , , ,
.
While ()
{
_1;

_n;
}
/*while.cpp*/
#include <stdio.h>
main ( )
{
int dlina=0;
puts ( , Enter);
while (getchar ( )!=\n)
dlina ++;
printf ( %d\n, dlina);
return 0;
}
do ... while :
do
;
while ();
, , ,
( , ).
Do
{
_1;

_n;
}
while ();
#include <stdio.h>
#include <conio.h> // getch ( )
#define ESC 27 // ESC
main ( )
{
float a, b, res;
do
{
puts ( );
scanf (%f%f, &a, &b);
res=a*b;
printf ( a*b %f \n, res);
154

puts ( ESC );
}
while (getch ( )!=ESC);
return 0;
}
, :
int i=0;
while (i<60);
{
printf (i=%d \n);
i++;
}
FOR.
.
For (_1; _2; _3)
;
_1 .
_2 .
_3 .
{
_1;

_n;
}
#include <stdio.h>
main ( )
{
int repeat;
for (repeat=1; repeat<=10; repeat++)
printf (%d \n, repeat);
return 0;
}

.
1 .
,
- .
:
_ _ ( _1, _n)
{
;
_1;

_n;
return ();
}
155

, void,
return .
, int.
, .
( ) , , .
, :
_ (void)
_ ( )
:
Int mul (int a, int b)
{
return;
}
void output (float x)
{
printf ( x=%f \n, x);
}
int input ( ) // int input (void)
{
int i;
puts ( :);
scanf (%d, &i);
return i;
}
, .
(
, ).
:
_ _ ( _1, _n);
Int mul (int a, int b);
Void output (float x);
Int input ( );
#include <stdio.h>
int sqr (int x);
//
main ( )
{
int t=10;
printf ( %d %d \n, t, sqr (t));
return 0;
}
int sqr (int x) //
{
x=x*x;
return x;
}
156

x .
t .

.
F1.
- .h ( ):
Stdio.h .
Conio.h .
Dos.h .
Math.h .
Sound (unsigned int) , , .
Nosaund ( ) .
Delay (unsigned int) .
Int kbhit 0, ,
.
/*sound.cpp*/
#include <stdio.h>
#include <dos.h> //
sound ( ), nosound ( ), delay
#include <conio.h> // kbhit ( )
main ( )
{
unsigned freq;
printf ( ( 50 5000));
scanf (%d, &freq);
while (!kbhit ( ))
{
sound (freg);
delay (2000);
nosound ( );
delay (1000);
}
return (0);
}

.
Inportb .
Outportb .
Inport ( ).
Outport .
dos.h.
Unsigned char inportb (unsigned port);
Port (0 65535), .
Void outportb (unsigned port, unsigned char value);
Port .
Value , .
#include <stdio.h>
#include <dos.h>
157

main ( )
{
unsigned char result;
unsigned port=0; //
result = inport (port);
printf ( %d 0x%x \n, port, result);
return 0;
}
#include <stdio.h>
#include <dos.h>
main ( )
{
char value =C
unsigned port = 0; //
outport (port, Value);
printf ( % %d \n, value, port);
return 0:
}
conio.h :
Inp .
Outp .
Inpw .
Outw .
: .
SPEAKER , .
i8254
CT0 OUT0
,
61 h
f = 1.9318 M CLK
D0
RG
GATE
0
1
2

CT1 OUT1
CT2

OUT2
&

2 ( ).
GATE (1) (0) .
(&) D1 = 1.
2 =42h.
PYC =43h/
2 7 !
/*speaker.cpp */
#include <stdio.g>
#include <dos.h> // inportb ( ), outportb ( ), delay ( )
#include <conio.h> // kbhit ( )
158

#define CTRL_PT 0x43 //


#define CTRL_WD 0x66 // 2
#define N_LOW 026 // N
#define N_HIGH 0x11 // N
#define CT2 0x42 // 2
#defineSYST_PRT 0x61 //
main ( )
{
unsigned char ch1, ch2;
outportb (CTRL_PT, CTRL_WD); //
outportb (CT2, N_LOW); // 2
outportb (CT2, N_HIGH); //
ch1=inportb (SYST_PRT);
ch2=ch1; //
ch2=ch2 | 0x3 // D0=1,D1=1
while (!kbhit ( ))
{
outportb (SYST_PRT, ch2); //
delay (1000); // 1
ch2=ch2&0xfd; // 0xfd = 1111 1101
outportb (SYST_PRT, ch2); //
delay (1000);
ch2 = ch2| 0x2; // D1=1
}
outport (SYST_PRT, ch1);
return 0;
}
.
1 7.
:

3 ( ).
F = 440 ( )
N=f/f = 1931800 / 440 = 4390,45 1126h
: , .
01110110b = B6h.

.
, .
.
:
.
.

159

,
( ).
,
.
.
({)
.
Int global;
Void second ( )
{
unsigned lokal_2;
...
}
void first ( )
{
long lokal_1;
...
{
char lokal_3;
...
}
}
.
.

.
Heep ()
.

.
:
1. ,
. , .
2.
( ), .
3. ,
.
4. , ,
( ) (
).
:
( ).
Auto .
Regicter .
Static .
Extern .
:

.
160

auto, static,
, , int.
,
.
:
Static int a;
Double z;
Static b;
Auto int c; //
Func ( )
{
int d;
auto char e;
static double i;
}

first.c
Int a;
Void F1
(void)
{
Static int b;
...
}
Void F2
(void)
{
Extern int b;
...
}

second.c
Extern int b;
Int c;
Void F3 (void)
{
Extern int a
...
}
Void F4 (void)
{
...
}

F1
F2
F3
F4
A

.
1. .
1=2
1 .
2 .
: i = 3.
2. .
=+3
161

=*3

+=
E1+ =E2

1=1 + 2
-=
E1- =E2

1=1 - 2
/=
E1/ =E2

1=1/2
*=
E1* =E2

1=1 * 2
%=
E1% = E2

1=1 % 2
<<=
E1<<=E2

1=1 << 2 (2 )
>>=
E1>>=E2

1=1 >> 2

| =
E1| =E2
1=1 | 2
&=
E1& =E2

1=1 & 2
^=
E1^ =E2

1=1 ^ 2

.
1 ? 1 : 2;
1 .
2, 3 ( ).
1:
1 ( 0), 2.
1=0, () 3.
:
Int a=4, b=3, c;
C = c>b?a*a+b*b:0;
C = a*a+b*b = 25

sizeof ( ).
( ) .
, ,
.
:
Int i,r;
Char ch;
Long double ff;
r = sizeof int; //r=2
r = sizeof i; //r=2
r = sizeof long double; //r=10
162

.
.
, .
:
Int i;
I = 35;
&i
printf ( %d \n, &i);
(
, )
: *_.
, .
: int *iptr;
Float *fptr;
, :
Int *iptr;
Int i;
Iptr = &i;
:
#include <stdio.h>
main ( )
{
int i=35;
int *iptr;
iptr = &i;
printf ( , i);
}

. - .
_[-]

Int array [40]

- :
1. -
2. - ;
-=0.
3. . -= ( .. .. -
)
.. -:
1. (
) - .
2. -( . . -
{})
. 2 :
1. - . .( - ):
163

int array [10] = { 1,2,3,4,5 };


array [0] = 1;
array [1] = 2;
..
array [4] = 5;
) . . :
array [5] = 0;
..
array [9] = 0;
) . . - - :
array [5] = ?;
..
array [9] = ?;
- , -, , .
2. , . ( - - )
char array []= { A, B, C, D};
- . . 2 :
1. .
2..
1 - .
Main ()
{
int a[] = { 1,2,3,4,5 };
int index = 0, first, last, bad;
first = a [ index ]; // first = 1;
last = a [ index+4 ]; // last = 5;
bad = a [ index+6 ]; // bad
CI .
, , sizeof. -
, . .
Int array [] = { 1,2,3,4,5,6,7 };
Int members;
Members = sizeof ( array ) / sizeof ( int );
- = 7 -.
2 .. . . 1- -, *
-
array [ i ] *( array+i )
array = & array [ 0 ];
# include < stdio.h >
# define num 10
main ()
{
int array [ num ];
int index; // . .
For ( index = 0 ; index < num >; index ++)
Array [ index ] = index*10;
// ;
for ( index = 0, index < num >; index++)
printf ( - %d = %d \ n , index, *(array+index));
// .
Int * iptr;
Iptr = array;
164

For ( index = 0; index < num >; index++)


Printf( - %d = %d\n, index, iptr [ index ]);
Return 0;
}
CI .
dimension , . -

Int array [10] [20];

Int array [3] [3] = {00,01,02,


10,11,12,
20,21,22 };
int array [3] [3] = {{ 00,01,02 } { 10,11,12} { 20,21,22 };

.. - . ,
. . ( . - , ). ( . ).
: min - .
Int rand () . .
< stdlib.h >
# include < stdio.h >
# include < stdlib.h >
# define DLINA 10
int min_index ( int sp[ ], int ras )
{
int i, miniindex = 0; m;
m = sp [ miniindex ];
for ( i=1; i<ras; i++ )
if ( sp[ i ] < m )
{
m = sp [ i ];
miniindex = i;
}
return miniindex;
}
main ()
{
int k, list [ DLINA ];
for ( k=0; k<DLINA; k++ )
{
list [ k ] = rand ();
printf ( %d=%d\n, k, list[ k ]);
}
k = miniindex ( list, DLINA ),
printf ( %d = %d \ n , k, list [ k ]);
return 0;
}

165


. .
.
. . CI . - char, .
\ 0 ( - )

.. - . ASCII ASCIIZ
, . -:
Char array [ ] = ;
Char array [ 6 ] = ;
Char array [ 6 ] = { c , n , o , , o , \ o }
Char *string = ;
Char *string 1;
String 1 =

- ,
-
-
. < string.h >

-
Strcat()
Strcmp ()
Strcmp ()
Strcpy ()
Strdup ()
Strlen ()





.
( , )
.
.
.

Strlen ()
# include < stdio.h >
# include < string.h >
166

main ()
{
char name [ 40 ];
int count;
puts ( : );
gets ( name );
count = strlen (name);
printf ( % s % d \ n , name, count );
return 0;
}
:
Strcmp () 2 , . . - 0,
0, .
.
If ( strcmp ( name1, name2) == 0 )
Puts ( );
Else
Puts ( );
.
:

..
char name [ 20 ]
..
strcpy () , . :
strcpy ( name, );
..
strcpy ( name 1, name 2 );
:
, , ,
\ o .
Strcat ()
- 2
# include < stdio.h >
# include < string.h >
main ()
{
char name 1 [ 40 ], name 2 [ 20 ];
strcpy ( name 1, );
strcpy ( name 2, );
strcat ( name 1, name 2);
puts ( name 1 );
return 0;
}
-: .

.
. .
Char name [ 10 ] [ 20 ];
167

Max .

CI :
Gets ()
Puts ()
# include < stdio.h >
main ()
{
char name [ 10 ] [ 20 ];
int index;
for ( index = 0; index<10; index++);
gets ( name [ index ] );
for ( index = 0; index<10; index++)
puts ( name [ index ] );
return 0;
}

.
, . . . . ( .
. )
. . ( - )
Char *messages [ 10 ];
- . -:
Char *messages [] = { , , , };

, .
:
Typedef . .
Typedef __;
8 unsigned char
16 32 unsigned long
..
typedef unsigned char BYTE;
typedef unsigned int WORD;
typedef unsigned long DWORD;

.
BYTE b1,b2, b3;
..
WORD w1, w2;
:
. . ,
, , . . .
1. , - . . .
2. . , .
: . .
. . . :
168

1. .
2. . .
:
Struct _
{
1 _;
2 _;
.
n _;
};
struct BOOK
{
char name [ 20 ]; //
char title [ 44] ; //
int gear; //
float price; //
};
. . .
( )
Struct BOOK dog_book;
20+44+2+4=70
sizeof ( struct BOOT ) 70 .
.
.
. .
Dog_book . gear = 1998;
Strcpy ( dog_book . title, );
- .
Struct BOOK dog_book = { .. , , 1980,2,78};
Typedef struct
{;
char name [ 20 ];
char name [ 44 ];
int gear;
float price;
}BOOKS;
BOOKS dog_book; child_book;
.
Typedef struct
{
char name [ 20 ];
char title [ 44 ];
int gear;float price;
}BOOKS;
main ()
{
BOOKS first_book, *ptr;
Ptr = & first_book;
First_book = gear = 1992;
Strcpy ( first_book = name, .. )
.

.
169

Typedef struct
{
char name [ 20 ];
char title [ 44 ];
int gear;
float prite;
}BOOKS;
BOOKS library [ 50 ];
Int index;
Library [ index ]. Gear = 1990;
BOOKS *ptr;
Ptr = & library;
( ptr + index ) gear = 1992;

.
1. - - , -
- .
2. ( ) -, .
- .
.
2. # include < stdio.h >
# include < string.h >
typedef struct
{
.
}BOOKS;
void example ( BOOKS *first );
main ()
{
BOOKS ret;
Example ( & ret );
Printf ( % -20s % -40; % d, -%2, ret name, ret title, ret gear, ret price );
Return 0;
}
void example ( BOOKS * first )
{
strcpy ( first name, .. );
strcpy ( first title, );
first year = 1990;
first price = 5.25;
: .. 1990 5,25

.
, .
. .. CI
, . .
, . . .
Stdin ( )
Stdout ( )
Stderr . ( )
170

Stdprn
Stdaux . .
. , FILE.
. .
. .
FILE * _;
FILE * fp;
FILE * fin, * fout;
Fopen () < stdio.h >
Int fopen ( _ , _ )
R
W ( )
A
R+}
W+}
T
B
- fopen () : ,
null

FILE * fp;
Fp = fopen ( _ , W );
Fp = fopen ( a: \ myfiledat , W );
If (( fp = fopen ( myfile , W )) = NUUL )
{
puts ( );
return 1;
}
-:
Fclose ( _ );
FILE *fp;
.
Fclose ( fp );
Fcloseall ()
. . _.
0
1

+
+

,
EOF, .
.

- .
- ( ), - ( ).
. 4 .
1. .
2. .
3. .
4. .
1. .
Fgetc ()
Fputc ()
171

Int fputc ( , __ );
- , EOF
:
# include < stdio.h >
main ()
{
FILE *fp;
Char letter;
If (( fp = fopen ( myfile , W )) == NULL );
{
puts ( );
return 1;
}
do
}
letter = getchar ();
}
fputc ( letter, fp );
while ( letter ! = \ n );
fclose ( fp );
return 0;
}
int fgetc ( __ );
- , EOF
:
# include < stdio.h >
main ()
{
FILE *fp;
Char better;
If (( fp = fopen ( myfilo , r ) / == NULL )
{
puts ( );
return 1;
}
while ( better = fgetc ( fp ) ! = EOF )
printf ( % c , better);
fclose ( fp );
return 0;
}
int feof ( __ )
0, 0 .
Fputc.cpp
A: \ fputc.cpp
:
# include < stdio.h >
main ()
{
File *in, *out;
If (( in = fopen ( fputc.cpp , r )) ==NULL )
{
puts ( fputc.cpp );
return 1;
}
172

if // out = fopen ( a: \ fputc.cpp )) = NULL )


{
puts ( a: \ fputc.cpp );
return 1;
}
while ( ! feot ( in ))
fputc ( fgetc ( in ), out );
fclose ( out );
return 0;
}
2 .fputs ()
fgets () .
Int fputs ( __ );
, \ o (
).
, - NULL.
: / *fputs.cpp * /
# include < stdio.h >
# include < string.h >
main ()
{
FILE *fp;
Char name [ 40 ];
If (( = fopen ( myfile , W )) == NUUL )
{
puts ( );
return 1;
}
printf ( )
gets ( name);
while ( strlen ( name ) > 0 )
{
fputs ( name, fp );
fputs ( \ n , fp );
printf ( : );
gets ( name );
}
/*
Enter * /
fclose ( fp);
return 0;
}
int fgets ( , _, __ );
_ , .
- NULL ,
.
: / *fgets.cpp * /
# include < stdio.h >
main ()
{
FILE * fp;
Char name [ 40 ];
If (( fp = fopen ( myfilo , r )) ==NUUL )
{
puts ( );
173

return 1;
}
while ( name, 40, fp ) ==NUUL )
gets ( name );
fclose ( fp );
return 0;
}
3 - -;
fprintf () - .
() - .
( __, , _ )
.
EOF
Int fscanf ( __, _, _ )
: / * fprintf.cpp * /
# include < stdio.h >
# include < string.h >
main ()
{
FILE * fp;
Char filename [ 15 ];
Char product [ 20 ];
Float cost;
Int quantity;
Printf ( , : );
Gets ( name );
If (( fp = fopen ( name, W )) ==NUUL ))
{
printf ( . . %s \ n, name );
return 1;
}
printf ( . );
gets ( product );
while ( strlen ( product ) > 0 )
{
printf ( : );
fflush ( stain );
scanf ( % f , & cost );
printf ( - : );
fflust ( stdin );
scanf ( % d , & quantity );
fprintf ( fp, % s % f % d , product, cost, quantity );
printf ( : );
fflust ( stdin );
gets ( product );
}
fclose ( fp );
return 0;
}
/ * fscant.cpp * /
# include < stdio.h >
main ()
{
FILE * fp;
Char name [ 15 ];
174

Char product [ 40 ];
Float cost;
Int quantity;
Printf ( : );
Gets ( name );
If (( fp = fopen ( name, r )) ==NUUL )
{
printf ( . . % s \ n , name );
return 1;
}
while ( fscanf ( fp, % s % f % d , product, & cost, & quantity )=(EOF)
{
printf ( : % s \ n , product );
printf ( % 2 f \ n , cost );
printf ( - % d \ n , quantity );
}
fclose ( fp );
return 0;
}
fscanf () . , .
, - .

3
.
. . , . 380 50
mA.
. . -, .
. .
~ 1
182185
5735
57310
1533
1. :

380

175

TRA
P

( , , )

2.
2.1

ZQ1
+ 5

X1

R2

X2
RESIN

C1

V1

TRAP
TRAP

+5

.
15

READY

R1
+U2

CPU

..

RST 7.5
RST 6.5
RST 5.5
INTR
HOLD

MEMR

IOW

-U2

176

2.2.

11 = 0
11 = 1

5735

ROM

0
1

10
CS

57310
0
1

10

11

DD1

RAM

CS

DD2

0000
07FF
0800

0FF
F

+U2

+5B

153333
2.3.

I
0

+5

RG

0
1
2

0
1
.

..

C
OE
-U2

+5

+U2

4
1

IO
W

177
-U2

0000,0001 = 01 H

2.4.

853333

2
1

1
1

I
0

V1

RG

0
1
2

0
1
2
.
7

~380

+5

5
1

1
VL1
~220B

C
OE

+5

U3

&

IOW

1
178

0000,0010 = 02H
:
0 = 1

1 = 1 .
2 = 1 .
2.5.

SA1

11425

+U3

FU1

+5
+

+
~220B

C1

C2

C3.
..

C10

21428
+U2

-U2

PUMP
-

.
.


179

ALARM

.
.

:
.

: SP,
OPORT

IPORT

0=
1

50
01H OPORT
IPORT

1
=1

50
180
OPORT

ALAR
M
OPORT
03H
OPORT
500
OPORT
500
;
IPORT EQU;
OPORT EQU 02H;
STACK EQU 0FFFH;
ORG 0000H
PUMP: JMP INIT
ORG 0024H; . TRAP
JMP ALARM
ORG 0100H
INIT: LXI SP, STACK; . .
XRA A;
OUT OPORT
WAIT1: IN IPORT
ANI 00000001B; 0
JZ WAIT1; 0 = 0
CALL DEL50MS; .
MVI A, 01H
OUT OPORT;
WAIT2: IN IPORT
ANI 00000010B; 1
JZ WAIT2; 1 = 0
CALL DEL50MS
XRA A
OUT OPORT;
JMP WAIT1;
;
ALARM: XRA A
OUT OPORT;
MVI A, 03H;
OUT OPORT
181

CALL DEL500MS;
XRA A
OUT OPORT
CALL DEL500MS
JMP MEANDER
; .. 50 .
DEL50MS: LXI B, 3125
LOOP: NOP
NOP
NOP
NOP
DCX B
MOV A, C
ORA B
JNZ LOOP; ( BC ) 0
RET
; .. 500
; 10 ..
; 50
DEL500MS: MVI E, 10
CYCLE: CALL DEL50MS
DCR E
JNZ CYCLE
RET
END;
PUMP. ASM
PUMP. OBJ
PUMP. TSK
3. :

.
, . , ,
. - , -:
1. ( )
2. - .
3. , . .
- ,
-.
- :
1. - . .
2. - . -.
max .
, ( 1 . )
, . .
.
1. :
)

1

)

182
1

)
2. , . . , [ ./ . ]
3. Max -, [ ]
4. ( - .. )

.
1. . .
2. . .
1. .
2. .
. . . ..
- , , .
. . . .
- -:

: . , . .
: .
:
) . , .
.
SYN1

SYN2

..

. .
.
) .

..

SYN
STR
.AC

. . - , .
. , . . :

STR
183
ACK

:
1. .
2. .
3. .

Yi

1
1


- .

184

Yi

RQ


RQ

A1

RQ

..

Y1

An

Yn

RQ

.
:
-
-
, . .

185

1. .
+U

VT1

VT2

.
.
2. -, .

OE . :
OE = 1 Z .
OE = 0 0 1
.
.

~E
U


Uab

186


U1 = U1-( +Ub )
U0 = U0+( +Uab )
U1 U0 > U
: U > 0.4

5,0

5,0

2,0

2,4

U1

U1
0,4
0

U0
0,8

U0

()

.
.
1.

.
.

3.

.
.
.
:
) . .
) . .

~
)
1
U

~
2
187
U2

U1

U1 = U +
U2 = E
U = U1 U2 = U

..

( BS 4421 )
, , . ,
.. .
. - :
- - 2.

,
1 16
. 15 .

( )

----

S
Z
SO

----

A0

---
---
---

0 7

SC
AC
0 7

188

1
7

0
7

:
+5

R1

..
1

+5


. .
..

0
7

189

. , . ,
.

58055.
1

0
7

0
7

0
7

0
1

4
5

4
5
6

0
1
2

, .
.
1:
INIT 1

CHECK 1
OUTPUT 1 . .
190

2:
INIT 2

CHECK 2
INPUT 2 . .


L
0 0 0 0
H -

: 1000 0011 = 83H


: 0000 1101 =

0
1

0 0 0

0 0 1

.
7

1 1

INIT 1
.

( b

INIT 1: MVI A, 83H


OUT PYC
MVI A, 0DH
OUT PYC

1)

RET

INIT 2

( 7

CHECK
1

INIT 2: MVI A, 83H


OUT PYC
MVI A, 0FH
OUT PYC

RET
1)

. ( )

CHECK 1: IN PC
CMA
191

ANI 0000 1000


RET
3 = 1 . ,
3 = 0 z = 1.

CHECK 2: IN PC
CMA
ANI 0000 0100
RET

CHECK 2

.
2

OUTPUT 1

1
=
1

( )
4

1
=0

OUTPUT 1: IN PC
ANI 02H
JZ OUTPUT 1
;
MOV A, C
OUT PA
MVI A, 09H
OUT PYC
WAIT 1: IN PC
ANI 02H
JNZ WAIT 1
MVI A, 08H
OUT PYC
XRA A
OUT PA
RET

4
0
00
192

INPUT
2
5

0 =
1

INPUT 2: MVI A, OBH


OUT PYC
WAIT 2: IN PC
ANI 01H
JZ WAIT 2
IN PB
MOV C, A
MVI A, OA
OUT PYC
WAIT 3: IN PC
ANI 01H
JNZ WAIT 3
RET

0 =
0

Centronics

.
. . ( min = 2 )
1. RS 232 C
2. .
193

1. 2 / 2
( , )
2 :
1. ( 00 ) .
2. ( ) -

OOD
(DTE)

RS-232

AD
(DCE)

AD
(DCE)

RS-232

OOD
(DTE)

:
1. 25;
2. 9.
: (male ) (female ).
1

13

DB25P
14

25

DB9P
6

PG
SG
TxD
RxD
RTS
CTS

.
().
.
.
.

( ).
194

DSR
DTR
DCD
RI

( ).
.
.
().

+3 +12 .
-3 -12 .
:

U, B
+15
0
+5
0
-5
1
-15

:
U, B
+25
0
+3
0
-3
1
-25
| U| 2 .
DB9 DB25
TxD
3
2
RxD
2
3
DTR
4
20
DSR
6
6
RTS
7
4
CTS
8
5
DCD
1
8
RI
9
22
SG
5
7
DTE-1
TxD
RxD
DTR
DSR
DCR
RTS
CTS
SG

DTE-2

195

TxD
RxD
DTR
DSR
DCR
RTS
CTS
SG

XON =11H 1 .
XOFF = 13H 2 .
:
TxD
RxD
DTR
DSR
DCR
RTS
CTS
SG

TxD
RxD
DTR
DSR
DCR
RTS
CTS
SG

DTR .
RTS .
CTS .
80/85. 58051: .

F2
C

TxD
RxD
DTR
DSR
SIO
RTS
CTS
TxC
RxC

TT/RS

RS/TT

RS/TT
..

TT/RS

fc

TxD
RxD
DTR
DSR
SIO
RTS
CTS
TxC
RxC

: 300, 600, 1200, 2400, 4800, 9600 /.


= 1
= 16
= 64
: f = 4800 /.
. = 16
f = 4800*16 = 76800 .
: DSR = 0 CTS = 0.

.
INIT1

. .
..
196

: = 16.
.
.
: 0100 0000 = 40H .
: 0000 0001 = 01H .
INIT MVI A,40H
OUT

MVI A, XX
OUT

MVI A,01H
OUT

RET

OUTPUT1
.

TxRDY = 1

:
D7 D6 D5 D4 D3 D2 D1 D0
D0 1
D1 1 DTR = 0
D2 1
D5 1 DTS = 0
D6 1
:
D7 D6 D5 D4 D3 D2 D1 D0
DSR =1

1 (TxRDY)
1 (RxRDY)
.
OUTPUT 1 IN

ANI 01H
0
JZ OUTPUT1 TxRDY = 0
MOV A,C
197

OUT DAN
RET

INPUT1
.

RxRDY = 1

DAN

INPUT 2 IN
ANI 02H
JZ INPUT2
IN C,A
MOV A,C
RET
.

.
: DTR DSR; RTS CTS.

1
TxD
RxD
DTR
DSR
SIO
RTS
CTS
TxC
RxC

RS/TT

TT/RS

INPUT1.1
.

D7 = 1
(DSR=0)
INPUT1

198

2
TxD
RxD
DTR
DSR
SIO
RTS
CTS
TxC
RxC

INPUT1_1 IN
ANI 80H
JZ INPUT1_1
CALL INPUT1
RET

OUTPUT2_1
1 = 1
OUTPUT2

OUTPUT2_1 MVI A,03H


OUT
CALL OUTPUT2
RET

DTR
DSR

DTR
DSR

.
1

RTS
1 CTS
TxD
RxD
.
DTR
DSR
SIO
RTS
CTS
TxC
RxC

CPU
INT

RTS
CTS

TT/RS

RS/TT
199

2
TxD
RxD
DTR
DSR
SIO
RTS
CTS
TxC
RxC

1702:
-12 5

+12 8

TT 2

&

RS-232

U 1
1

&

TT 3

RS-232

4
1702:

3
4
2
5
1
6
14
7

+5 B
15

+12 B
10

13
12

11

10

RS-232

RS-422A

RS-423A

L = 9 m., V = 100 /
L = 1200 m., V = 1 /

L = 12 m., V = 10 M/
L = 1200 m., V = 100 /

.
.
I = 20 mA
I = 40 mA.
, 9600 /.
.
+
+
.
.
-

-
.
.

+
200
-

1 20 , 0 .
20 ,
.

+12 B
390

33

VT1
KT361

3k

VT2
0
KT361
VD1
(+)
(-)

+5 B
+

1k

VD1

15332

330
-

43k

VT1
128

..

I
201

E
I.. =
R
+ 2 R + R

..

I
: .

.

58051.


TxD
RxD
DSR
DTR
SIO
RTS
CTS
TxC
RxC

TT/RS

..

RS/TT

RS/TT

TT/RS
..

RxD
TxD
DTR
DSR
SIO
RTS
CTS
TxC
RxC

.
: , , ,
.
: , .

( ).

HPIB .
GPIB.
IEEE 488 .
IEC 625-1.
:
1 /
20 .
= 16
202



15
.

16 :
8
3
3 .
:
, ,
, ,
, .

, 0 -, 1
L-.

DI1 DI8

DAN
NRFD
NDAC
ATN
IFC
SRQ
REN
EOI

+5

203

:
DIO1 DIO8 . .
. :
(15) ( 32).
:
DAV (). ,
( ).
NRFD .
, .
NDAC ( ).
.
:
ATN , .
IFC () , .
SRQ , .
REN .
EOI .
: () .
:

DIO
DAV
NRFD
NDAC

2
3

7
4

DAV , NRFD NDAC . DAV


.
, , NRFD (1). ,
L- DAN (2).
NRFD = L- (3).
NDAC = L- (4).
NDAC = -, .
- NDAC DAV = - (5). ,
. L- NDAC (6) NRFD (7), .

.
, ATN = L-.
B8 B7 B6 B5 B4 B3 B2 B1
.
: B7, B6, B5.
B7 B6 B5
0
0
0

0
0
1

204

0
1
1

1
0
1

.
: : 0000 1110 30 .
, ,
, .
1111 UNT ( ).
:
UNL .
( ).
:
LLO .
PCL .
PPO
SPE
SPD
:
I8291 1 .
I8292 1 .
I8293 2 .

.
:
5 .
ASCII 7 .
-7 7 .
-8 8 .
ASCII
0
30H
1
31H

9
39H
+
23H
=
3DH
SOM
01H
EOM
03H
EOT
04H
NUL
00H

SOM

EOM NUL NUL SOM EOM EOT

0 00000000
1 00000001

255 11111111

0 255
205

: () DLE,
:
DLE STX .
DLE ETB .
DLE ETX .
DLE SOH .
DLE DLE , DLE.
DLE 55h
STX 76h
ETB 85h
: .
.
DLE

DLE

SOH DLE
| |
STX

STX

DLE

ETX

DLE

SOH DLE
| |

STX

DLE
ETB

.
IBM PC 1981 .
1. .
2. ( ).
3. .
/, :

8
8
A0 A19
20
D0 D7
8
IRQ2 IRQ7
6
DRQ1 DRQ3

3
DACK0 DACK3

4
MEMR, MEMW, IOR, IOW 4
AEN
1
RESET DRV
1
ALE
1
CLK
1
OSC
8
1
T/C
: GND,
206 1
IO CH SK
1
5 B, 12 B
IO CH RDY
1

:
0 19 (1 ).
07 .
IRQ2IRQ7 .
03 .
DRQ1DRQ3 .
MEMR, MEMW, IOR, IOW .
AEN .
AEN = H- .
AEN = L- .
RESET DRW .
ALE .
CLK f = 4,77 .
OSC fosc = 14,31818 , .
T/C .
IO CH SK .
IO CH RDY .

A31

A1
B1

Host Bus
B31

SRAM ()

A31

Host - PCI A1

DRAM (
)

PCI

PCI
PCI
- ISA
PC/AT

ISA.

ISA

ATX:
CPU
PCI
ISA

207

1. ISA.
2. Centronics.
3. RS-232 C.


ISA
2 ()
(
)

RS-232 C
5 ()
15
( )

Centronics
100 ()
2
(
)

,
8 16

,
8

36

ISA.
SA0 SA15 ( ).
SD0 SD15 .
:
1. 16 .
2. 8 .
I/O CS16 :
= 1, 8 - ( ).
= 0, 16 - .
I O R - .
I O W - .

208

SYSCLK ( fcl = 8 )
.
I/O CH RDY = 1, ; =0,
=1/fcl.
T 15 .
.
RESET DRY (
).
RESET
DRV

>1 mc
AEN , , = 1
.
:

+5
-5
+12
-12

,
4,5
1,5
1,5
1,5

200 .
,
+5
720
-5
00,3
+12
2,57,5
-12
00,3
- , :

Ivx 0 0.8mA
Ivx1 40mA
Ivix 0 24mA ,
Ivix1 3mA .
20
< 65 .
:

SYSCLK


91 .

SA0 SA15
S


176 .
>91

>176

>13

<32

SD0 SD15

<110

209

<62




110 .

1. .
2. .

:
1. .
2. .
58086 .
15336 .
I0 32 .
I1 5 .
58082 .
153333 .

SA0

SA7
+5 B

KP153333
DI RG D0
0
0
1
1
2
2
3
3
4
4
5
5
6
7
6
C
7
OE DD1

D0
0
SA8
BA8
1
SA9
BA9
AEN
2
BAEN
3
4
RESET DRV
B
5
A
SYS CLK
BF
B RESET
DRV0
0
6 SA0
B SYS
1 CLK 1
7
+5 B
DD2
BA0 2
2
3
3
4
15336 .
4
5
6
5
7
6
SA7
EAB
7
DI
0
1
2
3
4
5
6
7
C
OE

BA0

BA0

RG

IOW

IOR

OE

BD0

BD0

210

SEL

BIOR

BIOR
BIOW

= 1 .
= 0 .
O E = 1 Z .
SA0 SA9 , .
300 31FH .
300 307 , .
9 8 7 6 5 4 3 2 1 0
1
1
0
0
0
0
0
0
0
0

1
1
0
0
0
0
0
1
1
1
. .
N .
N = 1 , N = 0.
15332
BA7
BA6
BA5
BA4
BA3
AEN

BA9
BA8
1
1
1
1
1
1

BA0
BA1
BA2

&

1
A
2
0
3
1
DC 4
2
5

S E 3L0 H
S E 3L0H

6
7

&

15337



:
58055 .

SEL
+5B

PA
O
BD0
0
1
BD1
1
2
BD2
2

BD7
7 PIO 7
PB
BA0
A0
0
B
BA1
A1
1
&
CS
2
RD

WR
RESET
7
BRESET DRV
B
D

&

&

R8 4,7k

R1

1 6

211

S E 3L0 H

SA8

SA1

R9

R16

VD1

VD7

0
1
1

1
0
1

300
301
302
303

.
.
.
: 10010000 = 90
D0
,

.
0
/
1
AI
/#

AG
9 SVET
DG
DR

K555A3
/#
A
Q
/*svet.cpp*/ 1
1500
B/
# include <stdio.h> B G1 C
R/C
R
# include <dos.h>
4.7k
# include
+5B <conio.h>
# define PA 0x300
9.1k
# define PB 0x301
# define RUS 0x303
# define CW 0x90
main ( )
U AI DD1
{
1
unsigned char input;
outportb (RUS, CW); //
1
while (!kbhit( ))
{
input = inportb (PA); // SA
outportb (PB,~input);
}
return 0;
}

DO
0
1
2
3
4
5
6
7
8
9
DR

DI
0 RG DO
0
1
1
2
2
3
3
4 SA

4
5
5
6
7 VD 6
7
C
1
OE DD2

1
1

DI
0 RG DO
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
C
OE DD3

K11131 10- .
/ C - .

BIOR
212

BIOR

BD0
BD1
BD2
BD3
BD4
BD5
BD6
BD7

BD0
BD1
BD2
BD3
BD4
BD5
BD6
BD7

3 0 4 H .
DD2 ( 3 0 5 H ).
DD3 ( 3 0 6 H ).
ADC

..
..

0+10,24 .
03FFH .
01024 .
Kod
U=
10.24
1024
/*adconv.cpp*/
# include <stdio.h>
213

# include <dos.h>
# include <conio.h>
# define START 0x304 //
# define ADRL 0x305 //
# define ADRH 0x306 //
main ( )
{
while (!kbhit ( ))
{
unsigned code_ADC = 0; //
unsigned char code_L;
unsigned char code_H;
float U; // .
Outportb (START, 0);
While (((code_H = inportb (ADRH))&0x80)!=0);
Code_L = inportb (ADRL); //
Code_ = inportb (ADRH); //
Code_ADC = (code_H&0x03)<<8 + code_L;
U = (float) code_ADC*10.24/1024;
Printf ( = % , = %4.2f \n, code_ADC, U);
}
return 0;
}

Centronics .
- .
:
D0 D7 .
S T R O B E - .
BUSY .
A C K N L G - .
>500 >500 >500
D0 D7
D
B
BUSY
>2500
:
A U T O F D - ( ), .
.
SLCT .
S L C T I N - ( ).
I N I T - .
:
214

13

D
DB25P
14

25

.
1
2
3

9
10
11
12
13
14
15
16
17
1825

STR O B E
D0
D1

D8
A C KNL G
BUSY
PE
SLCT
A U T O FD
ERROR
INIT
S L C T IN
GND

I/O
0
0
0

0
I
I
I
I
0
I
0
0
-

.
2 .
2 .
:
LPT1 378
LPT2
LPT3
.
+1 ( ).
+2 ( ).
Centronics:
1. .
2. (100 /).
:
1. ( ).
2. .
3. .
(BASE)

(BASE+1)


(BASE+2)

D7

D6

D5

D4
D3

BUSY ACKNLG PE SLCT ERROR

, .
-

D2

D1

D0

INIT

AUTO
FD

STROBE


SLCT
IN

, .
: 8 8 .
215

+5

STROBE
INIT

KP153325
0
DI
0
0
1
1
2
RG

3
7

C
7
R

330
1

330

1553
+5 B

KP1533K11
1
A0
A1
A2
ERROR
A3
SLCT
Y0
B0
PE
MS Y1
B1
ACKNLG
Y2
B2
Y3
B3
SLCT IN
S
VD0).
R = 0 - VD (INIT = 0
OE
= 1 (STROBE = 1 ).
= 0 ( , STROBE =0).
S = 0 , Y=A.
S = 1 Y = B.
SLCT IN .
# include <stdio.h>
# include <dos.h>
# include <conio.h>
# define BASE 0x378
# define STROBE 0x01
# define INIT 0x04
# define SLCT_IN 0x08
# define MASK 0x0F
void control_drv (unsigned char control)
{
outportb (BASE+2, control^0x0B);
} // .
// :
unsigned char status_drv ( )
{
return ((inportb (BASE+1)>>3)^0x10);
}
//
void write_VD (unsigned char data)
{
outportb (BASE, data); //
control_drv (STROBE\INIT); // =1
control_drv (INIT); // =0
216

}
//
unsigned char read_SA ( )
{
unsigned char data;
data = status_drv ( )&MASK;
// SA0SA3
control_drv (SLCT_IN | INIT); // SA4SA7
data+=(status_drv&MASK)<<4;
return data;
}
main ( )
{
control_drv (0); //
control_drv (INIT); //
while (!kbhit ( ))
write_VD (read_sa ( ));
return 0;
}

KP153377
STROBE
0
AUTO FD
1
INIT
0
2
SLCT IN 1
3
DC
2
4
&
5
6
7
INIT AUTO FD STROBE
0
0
0
0
0
1

STR 0
STR1

STR 7


.
RS-232C .
,
.

217

RS-232c

RS-232.
IFC1488 .
55919.
+5 B
3
&
4
5 &
9
10 &
12
13 &

DIP14
1 -12 B
14 +12 B
7

3
6

RS-232C

8
11

IFC1489 (55920).

RS-232C

1
g1 2
4
5
g2
10
9
g3
13
12
g4

DIP14
&

&

&

&

11

14 +5 B
7

g
(
)

:
.
.
I8251 (58051)
I8250 (18472)
TL16C450
TL16C550
:
1 3F8H 3FFH () IRQ4 ()
COM2 2F8H 2FFH () IRQ3 ()
COM3 3E8H 3EFH () IRQ10 ()
COM4 2E8H 2EFH () IRQ12 ()
1
:

13

DB25P
14
1

25
5

218

DB9P
6

:
: i8250, TL16C450.

CS

1,8432
RS

TT

TT

RS

8 , 6 .
(BASE):
COM1: BASE=3F8H
COM2:BASE=2F8H
BASE :
,
RG BASE+3:
1. BASE
.
2. =1, BASE RG
.
- , /
0410
0300
0180
000
0060
0030

110
150
300
600
1200
2400


0018
000
0006
0003
0002
0001

4800
9600
19200
38400
57800
115200

BASE+1 ( 2 ).
RG BASE+3.
1. BASE+1
.
2. .
BASE+2 ( ,
).
BASE+3 ( ).

0,1
:
00 5
01 7
219

2
3,4

6
7

10 6
11 8
:
0 1
1 2
:
0
10
11
:
1 = 0 ( )
1 = 1 ( )
.
1
0 .
BASE BASE+1

BASE+4 ( ).

0
DTR
1
RTS
2,3
(OUT1 OUT2)
4
:
0
1
5,6,7

BASE+5 ( () )
.

0
1
1
1
2
1
3
1 ( )
4
1
5
1
6
1 .
7
1 TIME OUT
BASE+6 .

0
CTS
1
DSR
2
RI
3
DCD
4
CTS
5
DSR
6
RI
7
DCD
:
1. BASE+3 1 .
2. BASE BASE+1.
220

3. BASE+3 0
.
4. BASE+1 ( , 0).
5. BASE+4.
( ) serial.h.
// int BASE//
#define OUT_REG BASE // .
#define IN_REG BASE //
#define LOW_DIV BASE //
#define HIGH_DIV BASE+1 //
#define INT_REG BASE+1 //
#define INT_ID_REG BASE+2 //
#define CONTROL BASE+3 //
#define MODEM BASE+4 //
#define STATUS BASE+5 //
#define M_STATUS BASE+6 // .
//
# define B_4800 24
# define B_9200
# defineDEVISOR 0x80 //
# define BIT_8 0x03 // 8
# define STOP_2 0x04 //2
# define NOPARITY 0x00 //
# define DTR 0x01 // DTR
# define RTS 0x02 // RTS
# define LOOPBACK 0x10 //
# define DATA_IN 0x01 //
# define DATA_OUT 0x80 //
# define OVERRUN 0x02 //
# define FRAME_ERR 0x08 //
# define CTS 0x10 // CTS
# define DSR 0x20 // DSR
//
void init ( ); //
void out_sym (int symbol); //
int in_sym ( ); //
:
/*test.cpp*/
# include <stdio.h>
# include <dos.h>
# include <conio.h>
# include serial.h
#define ESC 27
main ( )
{
BASE = 0x3F8;
Int symbol, symbol2;
Init ( ); //
Outportb (MODEM, LOOPBACK); //
While (1)
{
221

symbol = getch ( );
if (symbol = = ESC)
return;
out_sym (symbol); //
symbol2 = in_sym ( ); //
printf (: %, : % \n, symbol, symbol2);
}
return 0;
}
void init ( )
{
outportb (CONTROL, DIVISOR);
outportb (LOW_DIV, B_9200);
outportb (HIGH_DIV, B_9600>>8);
outportb (CONTROL, BIT_8 | NOPARITY | STOP_2);
outportb (INT_REG,0); //
}
void out_sum (int symbol)
{
while (inportb (STATUS) & DATA_IN) = = 0);
outportb (out_REG, symbol);
}
int in_sym ( )
{
int sym;
while (inportb (STATUS) & DATA_IN) = = 0); //
if (intportb ((STATUS) & (FRAME_ERR | OVERRUN))!=0);
}
printf ( \n);
return;
{
sym = inportb (IN_REG);
return sym;
}
1. :

D 2
RxD
SG

2 D

RxD

SG

2. :
) XON/XOFF.

RxD

SG

2 D
222

3 RxD
5 SG

, XON=11h,
1 . XOFF = 13h
.

) :

D 2

2 D

RxD

RxD

SG

SG

RTS

RTS

CTS

CTS

DTR 2

DTR

DSR

DSR
1. RTS CTS
2. DTR DSR
3. RTS CTS; DTR DSR

I2C.
3 :
1. ; ;
.
2. (, , , , ).
3. , :
, .
Phillips ,
: intel IC (IIC, I2C).
.
:
SDA ( )
SCL .
100 /.
400 /.
400 .
, : , n-, ,
.
:
I) :
1) .
223

2)
3)
4)
5)

( ).
.
, .
.

II) :
1) 2 ,
.
2) .
I2C: .
, .
:
1) Master (, ).
2) Slave (, ).
.
.
.
:
1) .
2) .
.
. . ,
, .
, :
().
+U
R

SCL
SDA
SCL-1
IN

SCL-1
OUT

DATA-1
OUT

DATA-1
IN

( 2
)

.
R .
U = 3 15 . ( 5 ).
SCL.
:
SDA
SCL



()


()

() START STOP , .
224

SDA

SCL
START

SDA
SCL

STOP

: ;
.
SDA
SCL

START

ACK
()

9
ACK

STOP

: . :
.

.
, :
1. (27=128)
2. .
START.
START A6 A5 A4 A3 A2 A1 A0 R/ W A C K

|
|
|

( )

: 7 -

R/ W =1, ( )
R/ W =0, ( ).
:
START 1 1 1 1 0 A9 A8 R/ W

ACK

A7 A6 A5 A4 A3 A2 A1 A0

AC K

7 :
1. .
2. .
I2C ( 4 ).
( ).

225

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