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1)
1.1)
1.2) FPGA
1.3) CPLD
2)
2.1) Elaniv System View
2.2) Xilinx Foundation Series
2.3) Advanced Design System
2.4) Altera MAX+plus II
3) Active-HDL
3.1) Active-HDL
3.2) Active-HDL
3.3)
Active-HDL
3.3.1) Active-HDL
3.3.2)
Active-HDL
3.3.3)
Active-HDL
3.3.3.1) Control Tools
3.3.3.1.1)Design Wizard( )
3.3.3.1.2)Design Browser( )
3.3.3.1.3)Workspace/design Explorer
( /)
3.3.3.1.4)Design menu
3.3.3.1.5)Library manager
3.3.3.1.6)Console
3.3.3.1.7)
3.3.3.2) Design Entry Tools
3.3.3.2.1)HDE( HDL)
3.3.3.2.2)FSM( )
3.3.3.2.3)BDE( -)
3.3.3.3) Watch/Debugging tools
3.3.3.3.1)Syntax Checking
3.3.3.3.2)Code Tracing
3.3.3.3.3)State Machine Code Debugging
3.3.3.3.4)Break Points
3.3.3.3.5)

3.3.3.5.1)List window
3.3.3.5.2)Watch window
3.3.3.5.3)Processes window
3.3.3.5.4)Call stack
3.3.3.5.5)Data flow

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1

3.3.3.4)Simulation Kernel()
3.3.3.4.1)Stimulators
3.3.3.4.2)Waveform Editor
3.3.3.4.3)Simulations macros
3.3.3.4.4)VDHL testbench
3.3.3.4.5)
3.3.3.4.6)VDHL testbench wizard
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,
, , ,
,
() .

,

, -
- HDL (Hardware Description
Language - ).
HDL ABEL, Verilog VHDL.
ABEL (Advanced Boolean Equation Language -
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. ABEL
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ABEL VHDL Verilog ,
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VHDL, - Verilog.
VHDL Ada,

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Aldec Inc.
.

1.


90- ,
,
( ).

.

. 1.1.
(39% ).
, 26%
.
,
(19%) (16%).
, :
Alcatel, IBM, Booing, Lockheed, Hewlett Packard, Fujitsu, Hitachi, Silicon Graphics, Texas
Instruments, Motorola, Rockwell, Kodak .

. 1.1


.
Xilinx. Xilinx
,
,
, .
Altera
.
5

Lattice (59.7 . USD)


CPLD .
Actel (41.6
. USD).
, FPGA CPLD.
.
1.2 FPGA -
FPGA Field Programmable Gate Array -
. FPGA -
. 1.2.
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XCV50 XCV1000 XCS40/XL XCS20/XL XCS05/XL

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200

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2.5


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57906


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()

200

80

80

80

0.35/0.5

0.35/0.5

0.35/0.5

3.3/5.5

3.3/5.5

3.3/5.5

1124022

13K-40K

7K-20K

2K-5K

1728

27648

1862

180

514

0.2
2
2.5

205

950

238

160

77

1.3 CPLD -
CPLD (Complex Programmable Logic Device 7

) . 1.3
( 9500).
9500 :
1) JTAG - ( IEEE Std. 1149.1)

;
2) / (/);
3)

:
GTS.

GCK, / GSR,

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() 18 () "36
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36 . ()

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CPLD - Xilinx
. 1.2.
CPLD -
- , ,
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PLD ( FPGA) :
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CPLD .
1) JTAG ( IEEE Std. 1149.1)
;
2) / (/);
3) : GCK, /
GSR, GTS.
/
. () 18
() "36 1

. 1.3 - CPLD

1.2
CoolRuner

XC9500

XCR3320

XCR22V10 XC9536

XC952288


()

320

10

36

288

(MHz)

100

111

100

56.6

()

5;3

5;3

5;3

5;3

100

"pin - to - pin" ()

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7.5

1000
7.5

100
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2.

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. PCAD, DesignLab OrCAD.


- :
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FPGA Xilinx (ASIC)
(SOC).
(System View) (Microsoft Office, Serenade).
MatLab.

, ,
.

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.


.

.

2.1. Elanix SystemView

SystemView,

Elanix,

, ,
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, , , QAM64. SystemView
,
(DSP)
(FPGA),
.

. SystemView Professional Edition,

. -
,
,
.
:
Communications Library 40 ,
, ;
DSP Library
,
FPGA;
12

RF/Analog Library 40
,
;
Logic Library
;
CDMA/PCS Library ,
,
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Digital
Video Broadcasting (DVB) Library
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EnTegra Adaptive Filter Library ,
;
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. ,
Xilinx, (FPGA),
Matlab, .
,
Windows 95/98 NT,
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2.2. Xilinx Foundation Series


Xilinx ,
,
, . Xilinx Foundation Series
. ()

- (Intellectual Property Cores),
, .

. Xilinx Elanix
(DSP).
SystemView Elanix
Xilinx DSP.
Foundation Series Express :
Foundation Project Manager. ()
. , ,
, ;
.
EDIF ( XNF). Xilinx
Foundation Series Express :
LogiBLOX. ,
(, , ..),
, ,
13

HDL-;
HDL- HDL Editor.
HDL. netlist
EDIF ( XVHDL).
;
Schematic Editor.

. LogiBLOX-, FSM-,
VHDL- Verilog-;
( ) State Editor.

. VHDL-.
:
- Founda-tion Logic
Simulator.
,
.
;
Constraints Editor.

;
VHDL FPGA Express.
VHDL-;
VHDL VHDL Simulator. HDL
;
Timing Analyzer.
.
:
Flow Engine
,

Xilinx;

Floorplanner.

. CLB
;
EPIC.

;
PC Hardware
Debugger. .
,
JTAG;
PROM File Formater.
14

2.3. Advanced Design System



/,

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.
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DSP Designer.
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Altera Xilinx.

RFIC Designer, :
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Circuit Envelope ..

RF Board. :
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;

;
, Cadence Mentor.

2.4. Altera MAX+plus II


MAX+plus II
. , ,
,
.
15

MAX+plus II .
,
VHDL Verilog,
Mentor Graphics, Cadence, Synopsys, Elanix.
MAX+plus II ,

.
MAX+plus II VHDL, EDIF,
Verilog. EDIF
.
-
PDS ( PLDShell, PALASM) XNF (
XACT Xilinx). ,
OrCAD, .
MAX+PLUS II 11
(. 1).
2.1
Hierarchy
Display


,

Graphic Editor
WYSIWYG

Symbol Editor


Text Editor
, AHDL, VHDL, Verilog HDL
Waveform
:
Editor

Floorplan

Editor

Compiler


Simulator

Timing

Analyzer
,
, ,
Programmer
Altera
Message
,
Processor

16

3. Active-HDL
3.1 Active-HDL
,

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.

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(
)

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Active-HDL
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Active-HDL.
. 3.1 -
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.
17

. 3.1 - Active-HDL

18


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(Behavioral model, Interpreted model)
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(Performance Model, Uninterpreted
Model) -
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(Interface Model, bus functional model) 19

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Model, Hybrid Model) - ,
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3.2 Active-HDL
, 3.1.
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1.
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2. . Active-HDL
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VHDL ,
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20

3.
3 - .
,
VHDL,
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( VHDL- )
VHDL , ,
.

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4. ( ) , ..
(Register Transfer
Level Model - RTL - model).
, , , , ..
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5. 5
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3.3
Active-HDL.
3.3.1 Active-HDL

Active-HDL. , . ,
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21

, ,
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.
Control Tools
Active-HDL
, .
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, Control Tools
( ).
Design Entry Tools
-
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Design Entry Tools ( )
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(Simulator Kernel)
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. () Debugging Tools
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(
),
().

22

3.3.2

Active-HDL

. 3.2 Active-HDL, .


Control Tools. ( 3.2).
( / ;
; ..) Design Entry
Tools.
Design Entry Tools
. VHDL ( )
23

, .
, Debugging Tools
.
Simulator
Kernel. Simulator Kernel
. ,
.
,
Debugging Tools. ,
. , Simulator Kernel
.
: 3.2, Active-HDL
() .
. 2 3:
Control
Tools .

24

3.3.3
Active-HDL


.
3.3.3.1 Control Tools

Control Tools, .

. 3.3 Control Tools

,
, . ,
,
, . ,

.
, . , ,
, Active-HDL
, ,


. Control Tools.
Control Tools :
Design Wizard, ( )
, ,
. Design Browser ( )
25

. Design Tools
.
Console () ,
Active-HDL
, Active-HDL
(
).
, .
Design Flow Manager
( )
.
(HDE, FSM, BDE)
(functional simulation)
.

Active-HDL 7.1

(Framework)

. 3.4. (Framework) Active-HDL

3.4
. (Design Menu),
.
,
Active-HDL.

3.3.3.1.1 Design Wizard ( )


- ,
.
26

Getting Started (. 3.5)


(Open existing
workspace) (Create new workspace).
,
Create new workspace.

. 3.5 -

,
, .
,
.
.
New Workspace (. 3.6)
, .
my_designs, ,
.

. 3.6.-

New Design Wizard (. 3.7)


Create an Empty Design with Design Flow (
).

27

. 3.7 -

, /
, Archive-CAD. Archive-CAD
Active-HDL
.
Create an Empty Design with Design Flow ,
, Lesson_1
. ActiveHDL 7.1 (. 3.8). ,
: Lessons, Lesson_1.
Design Flow Manager.

. 3.8.- (Framework) Active-HDL

28

. New Design Wizard


. New Design Wizard
,
. (
4 ). HDL
-.

3.9- .

3.3.3.1.2 (Design Browser)



. - ,
. ,
, .
.
- , .
,
.

.
:

29

3.3.3.1.2.1 (Files)
Files .
. .
HDL ,
:

Files ,

. ,
, .
Files ,
.
, ,
,
, , .
. ,
,
.

. 3.10 -

:
30

VHDL Source Code (vhd;vhdl;vhq;tvhd;vho;vhm;vhi), configurations, and


testbenches
Verilog Source Code (v;vei;veo;vo;vm;vmd;vlb;vlg) and testbenches
C/C++ Source Code (cpp;c;h)
Verilog Value Change Dump (.vcd)
State Diagram (.asf)
Block Diagram (.bde)
BDE Symbol (.bds)
Waveform File (.awf)
List File (.lst)
Macro (.do)
SDF File (.sdf, .sdo)
EDIF Netlist (.edf, .edn, .edo)
Viewlogic Schematic (.1)
TCL Script (.tcl)
Active-CAD Test Vector (.asc)
Active-CAD Project (.pdf)
XNF Netlist (.xnf)
Basic Script (.bas)
Perl Script (.pl)
Drawing (.afc)
Bitmap (.bmp)
HTML Document (.htm)
Design Management Overview
Text (.*)
External file
-
. ,
, Files,
.
. , -,
Files.
3.3.3.1.2.1 Structure Tab
Structure Tab .
.
,
, . ,
:
;
;
31

(Value).
(, () , , , ,
), ,
. ,

Structure.

. 3.11 - (VHDL)

, , .
,
, Open .
Structure Tab
.
3.3.3.1.2.2 Resource Tab
Resource Tab :
- ,
- , ,

Waveforms - Waveform editor

, ,
Resources.
.

32

3.3.3.1.3
Workspace/Design
/ )

Explorer

Workspace/Design Explorer
, ,
. ,
, ,
.
Workspace/Design Explorer , Open Workspace
File.
/My_Designs/Samples_61/ folder, .

. 3.12 - Workspace/Design Explorer

/ Workspace/Design
Explorer . / .
Workspace/Design Explorer .
, ,
/ . Workspace/Design Explorer
.
- .
.
/ ,
.

33

3.3.3.1.4 Design Menu


The Design Menu
. , ,
.
, , , design project.

. 3.13 -

Design Settings .
:
General () -
HDL /
VHDL/Verilog - VHDL
Verilog ;
SDF -

Simulation () -
VHDL Verilog, VITAL
SDF,
.

34

Trace/Debug (/) -
;
Verilog PLI - DLL PLI;
EDIF

,
;

Code Coverage/Profiler
( / ) Code Coverage Profiler;

. 3.14 - Design Settings

Design Backup Revision


( ).
, .

.

,
, .. Active- HDL
. ,
.
.
, Active- HDL
. ,
Restore Revision,
. , ,
. , ,
Restore Revision.

35

3.15 - Backup Revision

Create Library Design New Library


Wizard.
.
VHDL .

.

36

3.3.3.1.5 (Library Manager)


,
Active-HDL.
:
.
, .
.
.
.
.
.
Library Manager:

. 3.16 - Library Manager

.
.
:

- ;

- . :
- (R/W) - (R/O));

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;

-
;

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37

( )
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Unit Name. ,
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VHDL,
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: (
VHDL Verilog), Netlist (
EDIF netlist);

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Verilog, EDIF;

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VHDL, Verilog, EDIF;

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..
- VHDL,
, ;
38


.
.
3.3.3.1.6 (Console)
,
Active-HDL
,
Active-HDL.

, ,
. Console ,
. ActiveHDL, ,
GUI () .

3.17 -


Active-HDL
, , , , ..
help <macro_command>
Active-HDL .
3.3.3.1.7
Active-HDL

-,

.
,
, , , ..
- ,
, Active-HDL.
,
COUNTER8.VHD TESTBENCH.VHD,
TESTBENCH_ARCH .
,
Waveform Viewer .
39

, - ,
.

- FUNCTIONAL.DO , :
# rebuild whole project
savealltabs
quiet on
acom counter8.vhd
acom testbench.vhd
asim testbench TESTBENCH_ARCH
# initialize simulation
wave
wave CLK
wave RESET
wave CE
wave LOAD
wave DIR
wave DIN
wave COUNT
run -all
endsim
quiet off


, ,
, ..
, GUI
. -
, .

, ,
, .
.

40

3.3.3.2 Design Entry Tools


Active-HDL,
Control Tools
Design Entry Tools.
Design Flow Manager
.
(HDE, FSM, BDE)
(functional simulation). ,
(options). . 3.18 ,
.

. 3.18 Design Entry Tools


1. HDE

(Hardware Description language Editor), ,


VHDL,
Verilog SystemC;

2. BDE (Block Diagram Editor), ,

;
3. FSM (Finite State Machine), ,

.

Design Entry Tools. . 3.18

.
41

.
VHDL .
BDE ,
VHDL, Generate HDL code.
(.. HDL ) Code2Graphics.
, ,

Watch/Debugging Tools.
HDE, BDE FSM.
3.3.3.2.1 HDE ( HDL)
HDL , HDL,
, , , .
HDE HDL Editor Design Flow Manager
. , ,
. ,
. Active-HDL
VHDL/Verilog,
New Source File Wizard

. 3.19 - HDE

3.3.3.2.1.1 New Source File Wizard


Active- HDL VHDL Verilog, Add
New File Design Browser. , , :
Block Diagram (-)
State Diagram ( )
VHDL Source Code ( VHDL)
42

Verilog Source Code ( Verilog)


Add Existing File ( )

. 3.20 -

:
Block Diagram Wizard ( -)
State Diagram Wizard ( )
VHDL Source Code Wizard ( VHDL)
Verilog Source Code Wizard ( Verilog)

. 3.21 - - Wizards

, .
,
.
1. ,

;
2. , -
( BDE FSM);
3. , .
;
43

4. .

. 3.22 - New Source File Wizard

3.3.3.2.1.2 HDL Editor


. 3.24 HDE Tools (
).

.

. 3.23 - Undock Window

,
. ,
. ,
, (
).

44

Active-HDL
(, group),
, . HDL Editor
, .

. 3.24 - HDE Tools

,
, .
,
Generate Structure..
, :
(. 3.25).

. 3.25 - VHDL- ()

45

, entity ,
port , ,
() . architecture -
. , (
) ( Preferences
Tools).
(
), Remove groups.

, Create group Remove groups EH.
- , . 3.25 ().
:

. ,
.

, ,
,
, , .

. 3.26 - VHDL-

Active-HDL ,
. HDL Editor
Autoformat text EH.
. 3.26 -. ,
(Indent) (Outdent),
.

46

. 3.27- VHDL-

VHDL-
. HDL Editor
Comment, .
, ,
Comment.
(.3.27 -). ,

Uncomment (. 3.27 -).
HDE
Tools (. 3.24). Column selection (
) . . 3.28 ,
.

. 3.28 -

Column selection ,
D0, D1, A, Y (. 12) .
. Comment ,
. ,
.

47

3.3.3.2.1.3 Language Assistant ( )



HDL. , .
:
Code Auto Complete - HDL, ,
;.
Language templates- .
Simulation templates- ,
, ..
Synthesis templates-
, , , , ..
Tutorial- ,
, , ,
.
User templates- , ,
.

3. 29 - Language Assistant

,
Active-HDL, HDE. ,
( )
.
,

Use
. HD
, .


, Language Assistant,
.

48

. 3.30 -

Language Assistant
.
.
, .
.
. ,
, . , ,
, .
Color Preferences ( ).
HDE ,
, . ,
, ,
Preferences | Environment | Appearance.
, ,
, .
, HDL.
HDE ,
, .

49

. 3.31- Preferences

HDE ,
Compile.
HDE , .

.
HDE
. :
- ,
- ,
- HDE,
- ,
- ,
, .
,
- ,
- .
VHDL, IF .. THEN
.
,
-
,
50

- ( )
, . , ,
. ( ,
),
- ,
.

,
:

, ,
.
,
HDL,
.

. 3.32 - HD, .

HDE
. HDE HDL,
:
-
;
. .

51

HDL
VHDL Verilog .
.
CASE:

. 3.33 -

3.3.3.2.2 FSM ( ).
FSM
.
.
.
,
.

. 3. 34- FSM

FSM
. , (FSM)
52


. FSM :
;
, ;
, ;
:
( );
( );
.
,
.
, , .. .
3.3.3.2.2.1 New Source File Wizard ( )
New Source File Wizard,
.
. ,
. ,

,
Add New File, ,
.
Add New File, .
3.3.3.2.2.2 State Machine Toolbars ( )
FSM.
State Machine,
:









,



53

. 3.35- State Machine Toolbars

FSM .
, .
,
. ,
.
,
Properties .
, ,
.
,
, , ..

. 3.36- Machine Properties

FSM -
HDL . ,
Generate HDL Code FSM Generate HDL code,
FSM.
, View HDL Code FSM. ,
, , . ,

54

3.3.3.2.3 BDE ( -)
BDE .
-
VHDL .
,
(DRC). ( HDL,
-).

. 3.37- BDE

BDE, ,
, -, , , ..,
, ,
.
- ,
, ..;
- - .
-
. .
- ,
: , , , ..

55

- , ,
.
- , ,.
- .
- Symbols Toolbox ( ),
. VHDL Verilog
.

. 3.38 - Symbols Toolbox

,
.
- , ,
, , . ,
, Push
.

56

Code2Graphics ( )

. 3.39 -

,
, .
, , , ,
.. , VHDL ( Verilog)
,
.
,
Push. ,

:
, BDE
, FSM
VHDL, Verilog, .., HD

57

. 3.40 -

58

3.3.3.3 Watch/Debugging Tools .


VHDL Active-HDL.

, .
, VHDL ,
,
. ,
, Active-HDL
.
VHDL :

Syntax Checking ( )
Compile.

Code tracing ( ) VHDL -



, .

Value verification ( ) - ,
Watch List.

3.3.3.3.1 Syntax Checking ( )


Active-HDL VHDL.
Compile .
:




,
VHDL, . ,
,
. ,
, .

59

. 3. 41- Compile

Compile VHDL
VHDL 03 LRM. ,
,
LRM.
, 100-
, , Compiler
Preferences.
Preferences .
Debug, . Document Type
VHDL .
Bring active source window to top, ,
. ,
., . . Separate view (
)
Single view (
).

60

. 3.42 - Preferences.

Active-HDL
VHDL . :

;
VHDL ,
;

3.3.3.3.2 Code Tracing ( )


.
,
. Active-HDL Waveform Editor,
.
.
Active- HDL
.
VHDL --.
, :
Trace into - VHDL.
, .
Trace over - - VHDL.

, , ,
.
Trace out - VHDL,
61

. ,
.
Trace over transition - VHDL,

.
,
Simulation Trace. Trace over
transition .
3.3.3.3.3 State Machine Code Debugging ( )
, Trace over Transition Simulation
.
Active-HDL ( FSM)
. , FSM
,
, , . Trace
, ,
. ,

VHDL , .

. 3. 43 - FSM

3.3.3.3.4 Breakpoints ( )
Active-HDL - Breakpoints
( ) VHDL.
, (-).

Watch.
62

VHDL
,
,
, ..

. 3. 44 -

Breakpoint Editor ( )
. Breakpoint Editor
Code breakpoints ( ).
,
, ,

,
.
Breakpoint Editor

.
, ,
. ,
: Name () , Condition (,

), Value ( ). Condition
:

Event () - ,

Value () - ,

Transaction () - ,
.

,
Show code Signal Code breakpoint. -

.

63

. 3.45 - Breakpoint Editor

3.3.3.3.5 .

, . ,

,
. ,
, Waveform Editor,
.
3.3.3.3.5.1 List Window ( ).
List Window ,
.
. - .
.
.
:
. (
);
. ( ).

64


. 3.46 - List
3.3.3.3.5.2 Watch Window ( ).
,
Watch . Watch
( ) .

. 3.47- Watch.
, :

names ;

types of the selected objects- ;

current value- ;

last value - ;

, ,
Design Browser .
VHDL.

65

3.3.3.3.5.3 Processes Window ( )


Processes Window

. ,
.

. 3.48 - Processes

,
, . ,
. :




, ,
, (
line__25 ( __ 25)).
, Process,
:
Ready ()- ,

Wait ().

Processes :


;
66

,
;

, ,
.

3.3.3.3.5.4 Call Stack ( ).


Call Stack - ,
( ) ,
. ,
, .

- ,
,
, .
:
.
, ,
.
,
Processes, ,
. Call Stack
.

. 3.49 - Call Stack

3.3.3.3.5.5 Data Flow ( ).


Data Flow- ,

, ,
. -
,
,
, .
:

67

,
.
,
.
, -
.

. 3.50- Data Flow-1

,
.
. .
,
Dataflow.

. 3.51 - Data Flow-2

.
Dataflow .

68

3.3.3.4 Simulator Kernel ()


,
. Active-HDL
:
1. ;
2. VHDL Testbench ( ),

Testbench Wizard;
3. VHDL Testbench ( ),

;
4. ;
5. , ;
6. ( Active-CAD).

,
,
. ,

,
.
3.3.3.4.1 Stimulators ().

Waveform Editor ( )
, Stimulators.
,
. :
-Value stimulators ( )
.
, .
, ,
.

-Formula stimulators ( )
, ,
, .
69

0 0, 1 10 ,
'0' =0 '1' 10 .
Hotkey stimulators ( )
.

. .
, 'R'
reset () , , R .

Clock stimulators ( ) ,
. Clock stimulators
, , ..
Counter stimulators ( ),
.
.
Predefined stimulators ( )
, ,
.
Custom
stimulators
(
)
,
,
Waveform Editor .

Waveform Editor .

. 3.52 - Stimulators

70

:
o VHDL

;
o ;
o ,

, , ..;
o

Active- HDL
VHDL;

3.3.3.4.2 Waveform Editor ( ).


Waveform Editor
,
, ,
.
,
.

Test Bench Wizard (
, ),
VHDL, .

71

. 3.53 -

.
Waveform Editor

. , ,
Waveform Editor .

, .
,
. ,
.

.3.54 - .

3.3.3.4.3 Simulation Macros ( ).


. Active-HDL
,
.
,
.
,
Waveform Editor ..

72

. 3.55 -

, .
,
.
,
Active-HDL.

,
. , ,
, , Test
Bench . - ,
, , ..
:
, ;
;
;

o ;

o .

. 3.56 -
73

3.3.3.4.4 VHDL testbench ( VHDL).


VHDL testbench - VHDL,
VHDL. VHDL
, , ,
.
, , ,
. VHDL testbench
VHDL (
VHDL), (Unit Under Test )
.

. 3. 57 - Testbench

VHDL
. , VHDL,
,
.
,
.
Test Bench Wizard.
.
Test Bench Wizard ,
. -,
,
. , waveform
.
Test Bench
.
, ,

/.

74

. 3.58 - Test Bench Wizard

VHDL, .
VHDL, ,
VHDL.
. VHDL,
Active-HDL,
. Language Assistant
VHDL.
:

VHDL VHDL;

:
o ( VHDL)

,
.

o VHDL,

.
3.3.3.4.5 .
75

, ,
.
,
. ,
, .
Active-HDL 15
.
,
.
3.3.3.4.5.1 .
,
.
, .
,
Unit Under Test (UUT).
.
-
Waveform Editor ,
Stimulators. :
Value -
Formula -
Hotkey -
Clock -
Counter -
Custom
Predefined

76

. 3.59

:
1. Override () -

FORCE.
2. Deposit () - ,
(,
P1 P2 () FORCE.
3. Drive ( ) - ,
, FORCE.
,
std_logic.

. 3.60-

3.3.3.4.5.2 Value ().


Value
, (, '1', 0). ,
(in, out, inout, buffered),
.
, ,
.
2, 8, 10 16.

77

Stimulator Waveform Editor


.

. 3.61 - Value

3.3.3.4.5.3 Formula ().


Formula ,
-. ,
. :
value time [,value time] [-r period] ( [
] [-r ])
, -r
. - ps
(). , :
ps -
ns -
us -
ms
:
0 0, 1 10, 0 20 defines a logic "1" that starts at 10 (ps) and ends at 20 ps
0 0, 1 10, 0 20 1, 10 ()
20 ,
1 0, 0 5 ns, -r 20 ns defines a pulse wave with period of 20 ns and 25% duty cycle
1 0, 0 5 ,-r 20 20 25%-

, ,
Stimulator Waveform Editor "formula" .
,
.
78

. 3.62 -

3.3.3.4.5.4 Hotkey ( ).
Hotkey

. ,
, ,
.
, 'R' reset (),
,
R .

. 3.64 - Hotkey

, , .
'0' '1'. , ,
Sequences Simulators/Hotkeys.

79

. 3.65 - Hotkey

3.3.3.4.5.5 Clock ().


Clock ,
. Clock
, , . Clock
Stimulator, .

. 3.66 - Clock

3.3.3.4.5.6 Counter ().


Counter,
. ,
, .
:

.
,
,
, .
Waveform Editor
.

80

. 3.67 - Counter

3.3.3.4.5.7 Custom ().


Custom ,,
,
Waveform Editor ,
. Custom ,
, ,
Waveform editor, Hotkey,
Formula .
Custom
.
Hotkey Formula .
Stimulator
CS ( ).

. 3.68 - Custom

3.3.3.4.5.8 Predefined ().


Predefined
/ , .

81

. 3.69 - Predefined

,
.

.

. 3. 70 - Predefined

-
.
.
, ,
.
Active-HDL
,
Active-HDL.
-
,
. , ,
, , ,
82

. ,
,
,
( ,
, ..) (FPGA, ASIC, ..).

.
, ,
..

. 3.71- The Waveform Editor

3.3.3.4.6 VHDL Testbench ( VHDL).


VHDL VHDL,
,
VHDL. , VHDL Testbench -
, Unit Under Test (UUT)-( )
,
. VHDL
:
1. Stimulus Generator ( ) -

Test Vector (
;

UUT

2. Unit Under Test (UUT)-( )

;
3. Verifier ()-


.
.

3.72- .
83

,
,
.
.
3.3.3.4.6.1 Off-line Configuration ( )

, ( ,
) .

.
UUT
. VHDL
. ,
(
),
( , ).

3. 73-Off-line Configuration .

3.3.3.4.6.2 On-line Configuration ( ).



.
.


, .
,

84

, ,
.

. 3.74 On-line Configuration

3.3.3.4.6.3 Adaptive Configuration ( ).


- - ,

VHDL. ,
,
.
UUT .
: ,
UART PCI.

. 3.74 -Adaptive Configuration

3.3.3.4.7 VHDL Test Bench Wizard ( VHDL).


, Test Bench
Wizard, VHDL.

, .

. , Bench
Wizard ,
.
85

Test Bench Wizard, Generate Test Bench


Tools. Entity ,
Next.

.3.74- Test Bench Wizard -1

, :
waveform
.
Next.

.3.75- Test Bench Wizard -2

,
... ,
.

86

.3.76- Test Bench Wizard -3

, .
- . -
, -
, ,

.
Finish,
.

.3.77- Test Bench Wizard -4

Test Bench Wizard


,
,
.
87



, .

, ,
,
.
- , .
,
.
.
Active-HDL

(),
,
.
Active-HDL
, .

. Active-HDL
,
,
.

,
. . ,
VHDL,
.


.

88


1. Active-HDL 7.1. http://www.kit-e.ru/articles/circuit
2. Active-HDL http://www.aldec.com/

3. .., .. .-.:
., 1990. -335 .
4. .. .-.:
., 1987.-182 .
5. .. : .
. -.: - , 2000.-359 .
6. .., www.compitech.ru

7. .., .. ..: ., 2003.-825 .


8. . . . -.: ., 1985.-424 .
9. .. : .
. -.: - , 2002.-389 .
10.. . .-.: , 1992.-623 .
11. ., . 44

: . . -.: , 1990.-288

89


1

Active HDL 7.1
:
Active HDL 7.1.
.
( , ).
HDE BDE.
.
1.
Active - HDL .1.1.

. 1.1 - Active - HDL

1.1 Active -HDL:


, , .
,
.

1.1 - , ,


. -
90

1 .
, : , , .
:

.1.2


"S" (), "R"(), .
"S", "R"
X ,
"Q"
. "Q".

"C" (Clok- ), .
.
RS- S R
Q=1 S=1 R=0 Q=0 S=0 R=1 S=R=0
S=R=1 - (
) . . Q

. 1.3 RS-

1.2
.
,
,
. ,
, , .
RS-.

Waveform Editor,
New Waveform
Standard. Waveform
91

, . ,
.
Waveform Editor
, .
, .
Add
Signals. .
: D0, D1, A, Y, F1, F2, F3.
Shift Ctrl ,
, D0, D1, A Y. Add
Waveform Editor (. 2)
Add Signals ( Close).

. 1.4 ,


Stimulators Stimulators.
.
D0, D1 A .
.
.
Clock.
Stimulators (. 3). Signals
D0, Type Clock
(Frequency) 10 . Apply ,
, D1.

. 1.5 D0, D1 A

92

5 . ,
A 1 . ,
Stimulators ( Close).

( Initialize Simulation
Simulation). Value
(. 4). Y U (Uninitialized
).
mux2_schema.bde, ,
.

. 1.5

(. 5).
Run For Simulation.
F5. , ,
, .

. 1.6

100 ns, .
. .
,
.
.

,
Run Until Simulation.
93

(. 5). (. 6),
, 1.2us (1,2 ).

. 1.8

Run
(Alt+F5). ,
(transactions) .
(Clock),
, ,
TIME'HIGH.

, Break ,
Restart . , Run
.
,
, (Console).
: run 1200ns Enter.
(. 7).

. 1.7 mux2_schema

, A
, D0. A '1'
( 500 ns), D1.
() .
.
Save.
Waveform Editor 1.awf.
94

,
mux2_schema.awf.
Active-HDL 7.1
, . (
Restart) New List ( ). list1,
D0, D1, A Y ( Add
Signals ). ,
(. 8).

. 1.9. ()

(, , ),
, ,
.

95

:
1. ,
Active - HDL .
2.
(New Design Wisard).
6. (New Design Wisard)
.
7. Design
Flow Manager. .
8. HDE (Hardware Description
Editor- ) BDE (Block Diagram Editor- ).
9. RS HDE.
VHDL ,
RS -. : 2 R S 2
U INV_U STD_LOGIC.
10. .

11. .
.
13. RS BDE,
.
14. ( )
( VHDL).
Generate HDL Code,
Diagram.
15. : RS ,
HDE VHDL-.
16. .

96

17. .
.
18. .

1.
2.
3.
4.
5.
6.
7.


Active - HDL.
(New Design Wisard).
Active - HDL
?
(Design Browser)?
?
VHDL?
ActiveHDL?


1. ;
2. Active - HDL ;
3. ;
4. 2- , ,
HDE BDE;
5. 2- ,
, HDE BDE ;
6. .

97

2
:

:

Active-HDL,

.
:

,
.
time.


. VHDL :
Y( )<= transport ( )after ;

, ,

.

,
.
, ,
.
:
Y( )<= inertial X( ) after ;
,
, ,
:
Y( )<= reject inertial X( ) after
;
,
- .
98

:
1. 1
.
2. , ,
(entity) VHDL,
HDE ( ).

2.1
3. VHDL
( 6 ns, 2 ns).
4. :
99

;
)
.
5. , ,
5 ns .
6. .
7. ,
15 ns.
8. .
9.


100

1. , ?
2. ?
3. VHDL?
4. VHDL.

1.

2.
3.
4.
5.
6.
7.
8.


;
,
Active - HDL;

;
VHDL - ;

(.4), ;
. 5, 7 ,
;
.

3
:

WAIT
101

:
wait Active-HDL.
.
:
.


, .
VHDL wait,
() .
, process
wait.
, wait.
wait,
process:
wait ,
. , ,

.
wait on _; - ,
- .
wait for const__time; -
wait.
wait until _; - (
1), .
, ,
wait. :
wait on _ until _;

wait until _ for const__time;.

:
LabWait, .
LabWait.
CLK ( 50
), Aout, Bout.
102

, Wform1,
.

. 3.1-

wait for CLK


( )
Pr_CLK.
10 ns.
Pr_A
wait on.
103

Pr_B
wait until.
wait ,
.

Wform1. Waveform Compare Waveforms.
"Open". Wform1.awf
"Open".
, Wform1.awf. -
(.1, 3.2),
(.2, . 3.2 ).
(.3, 3.2).
, .

. 3.2-

.
( ),
. , , "Remove
Difference Marks".
Pr_ wait for
30 ns.
,
Wform2.awf.
wait for, .10,
20 ns.
.
Wform2.awf.
, .

1. VHDL
.
2. wait
104

?
3. wait , ?
4. wait?
5. ,
.


1. ;
2. wait;
3. LabWait
(.3);
4. wait (. 5, 6, 7);
5. ( .9);
6. ( .14);
7. .

4
:

:
.

VHDL.
:
1. VHDL
105

, .
VHDL
.
:
Loop_: loop
_
end loop Loop_Label;
Loop_ , .
.
Exit:
,
, -
. exit.
exit loop_ when _;
:
exit;

.
next:
,
loop.
next when _;
While:
loop_: while _ loop
_
end loop;
(true).
(for):
loop_: for in loop
_
end loop;
VHDL ,
. .
, ,
.
, , .
2. VHDL
.
8- :
8- DATA_IN (7 downto 0) STD_LOGIC_VECTOR
;
CLK;
WE;
RE ( STD_LOGIC).
106

, 8- DATA_OUT (7 downto0)
( STD_LOGIC_VECTOR).
:
1)
(ZZZZZZZZ).
, ,
, .
2) WE = 1 RE = 0, .
3) WE = 0 RE = 1, ,
.
4) WE RE
.
5) CLK.
8- :
DATA_IN STD_LOGIC ;
CLK;
WE;
RE ( STD_LOGIC).
, 8- DATA_OUT (7 downto0)
( STD_LOGIC_VECTOR).
:
1)
(ZZZZZZZZ).
2) WE = 1 RE = 0, ,
DATA_IN DATA_OUT(0),
DATA_OUT(0) DATA_OUT(1) .
3) WE = 0 RE = 1, ,
.
4) WE RE
.
5) CLK.
.
1.

STD_LOGIC_VECTOR (7 downto 0).


2.
CLK.
3.
(for).
4. (7-) (1-).

107

:
1. .
2. VHDL - 8- .
3. ,
, , ,
.
4.
.
5.
5. VHDL - 8- .
6. ,
, ,
.
7.
. ,
8.
8. .

108


.
.
VHDL.
VHDL ?
VHDL ?
(.) ,
wait?

;
, VHDL;
VHDL -,
;

.

109

5
:
ACTIVE-HDL.
: .

ACTIVE-HDL.
:
()

(. 7.1),
.
, , ,
, .
:
1. :
1.1 (), . 7.1
(0, 1, 2) .
1.2 , . 7.1. (R0, R1, R2)
- .
1.3 R
CLK , "0"
"1", .
.

110

. 5.1 -
2. :
2.1. 0 ,
- .
2.2. R.
2.3. R ( R1) ""
"", , ,
0 R1.
, , .
2.4.
( )
;
2.5. R , .2.1,2.2
C0 - 2 ,
2.3.

:
111

1. (FSM
Editor) Active - HDL.
2. ,

(. ). 15 (0 . 9,
'+''-' '/' '*', '=').
3. (. ).
4. (
File\NewDesign\FSM Diagrame).
5. New Design Wizard New Source File Wizard
.
6. .
6.1. FSM State Editor,
(.1, . 7.2)
(S0, S1.),
.2.
6.2. FSM State Editor,
(.2,
.7. 2);
6.3. ,
R "1",
(.3, .7. 2)
FSM State Editor.
6.4. (, , )
.2.
(S0),
"Properties"
.
6.5.
( S1 . Sn (.4, . 7.2), ( 5, 6, .
7.2) ).
6.6. (. 7, . 7.2).

"Properties", .
7.
VHDL, .
8. VHDL .
9. .
10. .

112


1. .
2.
New Design Wizard New Source File
Wizard?
3. ?
4. ?
5. VHDL
-?
6.
?
7. , ,
VHDL -?
113


1. ;
2. 15
;
3. (
.2);
4. ;
5. ;
6. VHDL -
;
7. ;
8. .

114

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