NAME: Vikash Gurjar

ROLL NO: 21104111

EXPERIMENT: 4(a)
AIM: Implement 4:1 & 8:1 Mux using data and Behavioral modeling.
SOFTWARE: Xilinx

4x1 mux
Using data flow modeling:
`timescale 1ns / 1ps
module mux4(
input A0,
input A1,
input A2,
input A3,
input S0,
input S1,
output OUT
);
assign OUT= (~S1&~S0&A0)| (~S1&S0&A1)|(S1&~S0&A2)|(S1&S0&A3);
endmodule
RTL:
4:1 mux Using Behavioral modeling.
`timescale 1ns / 1ps module
mux4x1(s,inp,out);
input[0:1] s;
input[0:3] inp;
output íeg out;
always@(*)
begin
case({s[1],s[0]})
2'b00: begin
out=inp[0];
end
2'b01: begin
out=inp[1];
end
2'b10: begin
out=inp[2];
end
2'b11: begin
out=inp[3];
end
default: begin
out=1'b0;
end
endcase end
endmodule
RľL:
4:1mux Simulation :
`timescale 1ns / 1ps
module muxg4tb( );
reg s1,s2,A0,A1,A2,A3;
wire out;
mux4 uut(s1,s2,A0,A1,A2,A3,out);
initial
begin
A0=1'b0;
A1=1'b0;
A2=1'b0;
A3=1'b0;
s1=1'b0;
s2=1'b0;
#100 $finish ;
end
always #1 s1=~s1;
always #2 s2=~s2;
always #3 A0=~A0;
always #4 A1=~A1;
always #5 A2=~A2;
always #6 A3=~A3;
always @ (A0 or A1 or A2 or A3 or s1 or s2)
$monitor ("At time=%t, Output=%d",$time,out);

endmodule

WAVEFORM:

8:1mux
Using data flow
`timescale 1ns / 1ps
module mux8(
input A0,
input A1,
input A2,
input A3,
input A4,
input A5,
 input A6,
input A7,
input S0,
input S1,
input S2,
output OUT
);
assign OUT=(~S2 &~S1 &~S0 &A0)|
(~S2 &~S1 &~S0 &A0)|
(~S2 &~S1 &S0 &A1)|
(~S2 &S1 &~S0 &A2)|
(~S2 &S1 &S0 &A3)|
(S2 &~S1 &~S0 &A4)|
(S2 &~S1 &S0 &A5)|
(S2 &S1 &~S0 &A6)|
(S2 &S1 &S0 &A7);
Endmodule

RTL:

8:1 mux Using Behavioral modeling.

`timescale 1ns / 1ps

module mux8(

input D0,

input D1,

input D2,

input D3,

input D4,

input D5,

input D6,

input D7,

input S1,

input S2,

input S3,

output reg OUT

);

always@(*)

begin

case({S1,S2,S3})

3'b000: OUT=D0;

3'b001: OUT=D1;

3'b010: OUT=D2;

3'b011: OUT=D3;

3'b100: OUT=D4;
 3'b101: OUT=D5;

3'b110: OUT=D6;

3'b111: OUT=D7;

default: OUT=1'b0;

endcase

end

endmodule

RTL:

8:1 mux Simulation:

module mux8tb(

);

reg D0,D1,D2,D3,D4,D5,D6,D7,S1,S2,S3;

wire OUT;

mux8 uut(D0,D1,D2,D3,D4,D5,D6,D7,S1,S2,S3,OUT);

initial

begin

D0=1'b0;

D1=1'b0;
 D2=1'b0;

D3=1'b0;

D4=1'b0;

D5=1'b0;

D6=1'b0;

D7=1'b0;

S1=1'b0;

S2=1'b0;

S3=1'b0;

end

always #1 D0=~D0;

always #2 D1=~D1;

always #3 D2=~D2;

always #4 D3=~D3;

always #5 D4=~D4;

always #6 D5=~D5;

always #7 D6=~D6;

always #8 D7=~D7;

always #9 S1=~S1;

always #10 S2=~S2;

always #11 S3=~S3;

always@(D0 or D1 or D2 or D3 or D4 or D5 or D6 or D7 or S1 or S2 or S3)

$monitor("At time =%t, output=%d",$time,OUT);

endmodule
Waveform:

EXPERIMENT: 4(b)
AIM: Implement 16:1 Mux using 4:1 mux
SOFTWARE: Xilinx
16:1 mux using 4:1 mux

module mux_4to1 (

input [3:0] data_in,

input [1:0] sel,

output reg out

);

always @(*)

begin

case(sel)

2'b00: out = data_in[0];

2'b01: out = data_in[1];

2'b10: out = data_in[2];

2'b11: out = data_in[3];

 default: out = 1'b0;

endcase

end

endmodule

module mux_16to1 (

input [15:0] data_in,

input [3:0] sel,

output wire out

);

wire [3:0] sel1, sel2, sel3;

wire [3:0] sel1_inv, sel2_inv, sel3_inv;

wire [3:0] mux_out1, mux_out2, mux_out3;

assign sel1 = sel[3:2];

assign sel2 = sel[1:0];

assign sel3 = 4'b1111 - sel;

mux_4to1 mux1(.data_in(data_in[3:0]), .sel(sel1), .out(mux_out1));

mux_4to1 mux2(.data_in(data_in[7:4]), .sel(sel2), .out(mux_out2));

mux_4to1 mux3(.data_in(data_in[11:8]), .sel(sel3), .out(mux_out3));

mux_4to1 mux4(.data_in(data_in[15:12]), .sel(sel), .out(out));

endmodule

RTL:

16:1 mux using 4:1 Simulation:

`timescale 1ns / 1ps

module tb_mux_16x1;

reg [15:0] data_in;

reg [3:0] sel;

wire out;

mux_16to1 UUT (

.data_in(data_in),
 .sel(sel),

.out(out)

);

initial begin

data_in = 16'b0000_0000_0000_0001;

sel = 4'b0000;

#10;

if (out !== 1'b1) $display("Test case 1 failed!");

data_in = 16'b0000_0000_0000_0010;

sel = 4'b0001;

#10;

if (out !== 1'b0) $display("Test case 2 failed!");

data_in = 16'b0000_0000_0000_0100;

sel = 4'b0010;

#10;

if (out !== 1'b0) $display("Test case 3 failed!");

data_in = 16'b0000_0000_0000_1000;

sel = 4'b0011;

#10;

if (out !== 1'b0) $display("Test case 4 failed!");

 $finish;

end

endmodule

waveform: