1

681.32 (07)

4683-1

232

210106, 230201, 230101

2010

2
681.32 (076.5)
: .., ..
. . 1. : - , 2010. 64 .
,
-
. ,
.
,
.


CUPL WinCupl (Atmel).

CPLD FPGA Quartus II
- , .
210106 , 230201 ,
230101 , ,

, , . .
. 12. . 37 . .: 21 .

, . . , .
, 2010
.. , 2010
.. , 2010

1. 1.


WINCUPL
WINSIM ....................................................................................................................... 4
1.1. .............................................................................................. 4
1.2. .............. 4
1.3. CUPL ............................................................................ 6
1.4. Winupl.................................................................... 19
1.5. ............................................................ 28
1.6. .............................................................................. 33
1.7. ........................................................................... 33
2. 2.
-
QUARTUS II (ALTERA)
VHDL- -
........................................ 34
2.1. ............................................................................................ 34
2.2. ............................................... 34
2.3. ............................. 38
2.4. 8- -
VHDL ................................................................................................................. 40
2.5.
VHDL ...................................................................................................................... 47
2.6. .............................. 48
2.7. ........................................................................... 49
................................................................ 50
1.
1 .......................................................................... 52
2. COUNT10.PDF............................. 55
3.
1 .......................................................................... 57
4. VHDL- ............................. 62

4
1. 1.



WINCUPL WINSIM
1.1.

() CUPL.
WinCupl, .

WinCupl,
WinSim, .
.
1.2.
CUPL (Universal Compiler
for Programmable Logic), ,
[1, 5].
, .
,
( , ),
, .
. 1.

- , .
( ) [3], ,
( ) ( ),
.
, ..
.

5
,
CUPL.

PAL22V10 , ATF1500 Atmel [710].

( .pld) WinCupl. , .
, , .
:
.doc, .lst .jed. , . ,
, ,
(fuse), .
.lst
,
(.pld). .jed .
Jedec
(SPLD, CPLD).
,
.
WinCupl WinSim. . ,
, . , .
. . cupl.dl. . . ,
. , ( .doc), , -

6
( .sim).
. , [5, 6].
.
, .
. . . , .
1.3. CUPL
CUPL (Universal Compiler for Programmable Logic) Logical Devices, Inc(www.logical-devices.com)/ Atmel WinCupl [5, 6]. . 1.1 .
1.1
CUPL

b0
Binary
0

B1101
Binary
13

O663
Octal
435

D92
Decimal
92

hBA
Hexadecimal
186

O[300..477]
Octal (range)
192..314
()

()

H7FXX

Hexadecimal
(range)

32512..32767

4
: NOT, AND, OR XOR, .1.2.
. , .1.3 .

7
1.2
CUPL

NOT
AND
OR
XOR

!
&
#
$

!A
A&B
A#B
A$B

1
2
3
4

1.3

A3 & A2 & A1 & A0

B3 # B2 # B1 # B0
C3 $ C2 $ C1 $ C0

[A3, A2, A1, A0]:&

[B3..B0]:#
[C3, C2, C1, C0]:$

CUPL ( ) (** - ( - ) ( -
)), (* - 2), (/ -
2), , . (. 1.4).
1.4

CUPL

**

2**3

Exponentiation

2*I

Multiplication

4/2

Division

9%8

Modulus

2+4

Addition

4-I

Subtraction

FIELD, -

8
. , ADDRESS, 1
:
FIELD ADDRESS = [A7, A6, A5, A4, A3, A2, A1, A0];

MODE,
:
FIELD Mode = [Up, Down, Hold];

Up, Down, Hold , MODE.

mode:<>. , Up, 1,
Down Hold 0 mode:4.
, , , .
, .
FIELD input = [in3..0];
FIELD output = [out3..0];
TABLE input => output {
0=> 00; 1=>01; 2=>02; 3=>03;
4=>04; 5=>05; 6=>06; 7=>07;
8=>08; 9=>09; A=>10; B=>11;
C=>12; D=>13; E=>14; F=>15; }

CUPL,
(. 1.1) [6], ( , ) (. 1.2).
(Different State Machine Assignment
Statements), ,
.
CUPL () (. 1.2) [3]. , , {Z} {T}
{Y}

{X}.

: .

. 1.1. CUPL
Reset
Y1 Y2

Ym
...

X1
X2
X3

f0

f1

T0

T1

z0

z1

...

Xn
fk-1

Tk-1

Zk-1

CLK
...

. 1.2.

, {} , m {Y}.

10
k T0, T1, , Tk-1, CLK, () Reset. Ti
fi, i
, CLK 0 1, , , ( ). ( ) z0 , z1, , zk-1.
Z= (zk-1, zk-2, , z0) . k , 2 k
.
. t=0 Z(0). Reset. t
= 0, 1, X(0), X(1), Y(0), Y(1), (0), (1),
CLK Z(1), Z(2), , , .
.
:
Z(t+1)
Y(t)

=
=

[Z(t),X(t)]
[Z(t),X(t)]

t= 0,1, 2, Z(0) = z0 .
(Z,X)
. [Z(t), X(t)]
.
:
Z(t+1)
Y(t)

=
=

[Z(t),X(t)]
[Z(t)]

[Z(t), X(t)] , [Z(t)] .

11

.
,
CUPL, . 1.3, :
Input ;
Output ( , ) ;
Combinatorial Logic () ;
State Bits () ,
;
Storage Registers (), .

. 1.3. CUPL
CUPL , , .
SEQUENCE state_var_list {
PRESENT state_n0
IF (condition1)NEXT state_n1;
IF (condition2) NEXT state_n2 OUT out_n0;
DEFAULT NEXT state_n0;
PRESENT state_n1
NEXT state_n2;
.
PRESENT state_nn statements;
}

, SEQUENCE , ,
( D-, J-K-

12
, RS-, T-), , sequenced
D-. [2, 3].
state_var_list , , (), field ,

.
state_n ( ) , ,
present ,
next.
Out ,
condition.
<PRESENT state_nn statements;> statements, state_nn.
PRESENT state_n0
IF (condition1)NEXT state_n1;
IF (condition2) NEXT state_n2 OUT out_n0;
DEFAULT NEXT state_n0;

, state_n0, condition1
state_n1; condition2
state_n2 out_n0;
( ) state_n0.
CUPL-,
(Sequential Logic) [1,2]:
sequence BayBridge {
present red
if car next green out go ;

/* red */
/ * -

green go * /
default next red;
/ *
red* /
present green
/* green */
next red; / * red* /
}

. . , ,

, .

13
CUPL
, :
field input [in 1..0]
field output [out3..0]
table input => output {00=> 01; 01=>02; 10=>04; ll=>08}

, , CUPL- 16- . RES,

CLK, (D0...D15) , Load D
, Ser_in , Ser_out.
Load false
( ).
Ser_in , ; i- (i-1) , 0- Ser_out. F1500 (Atmel) [6].
/* Inputs */
pin 43 = CLK;
pin 1 = Load;
pin 2 = RES;
pin 44 = Ser_in;
pin [41..36,34..31,29..24] = [D0..15];
/* Outputs */
pin 21 = Ser_out;
/* Q Nodes */
pinnode = [Q1..15];
Field Qnodes = [Q15..1,Ser_out];
/* Q nodes */
Field Qshift = [Ser_in,Q15..1]; /* Shifting input */
Field Din
= [D15..0];
/* Data input */
/* EQUATIONS */
Qnodes.ck = CLK;
Qnodes.ar = RES;
Qnodes.d =
Load & Din
/*Load in the data*/
# !Load & Qshift;
/*Shifts the data*/

14
. 1.4
, WINSIM.

. 1.4. 16-

CUPL ,
.
[!] var [.ext] = exp; ,

15
var ,
, . , exp ;
.ext var, . 1.5 (. 1.1) [6];
! ,
var, , ,
;
.exp ,
CUPL .
1.5
CUPL

.Ext

(L ,
R-)
P
.AP
L
Asynchronous preset

of flip-flop
1
R
.AR
L
Asynchronous reset of

flip-flop
0
CE ()
.CE
L
CE input of enabled DD-CE
CE type flip-flop

.CK
L
Programmable clock of

Dflip-flop

.CK
L
Clock multiplexer se D- MUX
lection

D- (.D
L
D input of D-type flip) D-
flop
D- .DFB
R
D registered feedback

path selection
Q- D-
.DQ
R
Q output of D-type
flip-flop

16
. 1.5

.Ext

J- () JK-
K- () JK-
D- ()


Q- ()



R- () RS-
S- () RS-
P

1
T- ( )
T-
T

.INT

(L ,
R-)
R

.IO

.J

.K

.L

.LE

.LQ

.OE

Programmable output
enable

.R

.S

.SP

R input of SR-type
output flip-flop
S input of SR-type
output flip-flop
Synchronous preset of
flip-flop

.T

TFB

Internal feedback path

for registered macrocell
Pin feedback path selection
J input of JK-type output flip-flop
K input of JK-type
output flip-flop
D input of transparent
latch
Programmable latch
enable
Q output of transparent
input latch

T input of toggle output flip-flop

T registered feedback
path selection

17
. .ext .
, XOR 1 2

Y = X1 & !X2 # !X1 & X2;.

D-

Y.D = X1 & !X2 # !X1 & X2;,

Y pin,
IO (/).
.

.
, CUPL:
;

;
;


;
CUPL- -, .
CUPL . ,
,
.
. CUPL . .
, CUPL , . 1.5.
CUPL, 16- .
CUPL , [5].

18

. 1.5. CUPL

19
Name

Shift_16 ; /* Name of Program */

PartNo
Date
Revision
Designer
Company
Assembly
Location
Device
/* Inputs

S00 ;
15.12.2010 ;
01 ;
Engineer ;
TSURE ;
None ;
None ;
F1500A ;
*/

pin
pin
pin
pin

43 = CLK;
1 = Load;
2 = RES;
44 = Ser_in;

pin [41..36,34..31,29..24] = [D0..15];

/* Outputs */
pin 21 = Ser_out;
/* Q Nodes */
pinnode = [Q1..15];
Field Qnodes = [Q15..1,Ser_out];
/* Q nodes */
Field Qshift = [Ser_in,Q15..1]; /* Shifting input */
Field Din
= [D15..0];
/* Data input */
/* EQUATIONS */
Qnodes.ck = CLK;
Qnodes.ar = RES;
Qnodes.d =
Load & Din
/*Load in the data*/
# !Load & Qshift;
/*Shifts the data*/

1.4. Winupl
1. Winupl CD- Atmel Website [ SETUPEX.EXE].
Winupl
{C:\ D:\}.

(), WinSim , HEX JEDEC, ,
. . 1.6

20
WinCupl. ,
.

. 1.6. WinCupl
2. WinCupl - >>Atmel WinCupl.

21

Help>About.

3. C:\Wincupl\Examples\Atmel . PLD, , count10.pld ( 2),

4- PAL16v8a.

4. Winupl
( ), , Messages (). , .pld. Messages () , .

22

5. Project () ,
.
. , .
Editor () , , .
Messages () , .
6. Options.
Options :
Compiler (Ctrl+W)- CUPL;
Devices (Ctrl+D) PLD,
;
Simulator (Ctrl+L) ;
WinCUPL - WinCUPL.
7. Compiler Options. Output Files. List, ().

23

.jed, .doc,
.lst. Minimization Quick.

General , ,

24
<Apply>, <OK> .
8. <Device> () Options.
, Atmel SPLD-
EPLD- . Device in file ( , g16v8a).

9. <RUN>
<Device dependent compile>, .

25
! PLD-,
DEVICE Library .
5 :
1) ;
2) , , , , ;
3)
(
, );
4) ;
5)
;
count10.pld

Q0.d

=> !Q0 & !Q1 & !Q2 & Q3 & !clr # !Q0 & !Q3 & !clr

Q1.d

=> !Q0 & !Q1 & !Q2 & Q3 & !clr & dir
# Q0 & !Q1 & !Q3 & !clr & !dir
# !Q0 & Q1 & !Q3 & !clr & !dir # Q0 & Q1 & !Q3 & !clr & dir
# !Q0 & !Q1 & Q2 & !Q3 & !clr & dir

Q2.d

=> !Q0 & !Q1 & !Q2 & Q3 & !clr & dir
# Q0 & Q1 & !Q2 & !Q3 & !clr & !dir
# !Q1 & Q2 & !Q3 & !clr & !dir # Q0 & Q2 & !Q3 & !clr & dir
# !Q0 & Q1 & Q2 & !Q3 & !clr

Q3.d

=> Q0 & !Q1 & !Q2 & Q3 & !clr & dir
# !Q0 & !Q1 & !Q2 & !Q3 & !clr & dir
# Q0 & Q1 & Q2 & !Q3 & !clr & !dir
# !Q0 & !Q1 & !Q2 & Q3 & !clr & !dir

carry => !Q0 & !Q1 & !Q2 & !Q3 & !clr & dir
# Q0 & !Q1 & !Q2 & Q3 & !clr & !dir
clear => clr
count => Q3 , Q2 , Q1 , Q0
down => !clr & dir
mode => clr , dir
up
=> !clr & !dir
carry.oe => 1

count10.doc Chip Diagram (. 1.7), .

26

clk
clr
dir

GND

______________
|
Count10
|
x---|1
20|---x
x---|2
19|---x
x---|3
18|---x
x---|4
17|---x
x---|5
16|---x
x---|6
15|---x
x---|7
14|---x
x---|8
13|---x
x---|9
12|---x
x---|10
11|---x
|______________|

Vcc
carry
Q0
Q1
Q2
Q3
!oe

. 1.7.
. 1.8.
count10.pld.

. 1.8. WinCupl count10.pld

27
WinCupl
count10.jed, .
CUPL(WM)
5.0a Serial# 60008009
Device
g16v8ms Library DLIB-h-40-11
Created
Wed Dec 15 19:28:25 2010
Name
Count10
Partno
CA0018
Revision
02
Date
12/15/2010
Designer
Kahl
Company
Logical Devices, Inc.
Assembly
None
Location
None
*QP20
*QF2194
*G0
*F0
*L00256 11111111111111111111111111111111
*L00288 10110111111011101110111011111111
*L00320 10111011110111101110110111111111
*L00512 10111111111011101110110111111111
*L00544 10111111111011111111111011111111
*L00768 10110111111011101110110111111111
*L00800 10111011110111101111111011111111
*L00832 10111011111011011111111011111111
*L00864 10110111110111011111111011111111
*L00896 10110111111011101101111011111111
*L01024 10110111111011101110110111111111
*L01056 10111011110111011110111011111111
*L01088 10111011111111101101111011111111
*L01120 10110111110111111101111011111111
*L01152 10111111111011011101111011111111
*L01280 10110111110111101110110111111111
*L01312 10110111111011101110111011111111
*L01344 10111011110111011101111011111111
*L01376 10111011111011101110110111111111
*L02048 01111100010000110100000100110000
*L02080 00110000001100010011100000000000
*L02112 00000000110000111111111111111111
*L02144 11111111111111111111111111111111
*L02176 111111111111111101
*C4627
*_0D18

, , , [11] . 1.6 .

28
1.6

(.)
(.)
QF
QP
F
L
C
P
D
G

Number of fuses in device

Number of pins in test vectors ***

(hex)
Default fuse state

Fuse list

Fuse checksum
(hex)
Pin sequence **
()
Device (obsolete)

Security fuse

10. ,
Count10.si. Open with Winsim..

11. <>.
WINSIM ( ). <>
. ,
.
.
.
1.5.
1. WinSim . WinSim File>New.

29

2. <Design File > .

. . <OK>.

WinSim
.si. :

30
3. Signal >Add Signal, , . .

4. , . Signal>Add Vector.
, 32 :

coun[Q3..Q0] mod[clr..dir] ( , ). clk, clr,

(dir, !oe), (Q0..3).

31
5. ( ) , .. -.
.
.

, Set Whole Signal.
clr
1,
0. , .

dir 17 1,
0.
!oe 0 ( ). clk ( low, hi, low).

32
6. , ,
(Ctrl+L). .si.

,
(. 1.9).
View>Refresh .

. 1.9.

. . 1.9 , 0, , dir 1, : 1 , 0
9 8 7 6 5 4 3 2 1 0 9 8 .. , , 0 carry , 1.
dir, 0, : 0 1 2 3 4

33
5 6 7 8 9 0 1 2 .. ,
9 carry , 1.
1.6.
:
1) , ;
2) ,
, /;
3) ;
4) - ;
5) CUPL;
6) WinCupl CUPL;
7) WinSIM , ,
.
;
8) .doc ;
9) .jed
;
10) ( , , ).

1. ?
.
2. CUPL?
?
3.
.
4. CUPL.
5. CUPL ?
6. WinCupl?
7. CUPL?

34
8. WinCupl
?
9. WinSim ,
?
10.
CUPL ?
11. CUPL , CUPL.
12. .doc, , .
13. -
, ?
2. 2.
-
QUARTUS II (ALTERA)
VHDL- -

2.1.
-
Quartus II VHDL - , .
2.2.
Altera
VHDL- - , n- X Y [13, 15, 16, 17].
, - Quartus II.
(), , QuartusII, , , [21].

N, V, C, Z, , ( ), :

35
N (Negative), 1, ,
;
Z (Zero), 1, , ( 0). , ,
Z ;
V (oVerflow), 1, , .
, , 0. V 1, ;
C (Carry), 1, ,
n- Cn
. ( , 0).
;
(Parrity), 1, , ,
;
C, 1, , .
( , 0).
( 3- ,
4- ).
(.
, . 2.1) , ,
), ,
( , ).

36
2.1
2

.
1

X xor Y,
SAR5(not X) and Y,
X +Y+0,
SHL2(YX).0
not (SHR3(X).1 xor Y),
X and Y,
X Y +1 C0,
SAL6(X+Y).1
RCR2(X) Y,
not(X and not(Y)),
X+Y+1 0,
ROL3(Y)
X and not Y,
not X xor Y,
X +RCL5(Y) 0,
SAR2(Y X)
X or SHL9(not(Y)).0,
not(X and Y),
Y X1+0,
ROR3(X+Y)
SAR7(X) or not(Y+X),
X and Y,
X Y1+0,
ROL5(X)
not SHL6(X+Y).1 or Y,
not(X xor not(Y)),
Y X+0,
RCR4(Y)
not (X xor Y),
X and SAL8(Y).0,
Y X C0,
RCL2(X+Y)
SHL3(X+not(Y)+C0).0,
not(X) and not(Y),
RCR8(Y + X+0),
X or not(Y)
Z =ROR12(X+Y)
Y- not(X)
(Not (Y)) xor X
SHR8(Y).1

N, Z, , V

32

N, Z,V, P

24

N, Z, ,

14

N, Z, ,

16

N, Z, C, V

18

N, Z, C,V

28

N, Z, ,

20

N, Z, ,

34

N,Z,,

22

N,Z,V, P

26

37
. 2.1

.
10

11

12

13

14

15

16

17

18

not ROL2(X xor not(Y)),
not (X and Y),
Y +X +1 C0,
RCR1(X Y)
SHR4(X+Y+C0).1
XY
Y xor (not(X))
ROL1(not (Y) or X)
ROR7(not (Y) and X)
not (X+Y)
Not(Y) and not(X)
SAL10(Y xor X).1
not (SAR3(Not (Y) or X)))
X or (X-Y)
SAL8(X+Y).0
Not (Y and not(X))
ROR9(not(Y) xor not(X))
X and (X Y 1)
Not(Y) or not(X)
RCL7(X+Y)
RCR1(Y X)
Not (not (Y) and (X))
RCL2(X+Y+1 C0)
Not(Y) xor not(X)
SHR7 (X+Y) .0
Y X 1+C0
RCL11(Y and not(X))
Not (Y) or X
RCR3(X+Y+C0)
XY
X eor (not(Y+C0))
SAR9 (X or Y)
Not (ROR7(not (X)))
Y X+C0
Not(X xor not(Y))
ROL5(X+Y)
SHR7(X Y+1-C0).0
X or Y
Y and (X+Y)
ROR3(not(X) xor Y)

N, Z, C, P

12

N,Z,V, P

30

N, Z,V, P

16

N, Z, ,

36

N, Z, ,

10

N, Z, , V

32

N,Z,,

24

N, Z, C, P

18

N, Z,V, P

20

N, Z, ,

:
SHR(L)n().0 (1) - () n 0 (1) ,

38
ROR(L)n() () n
,
RCR(L)n() () n
( ),
SAR(L)n() () n .
2.3.
, , , [15, 16],

- ,
(, , , -, -,
), Quartus II .
,
, , .
,
. ,

.
, VHDL.
.
.
:
Quartus II, bdf- ( Max+PlusII
gdf), () . ( )
, . . -
, . Quartus II VHDL .
Quartus II (. 2.1) File

39
Create (Update) > Create HDL Design File for Current File Enter ( ). , . 2.2. VHDL
.
VHDL- . Quartus II .
, , .

. 2.1.
: , ,

40
VHDL, VHDL- , , . , ..
, VHDL.

. 2.2. VHDL- ,

2.4. 8- -
VHDL
,
/ (. 2.3).
F[5-3] (Y )
alu_1804
000
R+S+CO
F[5..3]
Y[7..0]
001
S-R-1+CO
S[7..0]
CF
010
R-S-1+CO
R[7..0]
C8
C0
OvF
011
R S
ZF
100
R &S
SF
101
R &S
110
R S
inst
111
R S
. 2.3.
: R S 8- ,
, ;
C0 ;
F(5..3) .

41
:
Y 8- ;
CF / (CF = not (C8) , CF = C8 ) F = 0
;
C8
( ) 8 = 0 ;
OVF ,
OVF = C 8 C 7 ( ) OVF = 0 ;
ZF , ZF = 1
0;
SF , SF = 1 .
VHDL, Entity , - ()
. 2.3. std_logic std_logic_1164 [10].
Entity VHDL
:
entity alu_1804 is
port( F: in Std_Logic_Vector(5 downto 3);
S: in Std_Logic_Vector(7 downto 0);
R: in Std_Logic_Vector(7 downto 0);
C0: in Std_Logic;
Y: out Std_Logic_Vector(7 downto 0) ;
CF,C8: out Std_uLogic;
OvF: out Std_uLogic;
ZF: out Std_uLogic;
SF: out Std_uLogic
);
end alu_1804;

R+S+CO , VHDL (and, or xor), for.
(. 2.4).

42
2.2

Si
Pi
SUMi
Pi+1
VHDL i-
0
0
0
0
SUMi <= (not (Ri ) and not (Si) and Pi ) or
0
1
1
0
(not (Ri ) and Si and not (Pi )) or
(Ri and not (Si) and not (Pi)) or
1
0
1
0
(Ri and Si and Pi);
1
1
0
1
Pi+1 <= (not (Ri) and Si and Pi) or
0
0
1
0
(Ri and not (Si) and Pi) or
0
1
0
1
(Ri and Si and not (Pi) or
1
0
0
1
(Ri and Si and Pi).
1
1
1
1

Ri
0
0
0
0
1
1
1
1

Pi
Ri

Yi

SUM

Pi+1

Si

Pi
Ri
Si

P0
R0

SUM

P1

S0

Yi
=1

=1

P1
R1

Y1
P2

...
1
&

=1

SUM

S1

&

Y0

Pi+1
Pn-1
Rn-1
Sn-1

. 2.4.

SUM

Yn-1
Pn

43

8- .
--
adder: for i in 0 to 7 generate
-- (i+1)-
Pin(i+1)<=(Pin(i) and (RI(i) xor SI(i))) or (RI(i) and SI(i));
-- i-
YI(i)<=RI(i) xor SI(i) xor Pin(i);
end generate;

i ,
.
, S+R. S+R+C0 Pin(0) 0 (
).
.
. SR1+C0 .
, 0, 0,
S+(R1) , 0, 1, S+(R). S R, Std_Logic_Vector(7 downto 0), , RI SI
:
if C0 = '0' then varR:=-conv_integer(R)-1;
else varR:=-conv_integer(R);
end if;
RI<=Conv_std_logic_vector(varR,8);
SI<=S;

varR , -128
+127.
RS1+C0. :
if C0 = '0' then varS:=-conv_integer(S)-1;
else varS:=-conv_integer(S);
end if;
SI<=Conv_std_logic_vector(varS,8);
RI<=R;

varS ,
-128 +127.

.
convert: process(S,R,F,C0)
variable varR, varS: integer range -128 to +127;
begin

44
if C0 = '0' then varR:=-conv_integer(R)-1;
else varR:=-conv_integer(R);
end if;
if C0 = '0' then varS:=-conv_integer(S)-1;
else varS:=-conv_integer(S);
end if;
case F is
when "001" => RI<=Conv_std_logic_vector(varR,8);
SI<=S;
when "010" => SI<=Conv_std_logic_vector(varS,8);
RI<=R;
when others =>
RI<=R;
SI<=S;
end case;
end process;

F (. 2.3).
8-
/:
--
SPpin: with F select
Pin(0)<=C0 when "000",
'0' when others;
--
adder: for i in 0 to 7 generate
--
Pin(i+1)<=(Pin(i) and (RI(i) xor SI(i))) or (RI(i) and SI(i));
--
YI(i)<=RI(i) xor SI(i) xor Pin(i);
end generate;

. : , , ,
.
, , SR
S R 1 . , SR1+C0
S R 1 1 C0 S R C0 . , , RS1+C0 R S C0 .
VHDL . R S VHDL- R or S, R & S
VHDL- R and S, R & S VHDL- S and
(not(R)), R S VHDL- R xor S , , R S VHDL- not (R xor S ).
SMUX , , -

45
. ,
,

F[5..3] . with select:
SMUX: with F select
YI2<=YI when "000"|"001"|"010",
R or S when "011",
R and S when "100",
S and (not(R)) when "101",
R xor S when "110",
not (R xor S) when others;

others
. std_logic, , , 0 1, X, U . , others F.
.
ZF 1
. VHDL-

ZF<='1' when YI2=X"00" else '0';

SF 1 , . VHDL- :
SF<=YI2(7);.

OVF 1 ,
: () . VHDL

OvF<=Pin(8) xor Pin(7) when (F="000") or (F="001")
or (F="010") else '0';

8 1 ,
(
):
C8 <=Pin(8) when (F="000") or (F="001") or
(F="010") else '0';

F 1 ,
( ), ( ) :

46
SCF: with F select
CF <=
Pin(8) when "000",
not Pin(8) when "001"|"010",
'0' when others;

,
VHDL-, . 4.
. 2.5.

. 2.5. VHDL-

. 2.6 , QuartusII RTL-viewer ( Tools Netlist
Viewers > RTL-viewer).

47

. 2.6. ,
RTL-viewer Quartus II
2.5.
VHDL
, VHDL
, .
VHDL ,
[18, 19].

48

0.SHR1() - 1 0 , :
Q(7 downto 0) <= 0 & X(7 downto 1);

SHL1().0 - 1 0 , :
Q(7 downto 0) <= X(6 downto 0) & 0;

ROR1() 1
, :
Q(7 downto 0) <= (0) & X(7 downto 1);

ROL1() 1
, :
Q(7 downto 0) <= X(6 downto 0) & (0);

SAR1() 1
, :
Q(7 downto 0) <= (7) & X(7 downto 1);

1
, :
Q(7 downto 0) <= MSF & X(7 downto 1),

MSF = N xor V, N , V ( ).
SAL1().0 1 , :
Q(7 downto 0) <= X(7) & X(5 downto 0) & 0;

. , ,
DI :
QO(7 downto 0) <= DI(6 downto 0)& DI(7);

2.6.
:
1) , ;
2) ;

49
3) ( ) (
) ; ;
4) VHDL- , ( );
5) VHDL- ,
( );
6) - ( );
7) ( );
8) , ;
9) ( , ,
,
(
)).

1.

Quartus II.
2. .
3. ?
?
4. ?
5. VHDL ?
6. , ?
7.
?
8. ?
9.
.
10. VHDL .
11. ?
?
?

50
12. VHDL - ?
13. VHDL?
14. VHDL .
15. VHDL- .
16. VHDL- n- .
17. VHDL- n- .

1. ., . : . . . .
.: , 2001. 704 .: . (.553 564).
2. .. : 2- . .: , 2002.
3. .. :
. 1. : - , 2008. 70.
4. ., . . , 8- : . . .: , 2004 .:.
5. WINCUPL / handleiding cup[1].pdf / http://www.atmel.com.
6. ATMEL WinCUPL. USERS MANUAL (Copyright Atmel Corporation 2006)
/ http://www.atmel.com.
7. PALCE22V10 and PALCE22V10Z Families ( 24-Pin EE CMOS (Zero Power)
Versatile PAL Device) / PALCE22V10.pdf / http://www.atmel.com.
8. ATF15XXBE Product Brief. Complex Programmable Logic Devices (CPLDs) /
doc3659.pdf / http://www.atmel.com.
9. http://www.atmel.com/products/pld/default.asp.
10. Atmel ATF15xx Family: ISP Devices User Guide/ 15-16316.pdf/
http://www.atmel.com.
11. JEDEC Standard Number 3A // http://www.atmel.com.
12.
/ . .., .., .. . : - , 1999. 59 .
13. .., .. .
. , 1974
14. .. Altera: , . .: -I,
2002. 576.: .

51
15. .. . .:
, 1985. 552 .: .
16. . . 1. / . .., .., ..,
... : - , 1994. 23 . (. . . 2104).
17. .. . .
. . . 2- .- .: .., 1989. 336 .: .
18. .. VHDL .
.: : 000 : , 2003. 208 .: .
19. .., .. VHDL. . .: -, 2006. 344 .: . ( ).
20. 50754-95. VDL.
. .: , 1995.
21. .., .., .., .. Altera Max+Plus II Quartus II. . .: , 2002 352 .: .

52
1.
1

, ,
. 1.2. . 1.1 1.2.

{xi }- ,
- 5 CLK;
{yj }- ;
- 1) , 2) ;
( )
1) + (), 2) ().
, CLK .
1.1
( )
X

Y

123456123456..
123456123456..
1
16
010110010110..
1
1D
011101011101..
2

0F

001111001111..

14

010100010100..

0E

001110001110..

1B

011011011011..

15

010101010101..

29

101001101001..

13

010011010011..

0D

001101001101..

1C

011100011100..

38

111000111000..

11

010001010001..

0C

001100001100..

18

011000011000..

32

110010110010..

25

100101100101..

21

100001100001..

10

19

011001011001..

10

26

100110100110..

11

17

010111010111..

11

2B

101011101011..

12

35

110101110101..

12

1A

011010011010..

53
1.2
( B)

X5,X7

Y1,Y2,Y3

X1,X2

Y4,Y5,Y6

X4,X6

Y7,Y8,Y9

X8,X9

Y1,Y2,Y4

X2,X4

Y4,Y2,Y3

X2,X3

Y4,Y2,Y6

X2,X6

Y1,Y2,Y7

X2,X7

Y1,Y2,Y8

X4,X8

Y5,Y3,Y8

10

X5,X8

Y4,Y2,Y7

11

X4,X7

Y1,Y3,Y5

12

X1,X5

Y4,Y2,Y8

13

X2,X8

Y1,Y3,Y7

14

X1,X7

Y1,Y3,Y8

15

X3,X8

Y5,Y3,Y6

16

X3,X6

Y1,Y2,Y5

17

X2,X5

Y4,Y2,Y5

18

X3,X5

Y1,Y2,Y6

19

X9,X6

Y1,Y3,Y4

20

X7,X3

Y1,Y3,Y6

21

X8,X6

Y4,Y2,Y9

22

X4,X9

Y1,Y3,Y9

23

X1,X9

Y5,Y3,Y7

24

X9,X7

Y1,Y2,Y9

54
. 1.2

25

X5,X9

Y5,Y3,Y9

26

X3,X9

Y5,Y7,Y6

27

X8,X1

Y1,Y5,Y7

28

X7,X6

Y1,Y6,Y8

29

X5,X4

Y4,Y1,Y7

30

X6,X1

Y4,Y1,Y8

31

X4,X1

Y5,Y1,Y9

32

X4,X3

Y5,Y1,Y6

33

X5,X6

Y6,Y1,Y4

34

X1,X3

Y6,Y1,Y7

35

X9,X2

Y7,Y1,Y8

36

X7,X8

Y7,Y1,Y9

37

X1,X11

Y10,Y11,Y12

38

X2,X10

Y1,Y11,Y12

39

X3,X11

Y2,Y10,Y12

40

X4,X10

Y3,Y11,Y10

41

X5,X11

Y4,Y11,Y2

42

X6,X12

Y5,Y11,Y7

43

X7,X11

Y6,Y11,Y9

44

X8,X12

Y7,Y11,Y10

45

X9,X11

Y8,Y5,Y12

46

X10,X12

Y9,Y1,Y12

47

X1,X12

Y7,Y3,Y12

48

X5,X10

Y8,Y5,Y7

55
2. COUNT10.PDF
Name
Count10;
Partno
CA0018;
Date
12/15/2010;
Revision 02;
Designer Kahl;
Company
Logical Devices, Inc.;
Assembly None;
Location None;
Device
g16v8a;
/** Inputs **/
Pin 1
= clk;
/* Counter clock
*/
Pin 2
= clr;
/* Counter clear input
*/
Pin 3
= dir;
/* Counter direction input
*/
Pin 11
= !oe;
/* Register output enable
*/
/** Outputs **/
Pin [14..17] = [Q3..0];
/* Counter outputs
*/
Pin 18 = carry;
/* Ripple carry out
*/
/** Declarations and Intermediate Variable Definitions **/
field count = [Q3..0];
/* declare counter bit field */
$define S0 'b'0000
/* define counter states */
$define S1 'b'0001
$define S2 'b'0010
$define S3 'b'0011
$define S4 'b'0100
$define S5 'b'0101
$define S6 'b'0110
$define S7 'b'0111
$define S8 'b'1000
$define S9 'b'1001
field mode = [clr,dir];
/* declare mode control field */
up = mode:0;
/* define count up mode */
down = mode:1;
/* define count down mode */
clear = mode:[2..3];
/* define count clear mode */
/** Logic Equations **/
Sequenced count {
/* free running counter */
present S0
if up
next S1;
if down
next S9;
if clear
next S0;
if down
out carry;
present S1
if up
next S2;
if down
next S0;
if clear
next S0;
present S2
if up
next S3;
if down
next S1;
if clear
next S0;
present S3
if up
next S4;
if down
next S2;
if clear
next S0;

56
present S4

if up
if down
if clear
present S5
if up
if down
if clear
present S6
if up
if down
if clear
present S7
if up
if down
if clear
present S8
if up
if down
if clear
present S9
if up
if down
if clear
if up
/* assert carry output */ }

next S5;
next S3;
next S0;
next S6;
next S4;
next S0;
next S7;
next S5;
next S0;
next S8;
next S6;
next S0;
next S9;
next S7;
next S0;
next S0;
next S8;
next S0;
out carry;

57
3.
1

PAL22V10C
(DIP24) ,
, .

X2,X4

Y4,Y2,Y3

, CLK .

1234512345..

1234512345..

09

0100101001..

03

0001100011..

07

0011100111..

04

0010000100..

1B

1101111011..

(. 4.1)
1

CLK

X2
X4
Y4
Y2
Y3

. 4.1.

58

1. ,
ai , bj ,
ai. a0
reset.
a0 0, a1
1, a2 2, a3 4 a5 5. . 4.2.
x2x4

a1
x2x4
x2x4

a0

y4y2y3

b1

b0

x2x4
y4y2y3

y4y2y3

b5 y4y2y3

x2x4

x2x4

b2

x2x4

a4

a2

x2x4

y4y2y3
b4

x2x4

a3

x2x4

. 4.2.
2. Cupl.

xx1
xx2
xx3
xx4
xx5

=
=
=
=
=

(!x2&!x4);
(x2&!x4);
(!x2&x4);
(!x2&x4);
(x2&x4);

,
. 4.2.
.
Field Moore1 =
$Define b0 'b'
$Define b1 'b'
$Define b2 'b'
$Define b4 'b'
$Define b5 'b'

[T2..0];
000
001
010
100
101

Field YYY = [Y4,Y2,Y3];
$define yy0 'b'001

59
$define
$define
$define
$define

yy1
yy2
yy3
yy4

'b'001
'b'010
'b'101
'b'101

.
Sequenced Moore1 {
present b0
if
xx1
default
present b1
if
xx2
default
present b2
if
xx3
default
present b4
if
xx4
default
present b5
if
xx5
default
}

next
next
next
next

b1;
b0;
b2;
b1;
next b4;
next b2;
next b5;
next b4;
next b0;
next b5;

table Moore1 => YYY
{
b0 => yy0;
b1 => yy1;
b2 => yy2;
b4 => yy3;
b5 => yy4;
}

,
T0.ar
T0.sp
T1.ar
T1.sp
T2.ar
T2.sp

=
=
=
=
=
=

reset;
'b'1;
reset;
'b'1;
reset;
'b'1;

3.
Name
PartNo
Date
Revision
Designer
Company
Assembly
Location
Device

moore ;
01 ;
19.12.2010 ;
01 ;
Engineer ;
TSURE ;
None ;
None ;
g22v10 ;

/* *************** INPUT PINS *********************/

PIN
1 = clk;
PIN
2 = !reset;
PIN
3 = x2;
PIN
4 = x4;
/* *************** OUTPUT PINS *********************/
PIN
20 = Y4;
PIN
19 = Y2;

60
PIN
PIN
PIN
PIN

18
23
22
21

=
=
=
=

Y3;
T2;
T1;
T0;

/** Declarations and Intermediate Variable Definitions **/

Field Moore1 =
$Define b0 'b'
$Define b1 'b'
$Define b2 'b'
$Define b4 'b'
$Define b5 'b'

[T2..0];
000
001
010
100
101

Field YYY = [Y4,Y2,Y3];

$define yy0 'b'001
$define yy1 'b'001
$define yy2 'b'010
$define yy3 'b'101
$define yy4 'b'101
y2.oe = 'b'1;
y1.oe = 'b'1;
y0.oe = 'b'1;
t2.sp = 'b' 0 ;
t1.sp = 'b' 0 ;
t0.sp = 'b' 0 ;
t2.ar = reset;
t1.ar = reset;
t0.ar = reset;
xx1
xx2
xx3
xx4
xx5

=
=
=
=
=

(!x2&!x4);
(x2&!x4);
(!x2&x4);
(!x2&x4);
(x2&x4);

Sequenced Moore1 {
present b0
if
xx1
default
present b1
if
xx2
default
present b2
if
xx3
default
present b4
if
xx4
default
present b5
if
xx5
default
}
table Moore1 => YYY

next b1;
next b0;
next b2;
next b1;
next b4;
next b2;
next b5;
next b4;
next b0;
next b5;

61
{

b0 => yy0;
b1 => yy1;
b2 => yy2;
b4 => yy3;
b5 => yy4;

4.

WinSim ,
.

Chip Diagram
===============================================================================

clk
reset
x2
x4

GND

______________
|
moore
|
x---|1
24|---x
x---|2
23|---x
x---|3
22|---x
x---|4
21|---x
x---|5
20|---x
x---|6
19|---x
x---|7
18|---x
x---|8
17|---x
x---|9
16|---x
x---|10
15|---x
x---|11
14|---x
x---|12
13|---x
|______________|

Vcc

Y4
Y2
Y3

62
4. VHDL-
. 2
. . 2.3.
--
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity alu_1804 is
port( F: in Std_Logic_Vector(5 downto 3);
S: in Std_Logic_Vector(7 downto 0);
R: in Std_Logic_Vector(7 downto 0);
C0: in Std_Logic;
Y: out Std_Logic_Vector(7 downto 0) ;
CF,C8: out Std_uLogic;
OvF: out Std_uLogic;
ZF: out Std_uLogic;
SF: out Std_uLogic
);
end alu_1804;
Architecture ALU of alu_1804 is
signal Pin: std_Logic_Vector(8 downto 0);
signal YI,YI2,SI,RI: std_Logic_Vector(7 downto 0);
BEGIN
convert: process(S,R,F,C0)
variable varR, varS: integer range -128 to +127;
begin
if C0 = '0' then varR:=-conv_integer(R)-1;
else varR:=-conv_integer(R);
end if;
if C0 = '0' then varS:=-conv_integer(S)-1;
else varS:=-conv_integer(S);
end if;
case F is
when "001" => RI<=Conv_std_logic_vector(varR,8);
SI<=S;
when "010" => SI<=Conv_std_logic_vector(varS,8);
RI<=R;
when others =>
RI<=R;
SI<=S;
end case;
end process;

63
SPpin: with F select
Pin(0)<=C0 when "000",
'0' when others;
--
adder: for i in 0 to 7 generate
Pin(i+1)<=(Pin(i) and (RI(i) xor SI(i))) or (RI(i) and SI(i));
YI(i)<=RI(i) xor SI(i) xor Pin(i);
end generate;
SMUX: with F select
YI2<=YI when "000"|"001"|"010",
R or S when "011",
R and S when "100",
S and (not(R)) when "101",
R xor S when "110",
not (R xor S) when others;
ZF<='1' when YI2=X"00" else '0';
SF<=YI2(7);
OvF<=Pin(8) xor Pin(7) when (F="000") or (F="001") or (F="010")
else '0';
C8 <=Pin(8) when (F="000") or (F="001") or (F="010") else '0';
SCF: with F select
CF <=Pin(8) when "000",
not Pin(8) when "001"|"010",
'0' when others;
Y <= YI2;
end ALU;

64

020565 23.06.1997 .
60841/16 .
.

..
..
..

.
... 4,0.

.2010 .

.-.. 3,8.

____ .

_____________________________________________________

17, , 28, , 44

17, , 28, , 1