Electrical Circuits Amd-Ati-Radeon-Hd5770/6770

8 7 6 5 4 3 2 1
C013
PCI-EXPRESS EDGE CONNECTOR
D D
+3.3V_BUS
+3.3V_BUS +12V_BUS +12V_BUS PCIe RESET Buffered
+3.3V_BUS +3.3V_BUS
+3.3V_BUS
x16 PCIe +3.3V_BUS
B1 A1 PRESENCE
B2 +12V#B1 PRSNT1#A1 A2
DNI DNI B3 +12V#B2 +12V#A2 A3
DNI B4 +12V#B3 +12V#A3 A4 C158
SMCLK B5 GND#B4 GND#A4 A5 R102 100nF_6.3V
p.6 GPIO_4_SMBCLK SMCLK JTAG2
SMDAT B6 A6 JTDIO_LOOP System JTAG TDI and TDO are hard wired. 10K
p.6 GPIO_3_SMBDATA SMDAT JTAG3
B7 A7 see p. 20 for GPU JTAG connection
GND#B7 JTAG4
5
DNI B8 A8
B9 +3.3V#B8 JTAG5 A9 R103 0R 1 NC7SZ08P5X_NL
JTAG1 +3.3V#A9 p.6,15,18 1V_LDO_POK
B10 A10 4 PERST#_gated
+3.3V_BUS B11 3.3Vaux +3.3V#A10 A11 PERST# 2
WAKE# PERST# U100
Mechanical Key
B12 A12
3
B13 RSVD#B12 GND#A12 A13
B14 GND#B13 REFCLK+ A14 PCIE_REFCLKP p.2
p.2 PETp0_GFXRp0 B15 PETp0 REFCLK- A15 PCIE_REFCLKN p.2
p.2 PETn0_GFXRn0 B16 PETn0 GND#A15 A16 PERp0
GND#B16 PERp0 PERp0 p.2
B17 A17 PERn0 DNI
PRSNT2#B17 PERn0 PERn0 p.2
Place these caps as close to the PCIE B18 A18
B19 GND#B18 GND#A18 A19
connector as possible p.2 PETp1_GFXRp1 PETp1 RSVD#A19 Place R104 in U100
B20 A20
B22 A22 PERn1
GND#B22 PERn1 PERn1 p.2
B23 A23
p.2 PETp2_GFXRp2 B24 PETp2 GND#A23 A24
+12V_BUS B26 A26 PERn2
B27 A27 PERST#_gated R110 7.5K 9 8
p.2 PETp3_GFXRp3 B28 PETp3 GND#A27 A28 JTAG_TRSTB p.19
p.2 PETn3_GFXRn3 B29 PETn3 GND#A28 A29 PERp3 U101C
C CAP CER 10UF 20% 16V X5R B30 A30 PERn3 C160 74LCX125MTC C
PERn3 p.2
10
B31 RSVD#B30 PERn3 A31 100pF_50V
(1206)1.8MM H MAX B32 PRSNT2#B31 GND#A31 A32
B33 GND#B32 RSVD#A32 A33
p.2 PETp4_GFXRp4 B34 PETp4 RSVD#A33 A34
+12V_BUS B36 A36 PERn4
B37 A37 JTAG_TRSTB R111 7.5K 5 6
p.2 PETp5_GFXRp5 B38 PETp5 GND#A37 A38 PERST#_buf p.2,18
C151 C152 p.2 PETn5_GFXRn5 B39 PETn5 GND#A38 A39 PERp5 U101B
150nF_16V 150nF_16V B40 A40 PERn5 C161 74LCX125MTC
PERn5 p.2
4
B41 GND#B40 PERn5 A41 100pF_50V
B44 A44 PERn6
B45 A45 DNI
+3.3V_BUS p.2 PETp7_GFXRp7 B46 PETp7 GND#A45 A46 +3.3V_BUS
CAP CER 10UF 10% 6.3V X5R GND#B47 PERp7 PERp7 p.2
B48 A48 PERn7 C159 100nF_6.3V
(0805)1.4MM MAX THICK B49 PRSNT2#B48 PERn7 A49
PERn7 p.2
B50 GND#B49 GND#A49 A50
14
p.2 PETp8_GFXRp8 B51 PETp8 RSVD#A50 A51
B53 A53 PERn8 PERST#_buf R112 7.5K 2 3
B54 A54
p.2 PETp9_GFXRp9 B55 PETp9 GND#A54 A55 U101A
+3.3V_BUS p.2 PETn9_GFXRn9 B56 PETn9 GND#A55 A56 PERp9 C162 74LCX125MTC
PERp9 p.2
7
1
B57 GND#B56 PERp9 A57 PERn9 100pF_50V
B58 A58
C155 C156 p.2 PETp10_GFXRp10 B59 PETp10 GND#A58 A59 PERST#_buf_delayed
C154 1uF_6.3V p.2 PETn10_GFXRn10 B60 PETn10 GND#A59 A60 PERp10
100nF_6.3V 10nF B61 A61 PERn10
13
B62 A62
p.2 PETn11_GFXRn11 B64 PETn11 GND#A63 A64 PERp11 PERST#_gated 12 11
GND#B64 PERp11 PERp11 p.2 TESTEN p.19
B65 A65 PERn11
B66 A66 U101D
p.2 PETp12_GFXRp12 B67 PETp12 GND#A66 A67 74LCX125MTC
B p.2 PETn12_GFXRn12 B68 PETn12 GND#A67 A68 PERp12 B
B69 A69 PERn12
B70 A70
p.2 PETp13_GFXRp13 B71 PETp13 GND#A70 A71 +3.3V_BUS
B73 A73 PERn13 1V_LDO_POK
B74 A74 PERST#_gated
p.2 PETp14_GFXRp14 B75 PETp14 GND#A74 A75 PERST#_buf TESTEN
p.2 PETn14_GFXRn14 B76 PETn14 GND#A75 A76 PERp14 JTAG_TRSTB
B77 A77 PERn14
B78 A78
PRESENCE B81 A81 PERn15
PRSNT2#B81 PERn15 PERn15 p.2
B82 A82
RSVD#B82 GND#A82
MPCIE100
SYMBOL LEGEND
DNI DO NOT
INSTALL
# ACTIVE
LOW
DIGITAL
GROUND
ANALOG
GROUND
A BUO BRING UP A
ONLY
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

© 2007 Advanced Micro Devices Advanced Micro Devices Inc.
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to, Date: Tuesday, November 10, 2009 Rev
any implied warranty of merchantibility or fitness for a particular
50
purpose, and disclaims responsibility forany consequences resulting Sheet 1
from use of the information included herein. of 21
Title RH JUNIPER GDDR5 1GB DP+DP/HDMI+DVI /sVGA Doc No. 102-C01301-00
8 7 6 5 4 3 2 1
5 4 3 2 1
(2) JUNIPER PCIe Interface

NOTE: Some of the PCIE testpoints will
be available through vias on traces.
U1B
TP101 PART 2 OF 15
AA38 Y33 PCIE_TX0P C100
p.1 PETp0_GFXRp0 PCIE_RX0P PCIE_TX0P PERp0 p.1
Y37 Y32 PCIE_TX0N 100nF_6.3V C101
p.1 PETn0_GFXRn0 PCIE_RX0N PCIE_TX0N PERn0 p.1
TP102 100nF_6.3V
Y35 W33 PCIE_TX1P C102
W36 W32 PCIE_TX1N 100nF_6.3V C103
TP103 100nF_6.3V
W38 U33 PCIE_TX2P C104
D p.1 PETp2_GFXRp2 PCIE_RX2P PCIE_TX2P PERp2 p.1 D
V37 U32 PCIE_TX2N 100nF_6.3V C105
TP105 TP104 100nF_6.3V
V35 U30 PCIE_TX3P C106
U36 U29 PCIE_TX3N 100nF_6.3V C107
TP106 100nF_6.3V
U38 T33 PCIE_TX4P C108
T37 T32 PCIE_TX4N 100nF_6.3V C110
TP107 100nF_6.3V
T35 T30 PCIE_TX5P C111
R36 T29 PCIE_TX5N 100nF_6.3V C109
TP108 TP109 100nF_6.3V
R38 P33 PCIE_TX6P C112
P37 P32 PCIE_TX6N 100nF_6.3V C113
TP110 100nF_6.3V
P35 P30 PCIE_TX7P C114
N36 P29 PCIE_TX7N 100nF_6.3V C115
TP111 P 100nF_6.3V
N38 N33 PCIE_TX8P C116
p.1 PETp8_GFXRp8 PCIE_RX8P C PCIE_TX8P PERp8 p.1
M37 N32 PCIE_TX8N 100nF_6.3V C117
TP113 TP112 I 100nF_6.3V
M35 N30 PCIE_TX9P C118
p.1 PETp9_GFXRp9
L36 PCIE_RX9P E PCIE_TX9P N29 PCIE_TX9N 100nF_6.3V C119 PERp9 p.1
TP114 X 100nF_6.3V
L38 L33 PCIE_TX10P C120
p.1 PETp10_GFXRp10
K37 PCIE_RX10P P PCIE_TX10P L32 PCIE_TX10N 100nF_6.3V C121 PERp10 p.1
p.1 PETn10_GFXRn10 PCIE_RX10N R PCIE_TX10N PERn10 p.1
TP115 100nF_6.3V
K35 E L30 PCIE_TX11P C122
J36 L29 PCIE_TX11N 100nF_6.3V C123
p.1 PETn11_GFXRn11 PCIE_RX11N S PCIE_TX11N PERn11 p.1
TP116 TP117 100nF_6.3V
J38 S K33 PCIE_TX12P C124
H37 K32 PCIE_TX12N 100nF_6.3V C125
TP118 100nF_6.3V
H35 J33 PCIE_TX13P C126
G36 J32 PCIE_TX13N 100nF_6.3V C127
TP119 100nF_6.3V
G38 K30 PCIE_TX14P C128
F37 K29 PCIE_TX14N 100nF_6.3V C129
C TP121 TP120 100nF_6.3V C
F35 H33 PCIE_TX15P C130
E37 H32 PCIE_TX15N 100nF_6.3V C131
TP122 100nF_6.3V
+1V
AB35 Y30 PCIE_CALRP 1.27K R100
p.1 PCIE_REFCLKP PCIE_REFCLKP PCIE_CALRP
AA36 Y29 PCIE_CALRN 2.0K R101
p.1 PCIE_REFCLKN PCIE_REFCLKN PCIE_CALRN
AA30 AB39
p.1,18 PERST#_buf PERSTB PCIE_VSS#1 E39
+1.8V PCIE_VSS#2 F34
PCIE_VSS#3 F39
B100 BLM15AG121SN1D +PCIE_PVDD AB37 PCIE_VSS#4 G33
PCIE_PVDD PCIE_VSS#5 G34
PCIE_VSS#6 H31
C132 C133 C134 C135 PCIE_VSS#7 H34
10uF 1uF_6.3V 100nF_6.3V 10nF PCIE_VSS#8 H39
PCIE_VSS#9 J31
+1.8V PCIE_VSS#10 J34
PCIE_VSS#11 K31
AA31 PCIE_VSS#12 K34
AA32 PCIE_VDDR#1 PCIE_VSS#13 K39
AA33 PCIE_VDDR#2 PCIE_VSS#14 L31
C141 C142 C143 C136 C137 C138 C139 C140 AA34 PCIE_VDDR#3 PCIE_VSS#15 L34
4.7uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 100nF_6.3V 100nF_6.3V V28 PCIE_VDDR#4 PCIE_VSS#16 M34
W29 PCIE_VDDR#5 PCIE_VSS#17 M39
W30 PCIE_VDDR#6 PCIE_VSS#18 N31
Y31 PCIE_VDDR#7 PCIE_VSS#19 N34
PCIE_VDDR#8 PCIE_VSS#20 P31
+1V PCIE_VSS#21 P34
PCIE_VSS#22 P39
G30 PCIE_VSS#23 R34
G31 PCIE_VDDC#1 PCIE_VSS#24 T31
H29 PCIE_VDDC#2 PCIE_VSS#25 T34
C148 C149 C150 C144 C145 C146 C147 H30 PCIE_VDDC#3 PCIE_VSS#26 T39
B
10uF 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V J29 PCIE_VDDC#4 PCIE_VSS#27 U31 B
J30 PCIE_VDDC#5 PCIE_VSS#28 U34
L28 PCIE_VDDC#6 PCIE_VSS#29 V34
M28 PCIE_VDDC#7 PCIE_VSS#30 V39
N28 PCIE_VDDC#8 PCIE_VSS#31 W31
R28 PCIE_VDDC#9 PCIE_VSS#32 W34
T28 PCIE_VDDC#10 PCIE_VSS#33 Y34
U28 PCIE_VDDC#11 PCIE_VSS#34 Y39
PCIE_VDDC#12 PCIE_VSS#35
JUNIPER XT A12 HF MVD SLT BIN1 TSMC FB12
A A

50
Title Doc No.
RH JUNIPER GDDR5 1GB DP+DP/HDMI+DVI /sVGA 102-C01301-00
5 4 3 2 1
5 4 3 2 1
(3) JUNIPER MEM Interface Ch A&B
U1C U1D
p.4 DQA0_[31..0] DQA1_[31..0] p.4 p.5 DQB0_[31..0] DQB1_[31..0] p.5
PART 3 OF 15 PART 4 OF 15
D D
DQA0_0 C37 C18 DQA1_0 DQB0_0 C5 AA4 DQB1_0
DQA0_1 C35 DQA0_0 DQA1_0 A18 DQA1_1 DQB0_1 C3 DQB0_0 DQB1_0 AB6 DQB1_1
DQA0_2 A35 DQA0_1 DQA1_1 F18 DQA1_2 DQB0_2 E3 DQB0_1 DQB1_1 AB1 DQB1_2
DQA0_3 E34 DQA0_2 DQA1_2 D17 DQA1_3 DQB0_3 E1 DQB0_2 DQB1_2 AB3 DQB1_3
DQA0_4 G32 DQA0_3 DQA1_3 A16 DQA1_4 DQB0_4 F1 DQB0_3 DQB1_3 AD6 DQB1_4
DQA0_5 D33 DQA0_4 DQA1_4 F16 DQA1_5 DQB0_5 F3 DQB0_4 DQB1_4 AD1 DQB1_5
DQA0_6 F32 DQA0_5 DQA1_5 D15 DQA1_6 DQB0_6 F5 DQB0_5 DQB1_5 AD3 DQB1_6
DQA0_7 E32 DQA0_6 DQA1_6 E14 DQA1_7 DQB0_7 G4 DQB0_6 DQB1_6 AD5 DQB1_7
DQA0_8 D31 DQA0_7 DQA1_7 F14 DQA1_8 DQB0_8 H5 DQB0_7 DQB1_7 AF1 DQB1_8
DQA0_9 F30 DQA0_8 DQA1_8 D13 DQA1_9 DQB0_9 H6 DQB0_8 DQB1_8 AF3 DQB1_9
DQA0_10 C30 DQA0_9 DQA1_9 F12 DQA1_10 DQB0_10 J4 DQB0_9 DQB1_9 AF6 DQB1_10
DQA0_11 A30 DQA0_10 DQA1_10 A12 DQA1_11 DQB0_11 K6 DQB0_10 DQB1_10 AG4 DQB1_11
DQA0_11 M DQA1_11 DQB0_11 M DQB1_11
DQA0_12 F28 D11 DQA1_12 DQB0_12 K5 AH5 DQB1_12
DQA0_13 C28 DQA0_12 E DQA1_12 F10 DQA1_13 DQB0_13 L4 DQB0_12 E DQB1_12 AH6 DQB1_13
A28 DQA0_13 DQA1_13 A10 M6 DQB0_13 DQB1_13 AJ4
DQA0_14
DQA0_14
M DQA1_14
DQA1_14 DQB0_14
DQB0_14
M DQB1_14
DQB1_14
DQA0_15 E28 C10 DQA1_15 DQB0_15 M1 AK3 DQB1_15
DQA0_16 D27 DQA0_15 O DQA1_15 G13 DQA1_16 DQB0_16 M3 DQB0_15 O DQB1_15 AF8 DQB1_16
DQA0_17 F26 DQA0_16 R DQA1_16 H13 DQA1_17 DQB0_17 M5 DQB0_16 R DQB1_16 AF9 DQB1_17
DQA0_18 C26 DQA0_17 DQA1_17 J13 DQA1_18 DQB0_18 N4 DQB0_17 DQB1_17 AG8 DQB1_18
DQA0_19 A26 DQA0_18 Y DQA1_18 H11 DQA1_19 DQB0_19 P6 DQB0_18 Y DQB1_18 AG7 DQB1_19
DQA0_20 F24 DQA0_19 DQA1_19 G10 DQA1_20 DQB0_20 P5 DQB0_19 DQB1_19 AK9 DQB1_20
DQA0_21 C24 DQA0_20 DQA1_20 G8 DQA1_21 DQB0_21 R4 DQB0_20 DQB1_20 AL7 DQB1_21
DQA0_22 A24 DQA0_21 I DQA1_21 K9 DQA1_22 DQB0_22 T6 DQB0_21 I DQB1_21 AM8 DQB1_22
DQA0_23 E24 DQA0_22 N DQA1_22 K10 DQA1_23 DQB0_23 T1 DQB0_22 N DQB1_22 AM7 DQB1_23
DQA0_24 C22 DQA0_23 DQA1_23 G9 DQA1_24 DQB0_24 U4 DQB0_23 DQB1_23 AK1 DQB1_24
DQA0_24 T DQA1_24 DQB0_24 T DQB1_24
DQA0_25 A22 A8 DQA1_25 DQB0_25 V6 AL4 DQB1_25
DQA0_26 F22 DQA0_25 E DQA1_25 C8 DQA1_26 DQB0_26 V1 DQB0_25 E DQB1_25 AM6 DQB1_26
DQA0_27 D21 DQA0_26 DQA1_26 E8 DQA1_27 DQB0_27 V3 DQB0_26 DQB1_26 AM1 DQB1_27
DQA0_27 R DQA1_27 DQB0_27 R DQB1_27
DQA0_28 A20 A6 DQA1_28 DQB0_28 Y6 AN4 DQB1_28
DQA0_29 F20 DQA0_28 F DQA1_28 C6 DQA1_29 DQB0_29 Y1 DQB0_28 F DQB1_28 AP3 DQB1_29
DQA0_29 DQA1_29 DQB0_29 DQB1_29
DQA0_30 D19
DQA0_30
A DQA1_30
E6 DQA1_30 DQB0_30 Y3
DQB0_30
A DQB1_30
AP1 DQB1_30
DQA0_31 E18 A5 DQA1_31 DQB0_31 Y5 AP5 DQB1_31
DQA0_31 C DQA1_31 DQB0_31 C DQB1_31
p.4 MAA0_[8..0] MAA1_[8..0] p.4 p.5 MAB0_[8..0] MAB1_[8..0] p.5
E E
MAA0_0 G24 H19 MAA1_0 MAB0_0 P8 Y9 MAB1_0
MAA0_1 J23 MAA0_0 MAA1_0 H20 MAA1_1 MAB0_1 T9 MAB0_0 MAB1_0 W9 MAB1_1
MAA0_2 H24 MAA0_1 MAA1_1 L13 MAA1_2 MAB0_2 P9 MAB0_1 MAB1_1 AC8 MAB1_2
MAA0_3 J24 MAA0_2 MAA1_2 G16 MAA1_3 MAB0_3 N7 MAB0_2 MAB1_2 AC9 MAB1_3
C C
MAA0_4 H26 MAA0_3 MAA1_3 J16 MAA1_4 MAB0_4 N8 MAB0_3 MAB1_3 AA7 MAB1_4
MAA0_5 J26 MAA0_4 MAA1_4 H16 MAA1_5 MAB0_5 N9 MAB0_4 MAB1_4 AA8 MAB1_5
MAA0_6 H21 MAA0_5 MAA1_5 J17 MAA1_6 MAB0_6 U9 MAB0_5 MAB1_5 Y8 MAB1_6
MAA0_7 G21 MAA0_6 MAA1_6 H17 MAA1_7 MAB0_7 U8 MAB0_6 MAB1_6 AA9 MAB1_7
MAA0_8 H23 MAA0_7 MAA1_7 J19 MAA1_8 MAB0_8 T8 MAB0_7 MAB1_7 W8 MAB1_8
MAA0_8 MAA1_8 MAB0_8 MAB1_8
p.4 WCKA0_0 A32 C14 WCKA1_0 p.4 p.5 WCKB0_0 H3 AE4 WCKB1_0 p.5
C32 WCKA0_0 WCKA1_0 A14 H1 WCKB0_0 WCKB1_0 AF5
p.4 WCKA0b_0 WCKA0B_0 WCKA1B_0 WCKA1b_0 p.4 p.5 WCKB0b_0 WCKB0B_0 WCKB1B_0 WCKB1b_0 p.5
D23 E10 T3 AK6
p.4 WCKA0_1 WCKA0_1 WCKA1_1 WCKA1_1 p.4 p.5 WCKB0_1 WCKB0_1 WCKB1_1 WCKB1_1 p.5
p.4 WCKA0b_1 E22 D9 WCKA1b_1 p.4 p.5 WCKB0b_1 T5 AK5 WCKB1b_1 p.5
WCKA0B_1 WCKA1B_1 WCKB0B_1 WCKB1B_1
B B
p.4 EDCA0_0 C34 A E16 EDCA1_0 p.4 p.5 EDCB0_0 F6 A AB5 EDCB1_0 p.5
D29 EDCA0_0 EDCA1_0 E12 K3 EDCB0_0 EDCB1_0 AH1
p.4 EDCA0_1 EDCA0_1 N EDCA1_1 EDCA1_1 p.4 p.5 EDCB0_1 EDCB0_1 N EDCB1_1 EDCB1_1 p.5
p.4 EDCA0_2 D25 J10 EDCA1_2 p.4 p.5 EDCB0_2 P3 AJ9 EDCB1_2 p.5
p.4 EDCA0_3 E20 EDCA0_2 K EDCA1_2 D7 EDCA1_3 p.4 p.5 EDCB0_3 V5 EDCB0_2 K EDCB1_2 AM5 EDCB1_3 p.5
EDCA0_3 EDCA1_3 EDCB0_3 EDCB1_3
p.4 DDBIA0_0 A34 C16 DDBIA1_0 p.4 p.5 DDBIB0_0 G7 AC4 DDBIB1_0 p.5
E30 DDBIA0_0 A DDBIA1_0 C12 K1 DDBIB0_0 B DDBIB1_0 AH3
p.4 DDBIA0_1 DDBIA0_1 DDBIA1_1 DDBIA1_1 p.4 p.5 DDBIB0_1 DDBIB0_1 DDBIB1_1 DDBIB1_1 p.5
p.4 DDBIA0_2 E26 J11 DDBIA1_2 p.4 p.5 DDBIB0_2 P1 AJ8 DDBIB1_2 p.5
C20 DDBIA0_2 DDBIA1_2 F8 W4 DDBIB0_2 DDBIB1_2 AM3
p.4 DDBIA0_3 DDBIA0_3 DDBIA1_3 DDBIA1_3 p.4 p.5 DDBIB0_3 DDBIB0_3 DDBIB1_3 DDBIB1_3 p.5
p.4 ADBIA0 J21 G19 ADBIA1 p.4 p.5 ADBIB0 T7 W7 ADBIB1 p.5
ADBIA0 ADBIA1 ADBIB0 ADBIB1
p.4 CSA0b_0 K24 M13 CSA1b_0 p.4 p.5 CSB0b_0 P10 AD10 CSB1b_0 p.5
K27 CSA0B_0 CSA1B_0 K16 L10 CSB0B_0 CSB1B_0 AC10
CSA0B_1 CSA1B_1 CSB0B_1 CSB1B_1
K20 K17 W10 AA10
p.4 CASA0b CASA0B CASA1B CASA1b p.4 p.5 CASB0b CASB0B CASB1B CASB1b p.5
p.4 RASA0b K23 K19 RASA1b p.4 p.5 RASB0b T10 Y10 RASB1b p.5
K26 RASA0B RASA1B L15 N10 RASB0B RASB1B AB11
p.4 WEA0b WEA0B WEA1B WEA1b p.4 p.5 WEB0b WEB0B WEB1B WEB1b p.5
p.4 CKEA0 K21 J20 CKEA1 p.4 p.5 CKEB0 U10 AA11 CKEB1 p.5
CKEA0 CKEA1 CKEB0 CKEB1
p.4 CLKA0 H27 J14 CLKA1 p.4 p.5 CLKB0 L9 AD8 CLKB1 p.5
B
G27 CLKA0 CLKA1 H14 L8 CLKB0 CLKB1 AD7 B
p.4 CLKA0b CLKA0B CLKA1B CLKA1b p.4 p.5 CLKB0b CLKB0B CLKB1B CLKB1b p.5
+MVDD +MVDD
R3605 R3606
40.2R 40.2R
1% 1%
L18 MVREFD_A Y12 MVREFD_B
MVREFDA MVREFDB
C3603
R3608 MVREFD/S =0.7* C3602 R3607
MVREFD/S =0.7* 1uF_6.3V
100R
+MVDD +MVDD 243R R3603 MEM_CALRP0 M27 1uF_6.3V
100R
+MVDD
1% 243R R3604 MEM_CALRN0 L27 MEM_CALRP0 VDDR1 1%
VDDR1 MEM_CALRN0
(GDDR3/4/5)
(GDDR3/4/5) 243R
243R
R3601
R3602
MEM_CALRP1
MEM_CALRN1
M12
N12 MEM_CALRP1
R3609 MEM_CALRN1 R3610
40.2R 243R R3613 MEM_CALRP2 AH12 40.2R
1% 243R R3614 MEM_CALRN2 AG12 MEM_CALRP2 1%
R3615 51.1R DRST AH11 L20 MVREFS_A MEM_CALRN2 AA12 MVREFS_B
p.4,5 DRAM_RST DRAM_RST MVREFSA MVREFSB
R3611 NOT FOR PRODUCTION ‐ FOR BACKUP ONLY; R3612

C3608 R3600 JUNIPER XT A12 HF MVD SLT BIN1 TSMC FB12 C3606 JUNIPER XT A12 HF MVD SLT BIN1 TSMC FB12 C3607
100R 100R
10K 120pF_50V 1uF_6.3V 1uF_6.3V
1% 1%
PLEASE SEE BOM FOR QUALIFIED VALUES
A A

50
Title RH JUNIPER GDDR5 1GB DP+DP/HDMI+DVI /sVGA Doc No.
102-C01301-00
5 4 3 2 1
5 4 3 2 1
(4) GDDR5 x16 MEM Channel A CH_A0 =U2000 & U2100 CH_A1 =U2200 & U2300 p.3 DQA1_[31..0] U2300 GDDR5 +MVDD
U2000 GDDR5 +MVDD U2100 GDDR5 +MVDD U2200 GDDR5 +MVDD M2 B1

p.3 DQA0_[31..0] DQ31 | DQ7 VDDQ-B1
p.3 DQA0_[31..0] p.3 DQA1_[31..0] M4 B3
M2 B1 M2 B1 M2 B1 N2 DQ30 | DQ6 VDDQ-B3 B12
M4 DQ31 | DQ7 VDDQ-B1 B3 M4 DQ31 | DQ7 VDDQ-B1 B3 M4 DQ31 | DQ7 VDDQ-B1 B3 N4 DQ29 | DQ5 VDDQ-B12 B14
N2 DQ30 | DQ6 VDDQ-B3 B12 N2 DQ30 | DQ6 VDDQ-B3 B12 N2 DQ30 | DQ6 VDDQ-B3 B12 T2 DQ28 | DQ4 VDDQ-B14 D1
N4 DQ29 | DQ5 VDDQ-B12 B14 N4 DQ29 | DQ5 VDDQ-B12 B14 N4 DQ29 | DQ5 VDDQ-B12 B14 T4 DQ27 | DQ3 VDDQ-D1 D3
T2 DQ28 | DQ4 VDDQ-B14 D1 T2 DQ28 | DQ4 VDDQ-B14 D1 T2 DQ28 | DQ4 VDDQ-B14 D1 V2 DQ26 | DQ2 VDDQ-D3 D12
T4 DQ27 | DQ3 VDDQ-D1 D3 T4 DQ27 | DQ3 VDDQ-D1 D3 T4 DQ27 | DQ3 VDDQ-D1 D3 V4 DQ25 | DQ1 VDDQ-D12 D14
V2 DQ26 | DQ2 VDDQ-D3 D12 V2 DQ26 | DQ2 VDDQ-D3 D12 V2 DQ26 | DQ2 VDDQ-D3 D12 DQA1_26 M13 DQ24 | DQ0 VDDQ-D14 E5
V4 DQ25 | DQ1 VDDQ-D12 D14 V4 DQ25 | DQ1 VDDQ-D12 D14 V4 DQ25 | DQ1 VDDQ-D12 D14 DQA1_27 M11 DQ23 | DQ15 VDDQ-E5 E10
DQA0_17 M13 DQ24 | DQ0 VDDQ-D14 E5 DQA0_4 M13 DQ24 | DQ0 VDDQ-D14 E5 DQA1_15 M13 DQ24 | DQ0 VDDQ-D14 E5 DQA1_28 N13 DQ22 | DQ14 VDDQ-E10 F1
DQA0_16 M11 DQ23 | DQ15 VDDQ-E5 E10 DQA0_3 M11 DQ23 | DQ15 VDDQ-E5 E10 DQA1_14 M11 DQ23 | DQ15 VDDQ-E5 E10 DQA1_25 N11 DQ21 | DQ13 VDDQ-F1 F3
DQA0_18 N13 DQ22 | DQ14 VDDQ-E10 F1 DQA0_2 N13 DQ22 | DQ14 VDDQ-E10 F1 DQA1_13 N13 DQ22 | DQ14 VDDQ-E10 F1 DQA1_24 T13 DQ20 | DQ12 VDDQ-F3 F12
DQA0_19 N11 DQ21 | DQ13 VDDQ-F1 F3 DQA0_0 N11 DQ21 | DQ13 VDDQ-F1 F3 DQA1_8 N11 DQ21 | DQ13 VDDQ-F1 F3 DQA1_29 T11 DQ19 | DQ11 VDDQ-F12 F14
D
DQA0_20 T13 DQ20 | DQ12 VDDQ-F3 F12 DQA0_1 T13 DQ20 | DQ12 VDDQ-F3 F12 DQA1_12 T13 DQ20 | DQ12 VDDQ-F3 F12 DQA1_30 V13 DQ18 | DQ10 VDDQ-F14 G2 D
DQA0_23 T11 DQ19 | DQ11 VDDQ-F12 F14 DQA0_6 T11 DQ19 | DQ11 VDDQ-F12 F14 DQA1_10 T11 DQ19 | DQ11 VDDQ-F12 F14 DQA1_31 V11 DQ17 | DQ9 VDDQ-G2 G13
DQA0_21 V13 DQ18 | DQ10 VDDQ-F14 G2 DQA0_7 V13 DQ18 | DQ10 VDDQ-F14 G2 DQA1_11 V13 DQ18 | DQ10 VDDQ-F14 G2 F13 DQ16 | DQ8 VDDQ-G13 H3
DQA0_22 V11 DQ17 | DQ9 VDDQ-G2 G13 DQA0_5 V11 DQ17 | DQ9 VDDQ-G2 G13 DQA1_9 V11 DQ17 | DQ9 VDDQ-G2 G13 F11 DQ15 | DQ23 VDDQ-H3 H12
F13 DQ16 | DQ8 VDDQ-G13 H3 F13 DQ16 | DQ8 VDDQ-G13 H3 F13 DQ16 | DQ8 VDDQ-G13 H3 E13 DQ14 | DQ22 VDDQ-H12 K3
F11 DQ15 | DQ23 VDDQ-H3 H12 F11 DQ15 | DQ23 VDDQ-H3 H12 F11 DQ15 | DQ23 VDDQ-H3 H12 E11 DQ13 | DQ21 VDDQ-K3 K12
E13 DQ14 | DQ22 VDDQ-H12 K3 E13 DQ14 | DQ22 VDDQ-H12 K3 E13 DQ14 | DQ22 VDDQ-H12 K3 B13 DQ12 | DQ20 VDDQ-K12 L2
DQ13 | DQ21 VDDQ-K3 M=1 DQ13 | DQ21 VDDQ-K3 M=1 DQ13 | DQ21 VDDQ-K3 DQ11 | DQ19 VDDQ-L2
E11 K12 E11 K12 E11 K12 B11 L13
B13 DQ12 | DQ20 VDDQ-K12 L2 Mirror B13 DQ12 | DQ20 VDDQ-K12 L2 Mirror B13 DQ12 | DQ20 VDDQ-K12 L2 A13 DQ10 | DQ18 VDDQ-L13 M1
B11 DQ11 | DQ19 VDDQ-L2 L13 B11 DQ11 | DQ19 VDDQ-L2 L13 B11 DQ11 | DQ19 VDDQ-L2 L13 A11 DQ9 | DQ17 VDDQ-M1 M3
A13 DQ10 | DQ18 VDDQ-L13 M1 A13 DQ10 | DQ18 VDDQ-L13 M1 A13 DQ10 | DQ18 VDDQ-L13 M1 DQA1_1 F2 DQ8 | DQ16 VDDQ-M3 M12
A11 DQ9 | DQ17 VDDQ-M1 M3 A11 DQ9 | DQ17 VDDQ-M1 M3 A11 DQ9 | DQ17 VDDQ-M1 M3 DQA1_0 F4 DQ7 | DQ31 VDDQ-M12 M14
DQA0_10 F2 DQ8 | DQ16 VDDQ-M3 M12 DQA0_31 F2 DQ8 | DQ16 VDDQ-M3 M12 DQA1_23 F2 DQ8 | DQ16 VDDQ-M3 M12 DQA1_2 E2 DQ6 | DQ30 VDDQ-M14 N5
DQA0_8 F4 DQ7 | DQ31 VDDQ-M12 M14 DQA0_29 F4 DQ7 | DQ31 VDDQ-M12 M14 DQA1_22 F4 DQ7 | DQ31 VDDQ-M12 M14 DQA1_3 E4 DQ5 | DQ29 VDDQ-N5 N10
DQA0_11 E2 DQ6 | DQ30 VDDQ-M14 N5 DQA0_30 E2 DQ6 | DQ30 VDDQ-M14 N5 DQA1_20 E2 DQ6 | DQ30 VDDQ-M14 N5 DQA1_4 B2 DQ4 | DQ28 VDDQ-N10 P1
DQA0_9 E4 DQ5 | DQ29 VDDQ-N5 N10 DQA0_28 E4 DQ5 | DQ29 VDDQ-N5 N10 DQA1_21 E4 DQ5 | DQ29 VDDQ-N5 N10 DQA1_6 B4 DQ3 | DQ27 VDDQ-P1 P3
DQA0_12 B2 DQ4 | DQ28 VDDQ-N10 P1 DQA0_26 B2 DQ4 | DQ28 VDDQ-N10 P1 DQA1_16 B2 DQ4 | DQ28 VDDQ-N10 P1 DQA1_5 A2 DQ2 | DQ26 VDDQ-P3 P12
DQA0_13 B4 DQ3 | DQ27 VDDQ-P1 P3 DQA0_25 B4 DQ3 | DQ27 VDDQ-P1 P3 DQA1_18 B4 DQ3 | DQ27 VDDQ-P1 P3 DQA1_7 A4 DQ1 | DQ25 VDDQ-P12 P14
DQA0_14 A2 DQ2 | DQ26 VDDQ-P3 P12 DQA0_27 A2 DQ2 | DQ26 VDDQ-P3 P12 DQA1_19 A2 DQ2 | DQ26 VDDQ-P3 P12 DQ0 | DQ24 VDDQ-P14 T1
DQA0_15 A4 DQ1 | DQ25 VDDQ-P12 P14 DQA0_24 A4 DQ1 | DQ25 VDDQ-P12 P14 DQA1_17 A4 DQ1 | DQ25 VDDQ-P12 P14 VDDQ-T1 T3
DQ0 | DQ24 VDDQ-P14 T1 DQ0 | DQ24 VDDQ-P14 T1 DQ0 | DQ24 VDDQ-P14 T1 VDDQ-T3 T12
VDDQ-T1 T3 VDDQ-T1 T3 VDDQ-T1 T3 VDDQ-T12 T14
VDDQ-T3 T12 VDDQ-T3 T12 VDDQ-T3 T12 VDDQ-T14
VDDQ-T12 VDDQ-T12 VDDQ-T12 p.3 MAA1_[8..0] +MVDD
T14 T14 T14 MAA1_8 J5
VDDQ-T14 +MVDD VDDQ-T14 +MVDD VDDQ-T14 +MVDD MAA1_7 K4 RFU/A12/NC C5
p.3 MAA0_[8..0] p.3 MAA0_[8..0] p.3 MAA1_[8..0] A7/A8 | A0/A10 VDD-C5
MAA0_8 J5 MAA0_8 J5 MAA1_8 J5 MAA1_6 K5 C10
MAA0_7 K4 RFU/A12/NC C5 MAA0_0 K4 RFU/A12/NC C5 MAA1_0 K4 RFU/A12/NC C5 MAA1_5 K10 A6/A11 | A1/A9 VDD-C10 D11
MAA0_6 K5 A7/A8 | A0/A10 VDD-C5 C10 MAA0_1 K5 A7/A8 | A0/A10 VDD-C5 C10 MAA1_1 K5 A7/A8 | A0/A10 VDD-C5 C10 MAA1_4 K11 A5/BA1 | A3/BA3 VDD-D11 G1
MAA0_5 K10 A6/A11 | A1/A9 VDD-C10 D11 MAA0_3 K10 A6/A11 | A1/A9 VDD-C10 D11 MAA1_3 K10 A6/A11 | A1/A9 VDD-C10 D11 MAA1_3 H10 A4/BA2 | A2/BA0 VDD-G1 G4
MAA0_4 K11 A5/BA1 | A3/BA3 VDD-D11 G1 MAA0_2 K11 A5/BA1 | A3/BA3 VDD-D11 G1 MAA1_2 K11 A5/BA1 | A3/BA3 VDD-D11 G1 MAA1_2 H11 A3/BA3 | A5/BA1 VDD-G4 G11
MAA0_3 H10 A4/BA2 | A2/BA0 VDD-G1 G4 MAA0_5 H10 A4/BA2 | A2/BA0 VDD-G1 G4 MAA1_5 H10 A4/BA2 | A2/BA0 VDD-G1 G4 MAA1_1 H5 A2 /BA0 | A4/BA2 VDD-G11 G14
MAA0_2 H11 A3/BA3 | A5/BA1 VDD-G4 G11 MAA0_4 H11 A3/BA3 | A5/BA1 VDD-G4 G11 MAA1_4 H11 A3/BA3 | A5/BA1 VDD-G4 G11 MAA1_0 H4 A1/A9 | A6/A11 VDD-G14 L1
MAA0_1 H5 A2 /BA0 | A4/BA2 VDD-G11 G14 MAA0_6 H5 A2 /BA0 | A4/BA2 VDD-G11 G14 MAA1_6 H5 A2 /BA0 | A4/BA2 VDD-G11 G14 A0/A10 | A7/A8 VDD-L1 L4
MAA0_0 H4 A1/A9 | A6/A11 VDD-G14 L1 MAA0_7 H4 A1/A9 | A6/A11 VDD-G14 L1 MAA1_7 H4 A1/A9 | A6/A11 VDD-G14 L1 VDD-L4 L11
A0/A10 | A7/A8 VDD-L1 L4 A0/A10 | A7/A8 VDD-L1 L4 A0/A10 | A7/A8 VDD-L1 L4 VDD-L11 L14
VDD-L4 L11 VDD-L4 L11 VDD-L4 L11 D4 VDD-L14 P11
VDD-L11 VDD-L11 VDD-L11 p.3 WCKA1_0 WCK01 | WCK23 VDD-P11
L14 L14 L14 D5 R5
VDD-L14 VDD-L14 VDD-L14 p.3 WCKA1b_0 WCK01# | WCK23# VDD-R5
C D4 P11 D4 P11 D4 P11 R10 C
p.3 WCKA0_0 WCK01 | WCK23 VDD-P11 p.3 WCKA0_1 WCK01 | WCK23 VDD-P11 p.3 WCKA1_1 WCK01 | WCK23 VDD-P11 VDD-R10
D5 R5 D5 R5 D5 R5 P4
p.3 WCKA0b_0 WCK01# | WCK23# VDD-R5 p.3 WCKA0b_1 WCK01# | WCK23# VDD-R5 p.3 WCKA1b_1 WCK01# | WCK23# VDD-R5 p.3 WCKA1_1 WCK23 | WCK01
R10 R10 R10 P5
VDD-R10 VDD-R10 VDD-R10 p.3 WCKA1b_1 WCK23# | WCK01#
P4 P4 P4 A1
p.3 WCKA0_1 WCK23 | WCK01 p.3 WCKA0_0 WCK23 | WCK01 p.3 WCKA1_0 WCK23 | WCK01 VSSQ-A1
P5 P5 P5 R2 A3
p.3 WCKA0b_1 WCK23# | WCK01# p.3 WCKA0b_0 WCK23# | WCK01# p.3 WCKA1b_0 WCK23# | WCK01# EDC3 | EDC0 VSSQ-A3
A1 A1 A1 p.3 EDCA1_3 R13 A12
R2 VSSQ-A1 A3 R2 VSSQ-A1 A3 R2 VSSQ-A1 A3 C13 EDC2 | EDC1 VSSQ-A12 A14
R13 EDC3 | EDC0 VSSQ-A3 A12 R13 EDC3 | EDC0 VSSQ-A3 A12 R13 EDC3 | EDC0 VSSQ-A3 A12 C2 EDC1 | EDC2 VSSQ-A14 C1
p.3 EDCA0_2 EDC2 | EDC1 VSSQ-A12 p.3 EDCA0_0 EDC2 | EDC1 VSSQ-A12 p.3 EDCA1_1 EDC2 | EDC1 VSSQ-A12 p.3 EDCA1_0 EDC0 | EDC3 VSSQ-C1
C13 A14 C13 A14 C13 A14 C3
C2 EDC1 | EDC2 VSSQ-A14 C1 C2 EDC1 | EDC2 VSSQ-A14 C1 C2 EDC1 | EDC2 VSSQ-A14 C1 P2 VSSQ-C3 C4
p.3 EDCA0_1 EDC0 | EDC3 VSSQ-C1 p.3 EDCA0_3 EDC0 | EDC3 VSSQ-C1 p.3 EDCA1_2 EDC0 | EDC3 VSSQ-C1 +MVDD DBI3# | DBI0# VSSQ-C4
C3 C3 C3 p.3 DDBIA1_3 P13 C11
P2 VSSQ-C3 C4 P2 VSSQ-C3 C4 P2 VSSQ-C3 C4 D13 DBI2 #| DBI1# VSSQ-C11 C12
+MVDD DBI3# | DBI0# VSSQ-C4 +MVDD DBI3# | DBI0# VSSQ-C4 +MVDD DBI3# | DBI0# VSSQ-C4 +MVDD DBI1# | DBI2# VSSQ-C12
p.3 DDBIA0_2 P13 C11 p.3 DDBIA0_0 P13 C11 p.3 DDBIA1_1 P13 C11 p.3 DDBIA1_0 D2 C14
D13 DBI2 #| DBI1# VSSQ-C11 C12 D13 DBI2 #| DBI1# VSSQ-C11 C12 D13 DBI2 #| DBI1# VSSQ-C11 C12 DBI0# | DBI3# VSSQ-C14 E1
+MVDD DBI1# | DBI2# VSSQ-C12 +MVDD DBI1# | DBI2# VSSQ-C12 +MVDD DBI1# | DBI2# VSSQ-C12 VSSQ-E1
p.3 DDBIA0_1 D2 C14 p.3 DDBIA0_3 D2 C14 p.3 DDBIA1_2 D2 C14 E3
DBI0# | DBI3# VSSQ-C14 E1 DBI0# | DBI3# VSSQ-C14 E1 DBI0# | DBI3# VSSQ-C14 E1 VSSQ-E3 E12
VSSQ-E1 E3 VSSQ-E1 E3 VSSQ-E1 E3 +MVDD G3 VSSQ-E12 E14
VSSQ-E3 VSSQ-E3 VSSQ-E3 p.3 RASA1b RAS# | CAS# VSSQ-E14
E12 E12 E12 p.3 CASA1b L3 F5
+MVDD G3 VSSQ-E12 E14 +MVDD G3 VSSQ-E12 E14 +MVDD G3 VSSQ-E12 E14 R2305 120R CAS# | RAS# VSSQ-F5 F10
p.3 RASA0b RAS# | CAS# VSSQ-E14 p.3 CASA0b RAS# | CAS# VSSQ-E14 p.3 CASA1b RAS# | CAS# VSSQ-E14 VSSQ-F10
p.3 CASA0b L3 F5 p.3 RASA0b L3 F5 p.3 RASA1b L3 F5 R2304 120R H2
R2003 120R CAS# | RAS# VSSQ-F5 F10 R2103 120R CAS# | RAS# VSSQ-F5 F10 R2203 120R CAS# | RAS# VSSQ-F5 F10 J3 VSSQ-H2 H13
VSSQ-F10 VSSQ-F10 VSSQ-F10 p.3 CKEA1 CKE# VSSQ-H13
R2004 120R H2 R2104 120R H2 R2204 120R H2 J11 K2
VSSQ-H2 VSSQ-H2 VSSQ-H2 p.3 CLKA1b CK# VSSQ-K2
p.3 CKEA0 J3 H13 p.3 CKEA0 J3 H13 p.3 CKEA1 J3 H13 J12 K13
CKE# VSSQ-H13 CKE# VSSQ-H13 CKE# VSSQ-H13 p.3 CLKA1 CK VSSQ-K13
J11 K2 J11 K2 J11 K2 M5
p.3 CLKA0b CK# VSSQ-K2 p.3 CLKA0b CK# VSSQ-K2 p.3 CLKA1b CK# VSSQ-K2 VSSQ-M5
J12 K13 J12 K13 J12 K13 M10
p.3 CLKA0 CK VSSQ-K13 p.3 CLKA0 CK VSSQ-K13 p.3 CLKA1 CK VSSQ-K13 VSSQ-M10
M5 M5 M5 p.3 CSA1b_0 G12 N1
VSSQ-M5 M10 VSSQ-M5 M10 VSSQ-M5 M10 L12 CS# | WE# VSSQ-N1 N3
VSSQ-M10 VSSQ-M10 VSSQ-M10 p.3 WEA1b WE# | CS# VSSQ-N3
p.3 CSA0b_0 G12 N1 p.3 WEA0b G12 N1 p.3 WEA1b G12 N1 N12
L12 CS# | WE# VSSQ-N1 N3 L12 CS# | WE# VSSQ-N1 N3 L12 CS# | WE# VSSQ-N1 N3 VSSQ-N12 N14
p.3 WEA0b WE# | CS# VSSQ-N3 p.3 CSA0b_0 WE# | CS# VSSQ-N3 p.3 CSA1b_0 WE# | CS# VSSQ-N3 VSSQ-N14
N12 N12 N12 R2302 120R 1% J13 R1
VSSQ-N12 N14 VSSQ-N12 N14 VSSQ-N12 N14 J10 ZQ VSSQ-R1 R3
R2002 120R 1% J13 VSSQ-N14 R1 R2101 120R 1% J13 VSSQ-N14 R1 R2201 120R1% J13 VSSQ-N14 R1 SEN VSSQ-R3 R4
J10 ZQ VSSQ-R1 R3 J10 ZQ VSSQ-R1 R3 J10 ZQ VSSQ-R1 R3 VSSQ-R4 R11
SEN VSSQ-R3 R4 SEN VSSQ-R3 R4 SEN VSSQ-R3 R4 J2 VSSQ-R11 R12
VSSQ-R4 VSSQ-R4 VSSQ-R4 p.3,5 DRAM_RST RESET# VSSQ-R12
R11 R11 R11 J1 R14
J2 VSSQ-R11 R12 J2 VSSQ-R11 R12 J2 VSSQ-R11 R12 MF VSSQ-R14 V1
p.3,5 DRAM_RST RESET# VSSQ-R12 p.3,5 DRAM_RST RESET# VSSQ-R12 p.3,5 DRAM_RST RESET# VSSQ-R12 VSSQ-V1
J1 R14 J1 R14 J1 R14 V3
MF VSSQ-R14 +MVDD MF VSSQ-R14 +MVDD MF VSSQ-R14 VSSQ-V3
V1 V1 V1 +MEM_VREF V12
B VSSQ-V1 V3 VSSQ-V1 V3 +MEM_VREF VSSQ-V1 V3 VSSQ-V12 V14 B
+MEM_VREF VSSQ-V3 V12 +MEM_VREF VSSQ-V3 V12 VSSQ-V3 V12 A5 VSSQ-V14
VSSQ-V12 V14 VSSQ-V12 V14 VSSQ-V12 V14 V5 Vpp,NC
A5 VSSQ-V14 A5 VSSQ-V14 A5 VSSQ-V14 Vpp,NC1 B5
V5 Vpp,NC V5 Vpp,NC V5 Vpp,NC C2344 A10 VSS-B5 B10
Vpp,NC1 B5 Vpp,NC1 B5 C2242 Vpp,NC1 B5 V10 VREFD1 VSS-B10 D10
VSS-B5 VSS-B5 VSS-B5 100nF_6.3V VREFD2 VSS-D10
C2003 A10 B10 C2139 A10 B10 100nF_6.3V A10 B10 G5
V10 VREFD1 VSS-B10 D10 V10 VREFD1 VSS-B10 D10 V10 VREFD1 VSS-B10 D10 VSS-G5 G10
100nF_6.3V VREFD2 VSS-D10 100nF_6.3V VREFD2 VSS-D10 VREFD2 VSS-D10 VSS-G10
G5 G5 G5 H1
VSS-G5 G10 VSS-G5 G10 VSS-G5 G10 C2343 1uF_6.3V VSS-H1 H14
VSS-G10 H1 VSS-G10 H1 VSS-G10 H1 R2309 2.37K 1% VSS-H14 K1
VSS-H1 VSS-H1 VSS-H1 +MVDD VSS-K1
C2004 1uF_6.3V H14 C2138 1uF_6.3V H14 C2239 1uF_6.3V H14 R2310 5.49K 1% VREFC_B1 J14 K14
R2009 1% 2.37K 1% VSS-H14 K1 R2109 1% 2.37K 1% VSS-H14 K1 R2209 1% 2.37K 1% VSS-H14 K1 C2345 1uF_6.3V VREFC VSS-K14 L5
+MVDD VSS-K1 +MVDD VSS-K1 +MVDD VSS-K1 VSS-L5
R2010 5.49K 1% VREFC_A0 J14 K14 R2110 VREFC_A1
5.49K 1% VREFC_A1 J14 K14 R2210 5.49K 1% VREFC_B0 J14 K14 L10
C2005 1uF_6.3V VREFC VSS-K14 L5 C2140 1uF_6.3V VREFC VSS-K14 L5 C2241 1uF_6.3V VREFC VSS-K14 L5 VSS-L10 P10
VSS-L5 L10 VSS-L5 L10 VSS-L5 L10 J4 VSS-P10 T5
VSS-L10 VSS-L10 VSS-L10 p.3 ADBIA1 ABI# VSS-T5
P10 P10 P10 T10
J4 VSS-P10 T5 J4 VSS-P10 T5 J4 VSS-P10 T5 VSS-T10
p.3 ADBIA0 ABI# VSS-T5 p.3 ADBIA0 ABI# VSS-T5 p.3 ADBIA1 ABI# VSS-T5
T10 T10 T10
VSS-T10 VSS-T10 VSS-T10 23F41GB7ME50
+MVDD
23F41GB7ME50 23F41GB7ME50 23F41GB7ME50
C2305 1uF_6.3V
C2306 1uF_6.3V
C2308 1uF_6.3V
C2312 1uF_6.3V
C2313 2.2uF_4V
C2315 2.2uF_4V
C2316 2.2uF_4V
C2317 1uF_6.3V
C2321 1uF_6.3V
C2322 1uF_6.3V
C2323 2.2uF_4V
C2324 2.2uF_4V
+MVDD Use internal Vref memory voltage +MVDD +MVDD
+MVDD
C2010 2.2uF_4V
C2000 1uF_6.3V
C2001 2.2uF_4V
C2011 2.2uF_4V
C2013 1uF_6.3V
C2014 2.2uF_4V
C2019 1uF_6.3V
C2020 1uF_6.3V
C2021 1uF_6.3V
C2024 1uF_6.3V
C2025 1uF_6.3V
C2145 1uF_6.3V
C2101 1uF_6.3V
C2102 1uF_6.3V
C2103 1uF_6.3V
C2108 1uF_6.3V
C2109 2.2uF_4V
C2110 1uF_6.3V
C2111 1uF_6.3V
C2112 1uF_6.3V
C2113 2.2uF_4V
C2114 1uF_6.3V
C2115 2.2uF_4V
C2116 1uF_6.3V
C2117 1uF_6.3V
C2119 1uF_6.3V
C2200 1uF_6.3V
C2202 1uF_6.3V
C2203 1uF_6.3V
C2205 2.2uF_4V
C2207 2.2uF_4V
C2208 1uF_6.3V
C2209 1uF_6.3V
C2210 2.2uF_4V
C2211 1uF_6.3V
C2212 1uF_6.3V
C2213 1uF_6.3V
C2214 2.2uF_4V
C2215 2.2uF_4V
C2217 1uF_6.3V
C2218 1uF_6.3V
+MVDD +MVDD
C2340 2.2uF_4V
C2330 2.2uF_4V
C2331 2.2uF_4V
C2325 2.2uF_4V
C2332 2.2uF_4V
C2327 1uF_6.3V
C2328 2.2uF_4V
C2329 1uF_6.3V
C2341 1uF_6.3V
C2342 1uF_6.3V
C2326 1uF_6.3V
C2333 1uF_6.3V
C2337 10uF
C2338 10uF
C2339 10uF
A A
C2335 10uF
C2336 10uF
+MVDD
+MVDD +MVDD
+MVDD +MVDD +MVDD +MVDD
+MVDD +MVDD CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
C2041
C2042
C2038
C2039
C2036
C2037
C2034
C2027
C2028

C2135
C2136
C2137
C2127
C2126
C2128
C2129
C2122
C2133
C2134
C2236
C2237
C2227
C2221
C2235
C2234
C2228
C2222
C2223
C2226
C2225
C2232
C2121 10uF
C2132 10uF
C2124 10uF
C2125 10uF
C2130 10uF
C2224 10uF
C2229 10uF
C2233 10uF
C2230 10uF
C2231 10uF
C2040 10uF
C2026 10uF
C2030 10uF
C2031 10uF
C2032 10uF
2.2uF_4V
2.2uF_4V
2.2uF_4V
1uF_6.3V
2.2uF_4V
1uF_6.3V
1uF_6.3V
1uF_6.3V
1uF_6.3V

1uF_6.3V
1uF_6.3V
2.2uF_4V
1uF_6.3V
2.2uF_4V
2.2uF_4V
2.2uF_4V
1uF_6.3V
1uF_6.3V
1uF_6.3V
2.2uF_4V
2.2uF_4V
2.2uF_4V
1uF_6.3V
1uF_6.3V
2.2uF_4V
2.2uF_4V
1uF_6.3V
1uF_6.3V
1uF_6.3V
1uF_6.3V
1uF_6.3V
50
Title Doc No.
5 4 3 2 1
5 4 3 2 1
(5) GDDR5 x16 MEM Channel B U2400 +MVDD

CH_B0 =U2400 & U2500
BOTTOM
CH_B1 =U2600 & U2700
TOP
M2 B1 U2500 GDDR5 +MVDD U2600 GDDR5 +MVDD
M4 DQ31 | DQ7 VDDQ-B1 B3 U2700 +MVDD
p.3 DQB0_[31..0] DQ30 | DQ6 VDDQ-B3 p.3 DQB0_[31..0] p.3 DQB1_[31..0] p.3 DQB1_[31..0] GDDR5
N2 B12 M2 B1 M2 B1
N4 DQ29 | DQ5 VDDQ-B12 B14 M4 DQ31 | DQ7 VDDQ-B1 B3 M4 DQ31 | DQ7 VDDQ-B1 B3 M2 B1
T2 DQ28 | DQ4 VDDQ-B14 D1 N2 DQ30 | DQ6 VDDQ-B3 B12 N2 DQ30 | DQ6 VDDQ-B3 B12 M4 DQ31 | DQ7 VDDQ-B1 B3
T4 DQ27 | DQ3 VDDQ-D1 D3 N4 DQ29 | DQ5 VDDQ-B12 B14 N4 DQ29 | DQ5 VDDQ-B12 B14 N2 DQ30 | DQ6 VDDQ-B3 B12
V2 DQ26 | DQ2 VDDQ-D3 D12 T2 DQ28 | DQ4 VDDQ-B14 D1 T2 DQ28 | DQ4 VDDQ-B14 D1 N4 DQ29 | DQ5 VDDQ-B12 B14
V4 DQ25 | DQ1 VDDQ-D12 D14 T4 DQ27 | DQ3 VDDQ-D1 D3 T4 DQ27 | DQ3 VDDQ-D1 D3 T2 DQ28 | DQ4 VDDQ-B14 D1
DQB0_17 M13 DQ24 | DQ0 VDDQ-D14 E5 V2 DQ26 | DQ2 VDDQ-D3 D12 V2 DQ26 | DQ2 VDDQ-D3 D12 T4 DQ27 | DQ3 VDDQ-D1 D3
DQB0_16 M11 DQ23 | DQ15 VDDQ-E5 E10 V4 DQ25 | DQ1 VDDQ-D12 D14 V4 DQ25 | DQ1 VDDQ-D12 D14 V2 DQ26 | DQ2 VDDQ-D3 D12
DQB0_18 N13 DQ22 | DQ14 VDDQ-E10 F1 DQB0_2 M13 DQ24 | DQ0 VDDQ-D14 E5 DQB1_15 M13 DQ24 | DQ0 VDDQ-D14 E5 V4 DQ25 | DQ1 VDDQ-D12 D14
DQB0_19 N11 DQ21 | DQ13 VDDQ-F1 F3 DQB0_4 M11 DQ23 | DQ15 VDDQ-E5 E10 DQB1_14 M11 DQ23 | DQ15 VDDQ-E5 E10 DQB1_26 M13 DQ24 | DQ0 VDDQ-D14 E5
DQB0_20 T13 DQ20 | DQ12 VDDQ-F3 F12 DQB0_1 N13 DQ22 | DQ14 VDDQ-E10 F1 DQB1_13 N13 DQ22 | DQ14 VDDQ-E10 F1 DQB1_25 M11 DQ23 | DQ15 VDDQ-E5 E10
DQB0_23 T11 DQ19 | DQ11 VDDQ-F12 F14 DQB0_3 N11 DQ21 | DQ13 VDDQ-F1 F3 DQB1_8 N11 DQ21 | DQ13 VDDQ-F1 F3 DQB1_27 N13 DQ22 | DQ14 VDDQ-E10 F1
D
DQB0_21 V13 DQ18 | DQ10 VDDQ-F14 G2 DQB0_0 T13 DQ20 | DQ12 VDDQ-F3 F12 DQB1_12 T13 DQ20 | DQ12 VDDQ-F3 F12 DQB1_24 N11 DQ21 | DQ13 VDDQ-F1 F3 D
DQB0_22 V11 DQ17 | DQ9 VDDQ-G2 G13 DQB0_5 T11 DQ19 | DQ11 VDDQ-F12 F14 DQB1_10 T11 DQ19 | DQ11 VDDQ-F12 F14 DQB1_30 T13 DQ20 | DQ12 VDDQ-F3 F12
F13 DQ16 | DQ8 VDDQ-G13 H3 DQB0_7 V13 DQ18 | DQ10 VDDQ-F14 G2 DQB1_11 V13 DQ18 | DQ10 VDDQ-F14 G2 DQB1_28 T11 DQ19 | DQ11 VDDQ-F12 F14
F11 DQ15 | DQ23 VDDQ-H3 H12 DQB0_6 V11 DQ17 | DQ9 VDDQ-G2 G13 DQB1_9 V11 DQ17 | DQ9 VDDQ-G2 G13 DQB1_29 V13 DQ18 | DQ10 VDDQ-F14 G2
E13 DQ14 | DQ22 VDDQ-H12 K3 F13 DQ16 | DQ8 VDDQ-G13 H3 F13 DQ16 | DQ8 VDDQ-G13 H3 DQB1_31 V11 DQ17 | DQ9 VDDQ-G2 G13
E11 DQ13 | DQ21 VDDQ-K3 K12 F11 DQ15 | DQ23 VDDQ-H3 H12 F11 DQ15 | DQ23 VDDQ-H3 H12 F13 DQ16 | DQ8 VDDQ-G13 H3
B13 DQ12 | DQ20 VDDQ-K12 L2 E13 DQ14 | DQ22 VDDQ-H12 K3 E13 DQ14 | DQ22 VDDQ-H12 K3 F11 DQ15 | DQ23 VDDQ-H3 H12
DQ11 | DQ19 VDDQ-L2 M=1 DQ13 | DQ21 VDDQ-K3 M=1 DQ13 | DQ21 VDDQ-K3 DQ14 | DQ22 VDDQ-H12
B11 L13 E11 K12 E11 K12 E13 K3
A13 DQ10 | DQ18 VDDQ-L13 M1 Mirror B13 DQ12 | DQ20 VDDQ-K12 L2 Mirror B13 DQ12 | DQ20 VDDQ-K12 L2 E11 DQ13 | DQ21 VDDQ-K3 K12
A11 DQ9 | DQ17 VDDQ-M1 M3 B11 DQ11 | DQ19 VDDQ-L2 L13 B11 DQ11 | DQ19 VDDQ-L2 L13 B13 DQ12 | DQ20 VDDQ-K12 L2
DQB0_10 F2 DQ8 | DQ16 VDDQ-M3 M12 A13 DQ10 | DQ18 VDDQ-L13 M1 A13 DQ10 | DQ18 VDDQ-L13 M1 B11 DQ11 | DQ19 VDDQ-L2 L13
DQB0_9 F4 DQ7 | DQ31 VDDQ-M12 M14 A11 DQ9 | DQ17 VDDQ-M1 M3 A11 DQ9 | DQ17 VDDQ-M1 M3 A13 DQ10 | DQ18 VDDQ-L13 M1
DQB0_11 E2 DQ6 | DQ30 VDDQ-M14 N5 DQB0_31 F2 DQ8 | DQ16 VDDQ-M3 M12 DQB1_22 F2 DQ8 | DQ16 VDDQ-M3 M12 A11 DQ9 | DQ17 VDDQ-M1 M3
DQB0_8 E4 DQ5 | DQ29 VDDQ-N5 N10 DQB0_29 F4 DQ7 | DQ31 VDDQ-M12 M14 DQB1_21 F4 DQ7 | DQ31 VDDQ-M12 M14 DQB1_1 F2 DQ8 | DQ16 VDDQ-M3 M12
DQB0_14 B2 DQ4 | DQ28 VDDQ-N10 P1 DQB0_30 E2 DQ6 | DQ30 VDDQ-M14 N5 DQB1_20 E2 DQ6 | DQ30 VDDQ-M14 N5 DQB1_0 F4 DQ7 | DQ31 VDDQ-M12 M14
DQB0_15 B4 DQ3 | DQ27 VDDQ-P1 P3 DQB0_28 E4 DQ5 | DQ29 VDDQ-N5 N10 DQB1_23 E4 DQ5 | DQ29 VDDQ-N5 N10 DQB1_2 E2 DQ6 | DQ30 VDDQ-M14 N5
DQB0_13 A2 DQ2 | DQ26 VDDQ-P3 P12 DQB0_26 B2 DQ4 | DQ28 VDDQ-N10 P1 DQB1_19 B2 DQ4 | DQ28 VDDQ-N10 P1 DQB1_3 E4 DQ5 | DQ29 VDDQ-N5 N10
DQB0_12 A4 DQ1 | DQ25 VDDQ-P12 P14 DQB0_25 B4 DQ3 | DQ27 VDDQ-P1 P3 DQB1_16 B4 DQ3 | DQ27 VDDQ-P1 P3 DQB1_5 B2 DQ4 | DQ28 VDDQ-N10 P1
DQ0 | DQ24 VDDQ-P14 T1 DQB0_27 A2 DQ2 | DQ26 VDDQ-P3 P12 DQB1_18 A2 DQ2 | DQ26 VDDQ-P3 P12 DQB1_6 B4 DQ3 | DQ27 VDDQ-P1 P3
VDDQ-T1 T3 DQB0_24 A4 DQ1 | DQ25 VDDQ-P12 P14 DQB1_17 A4 DQ1 | DQ25 VDDQ-P12 P14 DQB1_4 A2 DQ2 | DQ26 VDDQ-P3 P12
VDDQ-T3 T12 DQ0 | DQ24 VDDQ-P14 T1 DQ0 | DQ24 VDDQ-P14 T1 DQB1_7 A4 DQ1 | DQ25 VDDQ-P12 P14
VDDQ-T12 T14 VDDQ-T1 T3 VDDQ-T1 T3 DQ0 | DQ24 VDDQ-P14 T1
VDDQ-T14 +MVDD VDDQ-T3 T12 VDDQ-T3 T12 VDDQ-T1 T3
p.3 MAB0_[8..0] VDDQ-T12 VDDQ-T12 VDDQ-T3
MAB0_8 J5 T14 T14 T12
MAB0_7 K4 RFU/A12/NC C5 VDDQ-T14 +MVDD VDDQ-T14 +MVDD VDDQ-T12 T14
A7/A8 | A0/A10 VDD-C5 p.3 MAB0_[8..0] p.3 MAB1_[8..0] VDDQ-T14
MAB0_6 K5 C10 MAB0_8 J5 MAB1_8 J5 p.3 MAB1_[8..0]
MAB0_5 K10 A6/A11 | A1/A9 VDD-C10 D11 MAB0_0 K4 RFU/A12/NC C5 MAB1_0 K4 RFU/A12/NC C5 MAB1_8 J5 +MVDD
MAB0_4 K11 A5/BA1 | A3/BA3 VDD-D11 G1 MAB0_1 K5 A7/A8 | A0/A10 VDD-C5 C10 MAB1_1 K5 A7/A8 | A0/A10 VDD-C5 C10 MAB1_7 K4 RFU/A12/NC C5
MAB0_3 H10 A4/BA2 | A2/BA0 VDD-G1 G4 MAB0_3 K10 A6/A11 | A1/A9 VDD-C10 D11 MAB1_3 K10 A6/A11 | A1/A9 VDD-C10 D11 MAB1_6 K5 A7/A8 | A0/A10 VDD-C5 C10
MAB0_2 H11 A3/BA3 | A5/BA1 VDD-G4 G11 MAB0_2 K11 A5/BA1 | A3/BA3 VDD-D11 G1 MAB1_2 K11 A5/BA1 | A3/BA3 VDD-D11 G1 MAB1_5 K10 A6/A11 | A1/A9 VDD-C10 D11
MAB0_1 H5 A2 /BA0 | A4/BA2 VDD-G11 G14 MAB0_5 H10 A4/BA2 | A2/BA0 VDD-G1 G4 MAB1_5 H10 A4/BA2 | A2/BA0 VDD-G1 G4 MAB1_4 K11 A5/BA1 | A3/BA3 VDD-D11 G1
MAB0_0 H4 A1/A9 | A6/A11 VDD-G14 L1 MAB0_4 H11 A3/BA3 | A5/BA1 VDD-G4 G11 MAB1_4 H11 A3/BA3 | A5/BA1 VDD-G4 G11 MAB1_3 H10 A4/BA2 | A2/BA0 VDD-G1 G4
A0/A10 | A7/A8 VDD-L1 L4 MAB0_6 H5 A2 /BA0 | A4/BA2 VDD-G11 G14 MAB1_6 H5 A2 /BA0 | A4/BA2 VDD-G11 G14 MAB1_2 H11 A3/BA3 | A5/BA1 VDD-G4 G11
VDD-L4 L11 MAB0_7 H4 A1/A9 | A6/A11 VDD-G14 L1 MAB1_7 H4 A1/A9 | A6/A11 VDD-G14 L1 MAB1_1 H5 A2 /BA0 | A4/BA2 VDD-G11 G14
VDD-L11 L14 A0/A10 | A7/A8 VDD-L1 L4 A0/A10 | A7/A8 VDD-L1 L4 MAB1_0 H4 A1/A9 | A6/A11 VDD-G14 L1
D4 VDD-L14 P11 VDD-L4 L11 VDD-L4 L11 A0/A10 | A7/A8 VDD-L1 L4
p.3 WCKB0_0 WCK01 | WCK23 VDD-P11 VDD-L11 VDD-L11 VDD-L4
D5 R5 L14 L14 L11
p.3 WCKB0b_0 WCK01# | WCK23# VDD-R5 VDD-L14 VDD-L14 VDD-L11
C R10 D4 P11 D4 P11 L14 C
VDD-R10 p.3 WCKB0_1 WCK01 | WCK23 VDD-P11 p.3 WCKB1_1 WCK01 | WCK23 VDD-P11 VDD-L14
P4 D5 R5 D5 R5 D4 P11
p.3 WCKB0_1 WCK23 | WCK01 p.3 WCKB0b_1 WCK01# | WCK23# VDD-R5 p.3 WCKB1b_1 WCK01# | WCK23# VDD-R5 p.3 WCKB1_0 WCK01 | WCK23 VDD-P11
P5 R10 R10 D5 R5
p.3 WCKB0b_1 WCK23# | WCK01# VDD-R10 VDD-R10 p.3 WCKB1b_0 WCK01# | WCK23# VDD-R5
A1 P4 P4 R10
VSSQ-A1 p.3 WCKB0_0 WCK23 | WCK01 p.3 WCKB1_0 WCK23 | WCK01 VDD-R10
R2 A3 P5 P5 P4
EDC3 | EDC0 VSSQ-A3 p.3 WCKB0b_0 WCK23# | WCK01# p.3 WCKB1b_0 WCK23# | WCK01# p.3 WCKB1_1 WCK23 | WCK01
p.3 EDCB0_2 R13 A12 A1 A1 P5
EDC2 | EDC1 VSSQ-A12 VSSQ-A1 VSSQ-A1 p.3 WCKB1b_1 WCK23# | WCK01#
C13 A14 R2 A3 R2 A3 A1
C2 EDC1 | EDC2 VSSQ-A14 C1 R13 EDC3 | EDC0 VSSQ-A3 A12 R13 EDC3 | EDC0 VSSQ-A3 A12 R2 VSSQ-A1 A3
p.3 EDCB0_1 EDC0 | EDC3 VSSQ-C1 p.3 EDCB0_0 EDC2 | EDC1 VSSQ-A12 p.3 EDCB1_1 EDC2 | EDC1 VSSQ-A12 EDC3 | EDC0 VSSQ-A3
C3 C13 A14 C13 A14 p.3 EDCB1_3 R13 A12
P2 VSSQ-C3 C4 C2 EDC1 | EDC2 VSSQ-A14 C1 C2 EDC1 | EDC2 VSSQ-A14 C1 C13 EDC2 | EDC1 VSSQ-A12 A14
+MVDD DBI3# | DBI0# VSSQ-C4 p.3 EDCB0_3 EDC0 | EDC3 VSSQ-C1 p.3 EDCB1_2 EDC0 | EDC3 VSSQ-C1 EDC1 | EDC2 VSSQ-A14
p.3 DDBIB0_2 P13 C11 C3 C3 p.3 EDCB1_0 C2 C1
D13 DBI2 #| DBI1# VSSQ-C11 C12 P2 VSSQ-C3 C4 P2 VSSQ-C3 C4 EDC0 | EDC3 VSSQ-C1 C3
+MVDD DBI1# | DBI2# VSSQ-C12 +MVDD DBI3# | DBI0# VSSQ-C4 +MVDD DBI3# | DBI0# VSSQ-C4 VSSQ-C3
p.3 DDBIB0_1 D2 C14 p.3 DDBIB0_0 P13 C11 p.3 DDBIB1_1 P13 C11 +MVDD P2 C4
DBI0# | DBI3# VSSQ-C14 E1 D13 DBI2 #| DBI1# VSSQ-C11 C12 D13 DBI2 #| DBI1# VSSQ-C11 C12 P13 DBI3# | DBI0# VSSQ-C4 C11
VSSQ-E1 +MVDD DBI1# | DBI2# VSSQ-C12 +MVDD DBI1# | DBI2# VSSQ-C12 p.3 DDBIB1_3 DBI2 #| DBI1# VSSQ-C11
E3 p.3 DDBIB0_3 D2 C14 p.3 DDBIB1_2 D2 C14 +MVDD D13 C12
VSSQ-E3 E12 DBI0# | DBI3# VSSQ-C14 E1 DBI0# | DBI3# VSSQ-C14 E1 D2 DBI1# | DBI2# VSSQ-C12 C14
+MVDD VSSQ-E12 VSSQ-E1 VSSQ-E1 p.3 DDBIB1_0 DBI0# | DBI3# VSSQ-C14
G3 E14 E3 E3 E1
p.3 RASB0b RAS# | CAS# VSSQ-E14 VSSQ-E3 VSSQ-E3 VSSQ-E1
p.3 CASB0b L3 F5 E12 E12 E3
R2403 120R CAS# | RAS# VSSQ-F5 F10 +MVDD G3 VSSQ-E12 E14 +MVDD G3 VSSQ-E12 E14 VSSQ-E3 E12
VSSQ-F10 p.3 CASB0b RAS# | CAS# VSSQ-E14 p.3 CASB1b RAS# | CAS# VSSQ-E14 +MVDD VSSQ-E12
R2404 120R H2 p.3 RASB0b L3 F5 p.3 RASB1b L3 F5 p.3 RASB1b G3 E14
J3 VSSQ-H2 H13 R2503 120R CAS# | RAS# VSSQ-F5 F10 R2603 120R CAS# | RAS# VSSQ-F5 F10 L3 RAS# | CAS# VSSQ-E14 F5
p.3 CKEB0 CKE# VSSQ-H13 VSSQ-F10 VSSQ-F10 p.3 CASB1b CAS# | RAS# VSSQ-F5
J11 K2 R2504 120R H2 R2604 120R H2 R2703 120R F10
p.3 CLKB0b CK# VSSQ-K2 VSSQ-H2 VSSQ-H2 VSSQ-F10
J12 K13 p.3 CKEB0 J3 H13 p.3 CKEB1 J3 H13 R2704 120R H2
p.3 CLKB0 CK VSSQ-K13 CKE# VSSQ-H13 CKE# VSSQ-H13 VSSQ-H2
M5 J11 K2 J11 K2 p.3 CKEB1 J3 H13
VSSQ-M5 p.3 CLKB0b CK# VSSQ-K2 p.3 CLKB1b CK# VSSQ-K2 CKE# VSSQ-H13
M10 J12 K13 J12 K13 J11 K2
VSSQ-M10 p.3 CLKB0 CK VSSQ-K13 p.3 CLKB1 CK VSSQ-K13 p.3 CLKB1b CK# VSSQ-K2
p.3 CSB0b_0 G12 N1 M5 M5 J12 K13
CS# | WE# VSSQ-N1 VSSQ-M5 VSSQ-M5 p.3 CLKB1 CK VSSQ-K13
L12 N3 M10 M10 M5
p.3 WEB0b WE# | CS# VSSQ-N3 VSSQ-M10 VSSQ-M10 VSSQ-M5
N12 p.3 WEB0b G12 N1 p.3 WEB1b G12 N1 M10
VSSQ-N12 N14 L12 CS# | WE# VSSQ-N1 N3 L12 CS# | WE# VSSQ-N1 N3 G12 VSSQ-M10 N1
VSSQ-N14 p.3 CSB0b_0 WE# | CS# VSSQ-N3 p.3 CSB1b_0 WE# | CS# VSSQ-N3 p.3 CSB1b_0 CS# | WE# VSSQ-N1
R2400 120R 1% J13 R1 N12 N12 p.3 WEB1b L12 N3
J10 ZQ VSSQ-R1 R3 VSSQ-N12 N14 VSSQ-N12 N14 WE# | CS# VSSQ-N3 N12
SEN VSSQ-R3 R4 R2501 120R 1% J13 VSSQ-N14 R1 R2601 120R 1% J13 VSSQ-N14 R1 VSSQ-N12 N14
VSSQ-R4 R11 J10 ZQ VSSQ-R1 R3 J10 ZQ VSSQ-R1 R3 R2700 120R 1% J13 VSSQ-N14 R1
J2 VSSQ-R11 R12 SEN VSSQ-R3 R4 SEN VSSQ-R3 R4 J10 ZQ VSSQ-R1 R3
p.3,4 DRAM_RST RESET# VSSQ-R12 VSSQ-R4 VSSQ-R4 SEN VSSQ-R3
J1 R14 R11 R11 R4
MF VSSQ-R14 V1 J2 VSSQ-R11 R12 J2 VSSQ-R11 R12 VSSQ-R4 R11
VSSQ-V1 p.3,4 DRAM_RST RESET# VSSQ-R12 p.3,4 DRAM_RST RESET# VSSQ-R12 VSSQ-R11
+MEM_VREF V3 J1 R14 J1 R14 J2 R12
VSSQ-V3 +MVDD MF VSSQ-R14 +MVDD MF VSSQ-R14 p.3,4 DRAM_RST RESET# VSSQ-R12
V12 V1 V1 J1 R14
B VSSQ-V12 V14 +MEM_VREF VSSQ-V1 V3 VSSQ-V1 V3 MF VSSQ-R14 V1 B
A5 VSSQ-V14 VSSQ-V3 V12 +MEM_VREF VSSQ-V3 V12 +MEM_VREF VSSQ-V1 V3
V5 Vpp,NC VSSQ-V12 V14 VSSQ-V12 V14 VSSQ-V3 V12
C2400 Vpp,NC1 B5 A5 VSSQ-V14 A5 VSSQ-V14 VSSQ-V12 V14
A10 VSS-B5 B10 V5 Vpp,NC V5 Vpp,NC A5 VSSQ-V14
100nF_6.3V VREFD1 VSS-B10 Vpp,NC1 Vpp,NC1 Vpp,NC
V10 D10 C2544 B5 B5 V5
VREFD2 VSS-D10 G5 A10 VSS-B5 B10 C2640 A10 VSS-B5 B10 C2701 Vpp,NC1 B5
VSS-G5 100nF_6.3V VREFD1 VSS-B10 VREFD1 VSS-B10 VSS-B5
G10 V10 D10 100nF_6.3V V10 D10 100nF_6.3V A10 B10
VSS-G10 H1 VREFD2 VSS-D10 G5 VREFD2 VSS-D10 G5 V10 VREFD1 VSS-B10 D10
C2401 1uF_6.3V VSS-H1 H14 VSS-G5 G10 VSS-G5 G10 VREFD2 VSS-D10 G5
R2409 2.37K 1% VSS-H14 K1 VSS-G10 H1 VSS-G10 H1 VSS-G5 G10
+MVDD VSS-K1 VSS-H1 VSS-H1 VSS-G10
R2410 5.49K 1% VREFC_C0 J14 K14 C2539 1uF_6.3V H14 C2639 1uF_6.3V H14 H1
C2403 1uF_6.3V VREFC VSS-K14 L5 R2509 2.37K 1% VSS-H14 K1 R2609 2.37K 1% VSS-H14 K1 C2702 1uF_6.3V VSS-H1 H14
VSS-L5 +MVDD VSS-K1 +MVDD VSS-K1 VSS-H14
L10 R2510 5.49K 1% VREFC_C1 J14 K14 R2610 5.49K 1% VREFC_D0 J14 K14 R2709 2.37K 1% K1
VSS-L10 VREFC VSS-K14 VREFC VSS-K14 +MVDD VSS-K1
P10 C2541 1uF_6.3V L5 C2641 1uF_6.3V L5 R2710 5.49K 1% VREFC_D1 J14 K14
J4 VSS-P10 T5 VSS-L5 L10 VSS-L5 L10 C2700 1uF_6.3V VREFC VSS-K14 L5
p.3 ADBIB0 ABI# VSS-T5 VSS-L10 VSS-L10 VSS-L5
T10 P10 P10 L10
VSS-T10 J4 VSS-P10 T5 J4 VSS-P10 T5 VSS-L10 P10
p.3 ADBIB0 ABI# VSS-T5 p.3 ADBIB1 ABI# VSS-T5 VSS-P10
T10 T10 J4 T5
VSS-T10 VSS-T10 p.3 ADBIB1 ABI# VSS-T5
23F41GB7ME50 T10
VSS-T10
23F41GB7ME50 23F41GB7ME50 +MVDD
23F41GB7ME50
+MVDD
+MVDD +MVDD
C2707 2.2uF_4V
C2712 1uF_6.3V
C2713 2.2uF_4V
C2715 1uF_6.3V
C2717 2.2uF_4V
C2718 1uF_6.3V
C2719 1uF_6.3V
C2721 2.2uF_4V
C2722 1uF_6.3V
C2723 2.2uF_4V
C2724 1uF_6.3V
C2406 2.2uF_4V
C2407 2.2uF_4V
C2408 2.2uF_4V
C2410 2.2uF_4V
C2413 1uF_6.3V
C2414 1uF_6.3V
C2417 2.2uF_4V
C2418 2.2uF_4V
C2419 2.2uF_4V
C2421 1uF_6.3V
C2422 2.2uF_4V
C2423 1uF_6.3V
C2503 1uF_6.3V
C2504 2.2uF_4V
C2506 1uF_6.3V
C2508 1uF_6.3V
C2509 1uF_6.3V
C2510 1uF_6.3V
C2511 2.2uF_4V
C2512 2.2uF_4V
C2513 1uF_6.3V
C2514 1uF_6.3V
C2515 1uF_6.3V
C2516 1uF_6.3V
C2519 1uF_6.3V
C2520 1uF_6.3V
C2600 1uF_6.3V
C2643 1uF_6.3V
C2604 1uF_6.3V
C2606 1uF_6.3V
C2607 1uF_6.3V
C2608 1uF_6.3V
C2609 1uF_6.3V
C2612 2.2uF_4V
C2613 2.2uF_4V
C2614 2.2uF_4V
C2615 1uF_6.3V
C2617 1uF_6.3V
C2618 2.2uF_4V
C2620 2.2uF_4V
+MVDD
+MVDD +MVDD
C2734 2.2uF_4V
C2733 1uF_6.3V
C2742 2.2uF_4V
C2743 2.2uF_4V
C2726 2.2uF_4V
C2727 2.2uF_4V
C2732 2.2uF_4V
C2730 2.2uF_4V
C2731 1uF_6.3V
C2729 1uF_6.3V
C2728 1uF_6.3V
C2741 1uF_6.3V
C2735 1uF_6.3V
C2736 10uF
C2737 10uF
C2738 10uF
C2739 10uF
C2740 10uF
A A
+MVDD +MVDD +MVDD

+MVDD +MVDD +MVDD +MVDD
+MVDD +MVDD
C2444
C2435
C2436
C2434
C2430
C2405
C2431
C2443
C2441
C2432
C2438
C2439
C2442
C2538
C2536
C2537
C2525
C2526
C2521
C2532
C2527
C2522
C2529
C2523
C2638 1uF_6.3V
C2631 2.2uF_4V
C2621 1uF_6.3V
C2622 2.2uF_4V
C2623 2.2uF_4V
C2628 2.2uF_4V
C2632 2.2uF_4V
C2626 1uF_6.3V
C2627 1uF_6.3V
C2637 1uF_6.3V
C2636 1uF_6.3V
C2629 1uF_6.3V

C2433 10uF
C2428 10uF
C2437 10uF
C2440 10uF
C2429 10uF
C2625 10uF
C2633 10uF
C2635 10uF
C2630 10uF
C2634 10uF
C2535 10uF
C2524 10uF
C2530 10uF
C2533 10uF
C2534 10uF

2.2uF_4V
2.2uF_4V
2.2uF_4V
2.2uF_4V
1uF_6.3V
2.2uF_4V
2.2uF_4V
1uF_6.3V
1uF_6.3V
1uF_6.3V
1uF_6.3V
1uF_6.3V
1uF_6.3V
2.2uF_4V
1uF_6.3V
2.2uF_4V
1uF_6.3V
1uF_6.3V
2.2uF_4V
1uF_6.3V
2.2uF_4V
1uF_6.3V
1uF_6.3V
1uF_6.3V
50
102-C01301-00
5 4 3 2 1
5 4 3 2 1
(06) JUNIPER GPIOs Strap CF XTAL OSC
+3.3V_BUS
U1E
+3.3V_BUS
PART 5 OF 15 +3.3V_BUS BIOS1
AF23 AH20 GPIO_0 GPIO_0 VIDEO BIOS
AF24 VDDR3#1 GPIO_0 AH18 GPIO_1 GPIO_1 FIRMWARE
AG23 VDDR3#2 GPIO_1 AN16 GPIO_2 GPIO_2 BIOS
C1 C2 C3 R22 R27 AG24 VDDR3#3 GPIO_2 AH23 GPIO_3_SMBDATA
VDDR3#4 GPIO_3_SMBDATA GPIO_3_SMBDATA p.1
100nF_6.3V 100nF_6.3V 100nF_6.3V 2.2K 2.2K AJ23 GPIO_4_SMBCLK R14
GPIO_4_SMBCLK GPIO_4_SMBCLK p.1
AH17 GPIO_5 2.2K 113-C013XX-XXX +3.3V_BUS
D GPIO_5_AC_BATT GPIO_5 p.17 D
AJ17 GPIO_6_TACH U11
GPIO_6_TACH GPIO_6_TACH p.18
p.17 SCL SCL AK26 AK17 GPIO_7 35mil TP92 1 8
SDA AJ26 SCL GPIO_7_BLON AJ13 GPIO_8 3 33R 6 RP1C GPIO_8_R 2 CE# VCC 7
p.17 SDA SDA GPIO_8_ROMSO SO HOLD#
AH15 GPIO_9 1 33R 8 RP1A 3 6 GPIO_10_R
GPIO_9_ROMSI AJ16 GPIO_10 2 33R 7 RP1B 4 WP# SCK 5 GPIO_9_R C4
GPIO_10_ROMSCK AK16 GPIO_11 GND SI 100nF_6.3V
AJ30 GPIO_11 AL16 GPIO_12 PM25LV010A-100SCE
DDC6CLK G GPIO_12
AJ31 AM16 GPIO_13
DDC6DATA P GPIO_13 AM14 GPIO_14_HPD2
GPIO_14_HPD2 GPIO_14_HPD2 p.9
I AM13 GPIO_15_PWRCNTL_0
GPIO_15_PWRCNTL_0 GPIO_15_PWRCNTL_0 p.17
AK14 GPIO_16 TP93 1Mbit ROM
SCL / SDA BUS: O GPIO_16_SSIN AG30 GPIO_17_ThermINT
GPIO_17_THERMAL_INT GPIO_17_ThermINT p.17,18,19
AN14 TP98
I2C Address Function Device GPIO_18_HPD3 AM17 GPIO_19_CTF
GPIO_19_CTF GPIO_19_CTF p.18
AF35 AL13 GPIO_20_PWRCNTL_1
0x80 Write VDDC CONTROLLER AG36 RSVD#1 GPIO_20_PWRCNTL_1 AJ14
GPIO_20_PWRCNTL_1 p.17 PIN BASED STRAPS
0x81 Read ST AJ27 RSVD#2 GPIO_21_BB_EN AK13 GPIO_22_ROMCSb 4 33R 5 RP1D GPIO_22_ROMCSb_R
AK27 RSVD#3 GPIO_22_ROMCSB AN13 +3.3V_BUS
0x70 VDDC CONTROLLER UPI RSVD#4 GPIO_23_CLKREQB
CLKREQ# requires open drain connection,
AN36 R1 10K GPIO_0 GPIO(0) - TX_PWRS_ENB (Transmitter Power Savings Enable)
0xA0, 0xA2 MVDDQ, MVDDC, VDDCI AP37 RSVD#6 AJ19 GENERICA CONNECT AT ASIC and cannot be used as pinstrap DNI 0: 50% Tx output swing for mobile mode
0xA4 VREF CONTROL UP6266 RSVD#7 GENERICA AK19 GENERICB 1: full Tx output swing (Default setting for Desktop)
GENERICB AJ20
GENERICC AK20 GENERICD DNI R2 10K GPIO_1 GPIO(1) - TX_DEEMPH_EN (Transmitter De-emphasis Enable)
DDC6 BUS: GENERICD AJ24 GENERICE_HPD4 DNI 0: Tx de-emphasis disabled for mobile mode
GENERICE_HPD4 GENERICE_HPD4 p.9
AH26 GENERICF_HPD5 GENERICF_HPD5 p.9
1: Tx de-emphasis enabled (Default setting for Desktop)
I2C Address Function Device GENERICF_HPD5 AH24 N29218647 TP97
AJ21 GENERICG_HPD6 DNI GPIO_2 GPIO(2) - BIF_GEN2_EN (5.0 GT/s Enable)
AK21 NC#1 AK24 DNI 0 : Default. (Driver Controlled Gen2)
NC#2 HPD1 HPD1 p.8
AH16 1 : Strap Controlled Gen2
PWRGOOD
0x98 LM96163 - External JUNIPER XT A12 HF MVD SLT BIN1 TSMC FB12 DNI GPIO_9_R VGA DISABLE : 1 for disable (set to 0 for normal operation)
Temperature Sensor LM96163 PWRGOOD: DNI
Upper Cable Card Edge or Bundle B
Internal Singal.
+1.8V Bring to 0R PD for R6 10K GPIO_13 GPIO(13,12,11) - CONFIG[2..0]
verification. DNI 100 - 512Kbit M25P05A (ST)
C NOTE: If connecting DNI GPIO_12 CONFIG[2] 101 - 1Mbit M25P10A (ST) C
1V_LDO_POK, only one DNI 101 - 2Mbit M25P20 (ST)
pull up either to 1.8V or R8 10K GPIO_11 CONFIG[1] 101 - 4Mbit
101 - 8Mbit
M25P40
M25P80
(ST)
(ST)
3.3V DNI
100 - 512Kbit Pm25LV512 (Chingis)
DNI CONFIG[0] 101 - 1Mbit
p.15 1.8V_LDO_POK
PWRGOOD
CrossFire Card-Edge Pm25LV010 (Chingis)
V2SYNC - VIP_DEVICE_STRAP_DIS
DNI R9 10K V2SYNC p.7 1: Driver would ignore the value sampled on VHAD_0
p.1,15,18 1V_LDO_POK DNI during reset
R33
0: Driver would use the value sampled at reset from
1K VHAD_0 to determine whether or not a VIP slave device
DNI
(e.g. Theater chip) is connected
RESERVED:
R10 10K V1SYNC V1SYNC p.7
+1.8V U1F DNI Internal use only. Other logic must not affect these signals
DNI R11 10K H1SYNC H1SYNC p.7 during RESET.
PART 6 OF 15 DNI
AD12 AU1 DVPDATA_0 35mil TP60 DNI H2SYNC H2SYNC p.7 BIF_CLK_PM_EN
AF11 VDDR4#1 DVPDATA_0 AU3 DVPDATA_1 35mil TP61 DNI 0 - Disable CLKREQ# power management capability
AF12 VDDR4#2 DVPDATA_1 AW3 DVPDATA_2 35mil TP62 DNI GPIO_8_R 1 - Enable CLKREQ# power management capability
DNI C5 C6 C7 AF13 VDDR4#3 DVPDATA_2 AP6 DVPDATA_3 35mil TP63 DNI
1uF_6.3V 1uF_6.3V 1uF_6.3V AF15 VDDR4#4 DVPDATA_3 AW5 DVPDATA_4 35mil TP64 Don't set GENERICC high at reset
AG11 VDDR4#5 DVPDATA_4 AU5 DVPDATA_5 35mil TP65
AG13 VDDR4#6 DVPDATA_5 AR6 DVPDATA_6 35mil TP66
AG15 VDDR4#7 DVPDATA_6 AW6 DVPDATA_7 35mil TP67 Lower Cable Card Edge
VDDR4#8 DVPDATA_7 AU6 DVPDATA_8 35mil TP68
DVPDATA_8 AT7 DVPDATA_9 35mil TP69
or Bundle A (closer to the bracket) +3.3V_BUS
DVPDATA_9 AV7 DVPDATA_10 35mil TP70 1 2 J2
DVPDATA_10 AN7 DVPDATA_11 35mil TP71 DVOCLK 3 4 B8 BLM15AG121SN1D
DVPDATA_11 5 6 B9 BLM15AG121SN1D
D
AV9 DVPCNTL_2 7 8 Y2
TP84 35mil DVOCLK AR1 V DVPDATA_12 AT9 9 10 DVPDATA_0 27.000MHz_10PPM_30R
DVPCLK DVPDATA_13 AR10 11 12 XOUT_OSC_GENA 1 3XIN_OSC_GENA
P DVPDATA_14
DVPDATA_1 C38 C39
TP85 35mil DVPCNTL_0 AP8 AW10 13 14 DVPDATA_2 2 4 100nF_6.3V 100nF_6.3V +3.3V_BUS
TP86 35mil DVPCNTL_1 AW8 DVPCNTL_0 DVPDATA_15 AU10 DVPDATA_3 15 16
TP87 35mil DVPCNTL_2 AR3 DVPCNTL_1 DVPDATA_16 AP10 17 18 DVPDATA_4 U2
B DVPCNTL_2 DVPDATA_17 AV11 DVPDATA_5 19 20 C36 20pF_50V 10 1 C37 B
DVPDATA_18 XTALOUT XTALIN
5.1K
AR8 AT11 21 22 DVPDATA_6 20pF_50V
AU8 DVPCNTL_MVP_0 DVPDATA_19 AR12 DVPDATA_7 23 24 4 VDD33_100M_GENA
DVPCNTL_MVP_1 DVPDATA_20 AW12 25 26 DVPDATA_8 MR34 10R CLK_100M_GENA 5 VDD_100M 8 VDD33_27M_GENA
+1.8V DVPDATA_21 100M_OUT VDD_27M
R30
AU12 DVPDATA_9 27 28
R17 221R VREFG AH13 DVPDATA_22 AP12 29 30 DVPDATA_10 7 SS_SEL0_GENA
R18 110R VREFG DVPDATA_23 DVPDATA_11 31 32 OVERLAP R34/MR34 SS_SEL0 3 SS_SEL1_GENA
C8 100nF_6.3V 33 34 DVPCNTL_0 9 SS_SEL1
27M_OUT
5.1K
5.1K
JUNIPER XT A12 HF MVD SLT BIN1 TSMC FB12 DVPCNTL_1 35 36 6
37 38 GPIO_2 GND_100M 2
GENERICD 39 40 GND_27M 11
GND_PAD
R35
R36
SL16010DCT
+3.3V_BUS
GENERICA_100M GENERICA B2 BLM15AG121SN1D

B3 BLM15AG121SN1D
U1G Y1
FOR 740: DNI R28/TR19 ‐ 27.000MHz_10PPM_30R
+1.8V PART 7 OF 15 XOUT_OSC 1 3 XIN_OSC C9 C10
B1 BLM15AG121SN1D +DPLL_PVDD AM32 XO_IN/2 ARE GND on 740/730 2 4 100nF_6.3V 100nF_6.3V +3.3V_BUS
DPLL_PVDD
C13 C14 C15 U12
100nF_6.3V
5.1K
10uF 1uF_6.3V AN32 C11 20pF_50V 10 1 C12
DPLL_PVSS XTALOUT XTALIN 20pF_50V
+1V 4 VDD33_100M
VDD_100M
R21
P AW35 XO_IN2 R28 10R CLK_100M 5 8 VDD33_27M
B4 BLM15AG121SN1D +DPLL_VDDC AN31 XO_IN2 100M_OUT VDD_27M
DPLL_VDDC L 7 SS_SEL0
SS_SEL0
5.1K
C16 C17 L 3 SS_SEL1
SS_SEL1
5.1K
1uF_6.3V 100nF_6.3V AW34 XO_IN TR19 0R CLK_27M 9
S XO_IN 27M_OUT 6
+1.8V GND_100M 2
GND_27M
MR15
MR16
B5 BLM15AG121SN1D +SPV18 AM10 11
SPV18 X DNI GND_PAD
C18 C19 C20 T SL16010DCT
10uF 1uF_6.3V 100nF_6.3V AN10 AV33 XTALIN DNI R23 221R
SPVSS A XTALIN
A A
L Divider for 1.8V
+1V signaling.
B6 BLM15AG121SN1D +SPV10 AN9 AU34
SPV10 XTALOUT
C21 C22
1uF_6.3V 100nF_6.3V
+1.8V AK10 © 2007 Advanced Micro Devices Advanced Micro Devices Inc.
B7 BLM15AG121SN1D +MPV18 H7 CLKTESTA This AMD Board schematic and design is the exclusive property of AMD,
MPV18#1 and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
H8 AL10 with AMD for evaluation purposes. Further distribution or disclosure
C25 C26 C27 MPV18#2 CLKTESTB is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
10uF 1uF_6.3V 100nF_6.3V other than evaluation requires a Board Technology License Agreement
JUNIPER XT A12 HF MVD SLT BIN1 TSMC FB12 regarding this schematic and design, including, not limited to, Date: Tuesday, November 10, 2009 Rev
50
route 50ohms single‐ended/100ohms diff and keep short purpose, and disclaims responsibility forany consequences resulting Sheet 6
Title Doc No.
5 4 3 2 1
8 7 6 5 4 3 2 1
(07) JUNIPER DAC1 and DAC2
+VDD12DI U1H
PART 8 OF 15
+VDD12DI AC33 AD39
VDD1DI R AD37
RB
AC34
VSS1DI
D D
AE36
G AD35
+AVDD_DAC12
D GB
+AVDD_DAC12 AD34 A +5V_VESA
AVDD
C
AF37
AE34 1 B AE38
AVSSQ BB
AC36 H1SYNC
R1500 499R RSET AB34 HSYNC AC38 V1SYNC A_R_DAC2_F
RSET VSYNC A_G_DAC2_F
A_B_DAC2_F
JUNIPER XT A12 HF MVD SLT BIN1 TSMC FB12 DDC2_MONID0
DDCDATA_DAC2_R
DDC2_MONID2
DDCCLK_DAC2_R
HSYNC_DAC2_R
VSYNC_DAC2_R
p.6 H1SYNC
C C
p.6 V1SYNC
OPTIONAL ESD PROTECTION DIODES
A_R_DAC2_F
A_G_DAC2_F
See BOM for qualified filters
A_B_DAC2_F
Pseudo differential RGB should be routed from the ASIC to the display
connector without switching reference plane or running over split plane. DDCDATA_DAC2_R
+1.8V U1I
+VDD12DI DDCCLK_DAC2_R
PART 9 OF 15
B1600 BLM15AG121SN1D +VDD12DI AG31 AC30 R_DAC2 L1600 HSYNC_DAC2_R
VDD2DI R2 AC31 RB_DAC2 47nH
R2B R1601 VSYNC_DAC2_R
C1600 C1601 C1602 AG32 75R
1uF_6.3V 100nF_6.3V 10nF VSS2DI 402 402 402
AD30 G_DAC2 R1602 37.4R +5V_VESA
G2 AD31 GB_DAC2
+1.8V +AVDD_DAC12 G2B
D
AD33 L1601
B1601 BLM15AG121SN1D +AVDD_DAC12 A2VDDQ A 47nH
C AF30 B_DAC2 R1604 R1605 R1606
AF33 B2 AF31 BB_DAC2 2.2K 2.2K
A2VSSQ 2 B2B 75R
C1607 C1608 402 402 402
1uF_6.3V 100nF_6.3V / R1608 37.4R
A_R_DAC2_F
T AD29 H2SYNC A_G_DAC2_F
A_R_DAC2_F p.8
B H2SYNC A_G_DAC2_F p.8 B
+3.3V_BUS AG33
A2VDD
V V2SYNC
AC29 V2SYNC L1602 A_B_DAC2_F A_B_DAC2_F p.8
47nH
B1602 BLM15AG121SN1D +A2VDD R1609 R1610 33R DDCDATA_DAC2_R
p.8 DDC4DATA DDCDATA_DAC2_R p.8
75R
AD32 402 402 402 R1612 33R DDCCLK_DAC2_R DDCCLK_DAC2_R p.8
Y p.8 DDC4CLK
C1611 C1612 C1613 C1614 AC32 R1613 37.4R
4.7uF_6.3V 1uF_6.3V 100nF_6.3V 10nF AA29 C AF32
R2SET COMP
R2SET
R1600
715R
p.6 H2SYNC 12 11 HSYNC_DAC2_B R1614 24R 402 HSYNC_DAC2_R HSYNC_DAC2_R HSYNC_DAC2_R p.8
U1500D
74VHCT125
10 13
DNI
74VHCT125
U1500C
p.6 V2SYNC 9 8 VSYNC_DAC2_B R1615 24R 402 VSYNC_DAC2_R VSYNC_DAC2_R VSYNC_DAC2_R p.8
DNI
+5V_VESA
C1514
100nF_6.3V U1500A
14
A 74VHCT125 A
2 3
7
1

4
74VHCT125 © 2007 Advanced Micro Devices Advanced Micro Devices Inc.

U1500B This AMD Board schematic and design is the exclusive property of AMD,
5 6 with AMD for evaluation purposes. Further distribution or disclosure
50
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
(08) JUNIPER TMDP A&B dDVI-I TOP

SEE BOM FOR QUALIFIED PARTS
U1J
+1.8V
PART 10 OF 15 R1701 499R
B1700 BLM15AG121SN1D +DPAB_18 AU28 AT27 DPA_TX2P C1701 100nF_6.3V ABTX2P
DPA_PVDD TX2P_DPA0P
AR26 DPA_TX2N C1705 100nF_6.3V ABTX2M
TX2M_DPA0N R1702 499R R1703 499R
AU26 DPA_TX1P C1706 100nF_6.3V ABTX1P
GND AV27 TX1P_DPA1P
D DPA_PVSS AV25 DPA_TX1N C1707 100nF_6.3V ABTX1M D
TX1M_DPA1N R1704 499R R1705 499R
AT25 DPA_TX0P C1708 100nF_6.3V ABTX0P
TX0P_DPA2P
AR24 DPA_TX0N C1709 100nF_6.3V ABTX0M
+DPAB_18 AV29 TX0M_DPA2N R1706 499R R1707 499R
Please pay attention to the grounding DPB_PVDD AU24 DPA_TXCAP C1710 100nF_6.3V ABTXCP
strategies for these filter capacitors to TXCAP_DPA3P
maintain a close loop for current. TXCAM_DPA3N
AV23 DPA_TXCAN C1711 100nF_6.3V ABTXCM
R1708 499R
GND AR28
DPB_PVSS
+1V AM27
AUX1P DPD_AUXP p.9
B1701 BLM15AG121SN1D +DPAB_VDD10 AP31 AL27
DPA_VDD10#1 AUX1N DPD_AUXN p.9
AP32 T
DPA_VDD10#2
C1713 C1714 M AM26 R1820 R1821
DDC1CLK
4.7uF_6.3V 1uF_6.3V D 0R 0R
AN26
P DDC1DATA
AN33
AP33 DPB_VDD10#1 DDCDATA_AUX5N
DPB_VDD10#2 A p.9 DDCDATA_AUX5N
/ p.9 DDCCLK_AUX5P DDCCLK_AUX5P
B
+DPAB_18 AN24
AP24 DPA_VDD18#1
DPA_VDD18#2
C1717 C1718
4.7uF_6.3V 1uF_6.3V
R1709 499R
AT33 DPB_TX5P C1720 100nF_6.3V ABTX5P
AP25 TX5P_DPB0P
AP26 DPB_VDD18#1 AU32 DPB_TX5N C1721 100nF_6.3V ABTX5M
C C
DPB_VDD18#2 TX5M_DPB0N R1710 499R R1711 499R
AR32 DPB_TX4P C1722 100nF_6.3V ABTX4P
TX4P_DPB1P
AT31 DPB_TX4N C1723 100nF_6.3V ABTX4M
TX4M_DPB1N R1712 499R R1713 499R
AV31 DPB_TX3P C1724 100nF_6.3V ABTX3P
150R R1700 DPAB_CALR AW28 TX3P_DPB2P
DPAB_CALR AU30 DPB_TX3N C1725 100nF_6.3V ABTX3M
TX3M_DPB2N R1714 499R
AN27 AR30
AP27 DPA_VSSR#1 TXCBP_DPB3P +12V_BUS
AP28 DPA_VSSR#2 AT29 DPAB_GND +5V_VESA
AW24 DPA_VSSR#3 TXCBM_DPB3N
AW26 DPA_VSSR#4
DPA_VSSR#5
3
AN29 R1717
AP29 DPB_VSSR#1 100K Q1700
AP30 DPB_VSSR#2 AL29 DDC4CLK C1712
DPB_VSSR#3 DDCCLK_AUX4P DDC4CLK p.7 SI2304DS
AW30 p.9 DVI_EN DVI_EN 1 1UF_16V
AW32 DPB_VSSR#4 AM29 DDC4DATA
DPB_VSSR#5 DDCDATA_AUX4N DDC4DATA p.7
J1700
2
C1727 25
JUNIPER XT A12 HF MVD SLT BIN1 TSMC FB12 100nF CASE
16V ABTX2M 1
ABTX2P 2 TMDS Data2-
3 TMDS Data2+
ABTX4M 4 TMDS Data2/4 Shield
DDCCLK_DAC2_R 6 TMDS Data4+
p.7 DDCCLK_DAC2_R DDC Clock
DDCDATA_DAC2_R 7
p.7 DDCDATA_DAC2_R DDC Data
VSYNC_DAC2_R 8
p.7 VSYNC_DAC2_R Analog VSYNC
ABTX1M 9
11 TMDS Data1+
OPTIONAL ESD PROTECTION DIODES 14 TMDS Data3+
15 +5V Power
B
16 GND (for +5V) B
ABTX2P ABTX0M 17 Hot Plug Detect
ABTX2M 19 TMDS Data0+
ABTX1P ABTX5P 21 TMDS Data5-
22 TMDS Data5+
ABTX1M ABTXCP 23 TMDS Clock Shield
ABTXCM 24 TMDS Clock+
ABTX0P TMDS Clock-
A_R_DAC2_F C1
p.7 A_R_DAC2_F Analog Red
ABTX0M A_G_DAC2_F C2
p.7 A_G_DAC2_F Analog Green
A_B_DAC2_F C3
p.7 A_B_DAC2_F Analog Blue
ABTXCP HSYNC_DAC2_R C4
p.7 HSYNC_DAC2_R Analog HYNC
C5
ABTXCM C6 Analog GND
Analog GND#C6
ABTX5P 26
27 CASE#26
ABTX5M 28 CASE#27
29 CASE#28
ABTX4P +3.3V_BUS 30 CASE#29
CASE#30
ABTX4M DVI_CONNECTOR
3
ABTX3P Q1701 1 R1715 10K HPD_DVIAB
MMBT3904
ABTX3M
2
p.6 HPD1
R1716
10K
A A

50
102-C01301-00
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
(09) JUNIPER Display Port C & Display Port/HDMI D
AUX/DDC:
FOR 740/730, INSTALL 0R ON ASIC‐SIDE OF AC COUPLING CAPS ONLY;
D FOR JUNIPER, INSTALL 0R ON CONNECTOR SIDE OF AC COUPLING CAPS ONLY; D
U1K
+1.8V J1800
PART 11 OF 15
B1800 BLM15AG121SN1D +DPCD_18 AU18 AT17 DPC_C0P C1801 100nF_6.3V DPC_0P 1
DPC_PVDD TX2P_DPC0P 2 ML_Lane_0p
AR16 DPC_C0N C1802 100nF_6.3V DPC_0N 3 GND_0
C1803 TX2M_DPC0N ML_Lane_0n
1uF_6.3V AU16 DPC_C1P C1805 100nF_6.3V DPC_1P 4
GND AV17 TX1P_DPC1P 5 ML_Lane_1p
DPC_PVSS AV15 DPC_C1N C1806 100nF_6.3V DPC_1N 6 GND_1
TX1M_DPC1N ML_Lane_1n
AT15 DPC_C2P C1807 100nF_6.3V DPC_2P 7
TX0P_DPC2P 8 ML_Lane_2p
AR14 DPC_C2N C1808 100nF_6.3V DPC_2N 9 GND_2
+DPCD_18 AV19 TX0M_DPC2N ML_Lane_2n
DPD_PVDD AU14 DPC_C3P C1809 100nF_6.3V DPC_3P 10
Please pay attention to the grounding TXCCP_DPC3P ML_Lane_3p
11
strategies for these filter capacitors to AV13 DPC_C3N C1810 100nF_6.3V DPC_3N 12 GND_3
TXCCM_DPC3N ML_Lane_3n
maintain a close loop for current.
GND AR18 DPC_DONGLE_DET 13
DPD_PVSS R1801 1M DPC_1M 14 Pin_13
Pin_14
+1V AN20 AUX2P C1811 100nF_6.3V DPC_AUXP DPC_AUXP 15
AUX2P R1802 100K 16 AUX_CHp
B1801 BLM15AG121SN1D +DPCD_VDD10 AP13 AM20 AUX2N C1812 100nF_6.3V DPC_AUXN DPC_AUXN 17 GND_6
AT13 DPC_VDD10#1 AUX2N R1803 100K AUX_CHn
DPC_VDD10#2 T +3.3V_BUS
C1813 C1814 HPD_DPC 18 G4
4.7uF_6.3V 1uF_6.3V M AM19 DDC2CLK R1816 R1817 +3.3V_BUS +3.3V_DP Hot_Det G4 G3
DDC2CLK 20 G3 G2
D 0R 0R +5V
+3.3V_BUS
F1800
DP_PWR G2
AL19 DDC2DATA 19 G1
P DDC2DATA DDC2DATA NANOSMDC150F-2 PWR_RTN G1
AP14 DDC2CLK R1806
DPD_VDD10#1
3
AP15 C1817 1M DISPLAYPORT
DPD_VDD10#2 C Q1800 1 10K 10uF
/ +5V MMBT3904 R1807
D DETC_BUF DPC_DONGLE_DET
2
C AUX2P C
p.6 GENERICE_HPD4
DPC_AUXN DPC_AUXP
+DPCD_18 AP20 AUX2N
AP21 DPC_VDD18#1 R1808
C1819 C1820 DPC_VDD18#2 10K
4.7uF_6.3V 1uF_6.3V
AT23 DPD_C0P C1822 100nF_6.3V DPD_0P

AP22 TX5P_DPD0P
AP23 DPD_VDD18#1 AR22 DPD_C0N C1823 100nF_6.3V DPD_0N
DPD_VDD18#2 TX5M_DPD0N
AU22 DPD_C1P C1824 100nF_6.3V DPD_1P
TX4P_DPD1P
AV21 DPD_C1N C1825 100nF_6.3V DPD_1N
TX4M_DPD1N
AT21 DPD_C2P C1826 100nF_6.3V DPD_2P
150R R1800 DPCD_CALR AW18 TX3P_DPD2P
DPCD_CALR AR20 DPD_C2N C1827 100nF_6.3V DPD_2N
TX3M_DPD2N
AN17 AU20 DPD_C3P C1828 100nF_6.3V DPD_3P
AP16 DPC_VSSR#1 TXCDP_DPD3P
AP17 DPC_VSSR#2 AT19 DPD_C3N C1829 100nF_6.3V DPD_3N
AW14 DPC_VSSR#3 TXCDM_DPD3N
AW16 DPC_VSSR#4 R1831 2.2K DPD_DONGLE_DET
DPC_VSSR#5 +5V_HDMI
AN19 DPD_1M
AP18 DPD_VSSR#1 R1832 2.2K
AP19 DPD_VSSR#2 AN21 DDCCLK_AUX5P DPD_AUXP
DPD_VSSR#3 DDCCLK_AUX5P DDCCLK_AUX5P p.8 p.8 DPD_AUXP
AW20
AW22 DPD_VSSR#4 AM21 DDCDATA_AUX5N DPD_AUXN
DPD_VSSR#5 DDCDATA_AUX5N DDCDATA_AUX5N p.8 p.8 DPD_AUXN
+3.3V_BUS
HPD_DPD
JUNIPER XT A12 HF MVD SLT BIN1 TSMC FB12 +3.3V_DP
+3.3V_BUS +3.3V_DPD
+5V +3.3V_BUS
3
DETD_BUF DPD_DONGLE_DET
DDCCLK_AUX5P Q1801 1 10K
B MMBT3904 B
DPD_AUXN DPD_AUXP R1814
2
p.6 GENERICF_HPD5 Share PADs
DDCDATA_AUX5N
DNI ‐ FOR TEST ONLY R1815
10K
OPTIONAL ESD protection diodes
p.6 GPIO_14_HPD2
+5V_HDMI
DPC_3N DPC_3N DPD_3N DPD_3N MJ1801
DPC_3P DPC_3P DPD_3P DPD_3P DPD_0P DPD_0P 1 20
2 1 GND#20 21
DPC_2N DPC_2N DPD_2N DPD_2N DPD_0N DPD_0N 3 2 GND#21 22
DPC_2P DPC_2P DPD_2P DPD_2P DPD_1P DPD_1P 4 3 GND#22 23
5 4 GND#23
DPD_1N DPD_1N 6 5
DPD_2P DPD_2P 7 6
8 7
DPD_2N DPD_2N 9 8
DPC_1N DPC_1N DPD_1N DPD_1N DPD_3P DPD_3P 10 9
DPC_1P DPC_1P DPD_1P DPD_1P 11 10
DPD_3N DPD_3N 12 11
DPC_0N DPC_0N DPD_0N DPD_0N CEC1 13 12
DPC_0P DPC_0P DPD_0P DPD_0P 14 13
DPD_AUXP 15 14
DPD_AUXN 16 15
R1822 R1823 R1824 R1825 R1826 R1827 R1828 R1829 17 16
499R 499R 499R 499R 499R 499R 499R 499R 18 17
HPD_DPD 19 18
19
DPD_GND LONG_TYPE-2_HDMI
DPC_AUXN 3
DPC_AUXP
Q1802
DPD_AUXN SI2304DS
A 1 C1834 A
p.8 DVI_EN
DPD_AUXP 1uF_6.3V
2
DPC_DONGLE_DET
DPD_DONGLE_DET OVERLAP HDMI WITH DP D
50
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
(10) JUNIPER LVTMDP E&F
U1L
+1.8V
PART 12 OF 15
B1900 BLM15AG121SN1D +DPEF_18 AM37 AP35
DPE_PVDD T2X2P_DPE0P
AR35
T2X2M_DPE0N
AR37
D
GND AN38 T2X1P_DPE1P D
DPE_PVSS AU39
T2X1M_DPE1N
AW37
T2X0P_DPE2P
AU35
+DPEF_18 AL38 T2X0M_DPE2N
DPF_PVDD AP34
T2XCEP_DPE3P
AR34
T2XCEM_DPE3N
GND AM35
DPF_PVSS
+1V AL30
DDCCLK_AUX3P
L
B1901 BLM15AG121SN1D +DPEF_VDD10 AL33 AM30
AM33 DPE_VDD10#1 V DDCDATA_AUX3N
DPE_VDD10#2
T
M 5V TOLERANT
D
AK33
P
AK34 DPF_VDD10#1
DPF_VDD10#2
E
/
F
+DPEF_18 AH34
AJ34 DPE_VDD18#1
DPE_VDD18#2
AG38
AF34 T2X5P_DPF0P
C C
AG34 DPF_VDD18#1 AH37
DPF_VDD18#2 T2X5M_DPF0N
AH35
T2X4P_DPF1P
AJ36
T2X4M_DPF1N
AJ38
150R R1900 DPEF_CALR AM39 T2X3P_DPF2P
DPEF_CALR AK37
T2X3M_DPF2N
AN34 AK35
AP39 DPE_VSSR#1 T2XCFP_DPF3P
AR39 DPE_VSSR#2 AL36
AU37 DPE_VSSR#3 T2XCFM_DPF3N
DPE_VSSR#4
AF39
AH39 DPF_VSSR#1
AK39 DPF_VSSR#2 AK30
AL34 DPF_VSSR#3 DDCCLK_AUX7P
AM34 DPF_VSSR#4 AK29
DPF_VSSR#5 DDCDATA_AUX7N
B B
A A

50
102-C01301-00
8 7 6 5 4 3 2 1
5 4 3 2 1
(11) JUNIPER Power & GND
+VDDC
U1N
U1M
+MVDD PART 14 OF 15
PART 13 OF 15 B31 A3
AC7 AA15 B33 GND#91 GND#1 A37
AD11 VDDR1#1 VDDC#1 AA17 B7 GND#92 GND#2 AA16
AF7 VDDR1#2 VDDC#2 AA20 B9 GND#93 GND#3 AA18
C1200 C1227 C1229 C1268 C1241 C1245 C1271 C1269 AG10 VDDR1#3 VDDC#3 AA22 C1203 C1224 C1236 C1237 C1238 C1212 C1239 C1213 C1 GND#94 GND#4 AA2
D
100nF_6.3V 100nF_6.3V 100nF_6.3V 100nF_6.3V 100nF_6.3V 100nF_6.3V 100nF_6.3V 100nF_6.3V AJ7 VDDR1#4 VDDC#4 AA24 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V C39 GND#95 GND#5 AA21 D
AK8 VDDR1#5 VDDC#5 AA27 E35 GND#96 GND#6 AA23
AL9 VDDR1#6 VDDC#6 AB16 E5 GND#97 GND#7 AA26
G11 VDDR1#7 VDDC#7 AB18 F11 GND#98 GND#8 AA28
G14 VDDR1#8 VDDC#8 AB21 F13 GND#99 GND#9 AA6
G17 VDDR1#9 VDDC#9 AB23 C1210 C1211 C1247 C1248 C1249 C1215 C1217 C1218 F15 GND#100 GND#10 AB12
C1251 C1253 C1252 C1209 C1222 C1233 C1256 C1221 G20 VDDR1#10 VDDC#10 AB26 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V F17 GND#101 GND#11 AB15
100nF_6.3V 100nF_6.3V 100nF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V G23 VDDR1#11 VDDC#11 AB28 F19 GND#102 GND#12 AB17
G26 VDDR1#12 VDDC#12 AC17 F21 GND#103 GND#13 AB20
G29 VDDR1#13 VDDC#13 AC20 F23 GND#104 GND#14 AB22
H10 VDDR1#14 VDDC#14 AC22 F25 GND#105 GND#15 AB24
J7 VDDR1#15 VDDC#15 AC24 C1258 C1259 C1260 C1261 C1262 C1263 C1250 C1265 F27 GND#106 GND#16 AB27
J9 VDDR1#16 VDDC#16 AC27 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V F29 GND#107 GND#17 AC11
C1201 C1242 C1214 C1243 C1244 C1206 C1202 C1207 K11 VDDR1#17 VDDC#17 AD18 F31 GND#108 GND#18 AC13
1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V K13 VDDR1#18 VDDC#18 AD21 F33 GND#109 GND#19 AC16
K8 VDDR1#19 VDDC#19 AD23 F7 GND#110 GND#20 AC18
L12 VDDR1#20 VDDC#20 AD26 F9 GND#111 GND#21 AC2
L16 VDDR1#21 VDDC#21 AF17 C1264 C1220 G2 GND#112 GND#22 AC21
L21 VDDR1#22 VDDC#22 AF20 1uF_6.3V 1uF_6.3V G6 GND#113 GND#23 AC23
L23 VDDR1#23 VDDC#23 AF22 H9 GND#114 GND#24 AC26
C1208 C1231 C1254 C1255 C1230 C1228 C1257 L26 VDDR1#24 VDDC#24 AG16 J2 GND#115 GND#25 AC28
2.2UF_2.5V 2.2UF_2.5V 2.2UF_2.5V 2.2UF_2.5V 2.2UF_2.5V 2.2UF_2.5V 2.2UF_2.5V L7 VDDR1#25 VDDC#25 AG18 J27 GND#116 GND#26 AC6
M11 VDDR1#26 VDDC#26 AG21 J6 GND#117 GND#27 AD15
VDDR1#27 VDDC#27 4V, 0805 FOOTPRINT GND#118 GND#28
N11 AH22 J8 AD17
P7 VDDR1#28 VDDC#28 AH27 K14 GND#119 GND#29 AD20
VDDR1#29 P VDDC#29 GND#120 GND#30
R11 AH28 K7 AD22
U11 VDDR1#30 O VDDC#30 M26 L11 GND#121 GND#31 AD24
VDDR1#31 VDDC#31 GND#122 GND#32
C1234 C1232 U7
VDDR1#32
W VDDC#32
N24 C1273 C1276 C1277 C1282 C1284 C1287 C1283 C1235 C1240 L17
GND#123 GND#33
AD27
2.2UF_2.5V 2.2UF_2.5V Y11 N27 47uF_2.5V 47uF_2.5V 47uF_2.5V 47uF_2.5V 47uF_2.5V 47uF_2.5V 47uF_2.5V 47uF_2.5V 22uF L2 AD9
Y7 VDDR1#33 E VDDC#33 R18 L22 GND#124 GND#34 AE2
VDDR1#34 R VDDC#34 R21 L24 GND#125 GND#35 AE6
VDDC#35 R23 L6 GND#126 GND#36 AF10
VDDC#36 R26 M17 GND#127 GND#37 AF16
VDDC#37 T17 M22 GND#128 GND#38 AF18
VDDC#38 T20 M24 GND#129 GND#39 AF21
M20 VDDC#39 T22 N16 GND#130 GND#40 AG17
NC_VDDRHA VDDC#40 T24 N18 GND#131 GND#41 AG2
VDDC#41 GND#132 G GND#42
C T27 N2 AG20 C
VDDC#42 U16 N21 GND#133 N GND#43 AG22
M21 VDDC#43 U18 N23 GND#134 GND#44 AG6
MC1266 MC1267 MC1270
NC_VSSRHA VDDC#44 GND#135 D GND#45
10uF 10uF 10uF U21 N26 AG9
VDDC#45 U23 N6 GND#136 GND#46 AH21
VDDC#46 U26 R15 GND#137 GND#47 AJ10
VDDC#47 V17 R17 GND#138 GND#48 AJ11
Overlap cap pair foorprints (0805 with 0603) VDDC#48 GND#139 GND#49
V20 R2 AJ2
V12 VDDC#49 V22 R20 GND#140 GND#50 AJ28
NC_VDDRHB VDDC#50 V24 R22 GND#141 GND#51 AJ6
VDDC#51 V27 R24 GND#142 GND#52 AK11
VDDC#52 Y16 R27 GND#143 GND#53 AK31
U12 VDDC#53 Y18 R6 GND#144 GND#54 AK7
NC_VSSRHB VDDC#54 Y21 T11 GND#145 GND#55 AL11
VDDC#55 Y23 T13 GND#146 GND#56 AL14
+1.8V VDDC#56 Y26 T16 GND#147 GND#57 AL17
VDDC#57 Y28 T18 GND#148 GND#58 AL2
VDDC#58 T21 GND#149 GND#59 AL20
T23 GND#150 GND#60 AL21
T26 GND#151 GND#61 AL23
C30 C31 C32 AF26 U13 GND#152 GND#62 AL26
1uF_6.3V 1uF_6.3V 100nF_6.3V AF27 VDD_CT#1 U15 GND#153 GND#63 AL32
+VDDCI AG26 VDD_CT#2 U17 GND#154 GND#64 AL6
AG27 VDD_CT#3 U2 GND#155 GND#65 AL8
VDD_CT#4 U20 GND#156 GND#66 AM11
U22 GND#157 GND#67 AM31
AA13 U24 GND#158 GND#68 AM9
AB13 VDDCI#1 U27 GND#159 GND#69 AN11
AC12 VDDCI#2 U6 GND#160 GND#70 AN2
C1288 C1289 C1294 C1306 C1311 C1310 C1304 C1303 C1291 AC15 VDDCI#3 V11 GND#161 GND#71 AN30
1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V AD13 VDDCI#4 V13 GND#162 GND#72 AN6
AD16 VDDCI#5 V16 GND#163 GND#73 AN8
M15 VDDCI#6 V18 GND#164 GND#74 AP11
M16 VDDCI#7 +1.8V V21 GND#165 GND#75 AP7
M18 VDDCI#8 V23 GND#166 GND#76 AP9
M23 VDDCI#9 V26 GND#167 GND#77 AR5
N13 VDDCI#10 W2 GND#168 GND#78
C1299 C1300 C1302 N15 VDDCI#11 0‐1V INPUT R4020 W6 GND#169 B11
B
1uF_6.3V 1uF_6.3V 1uF_6.3V N17 VDDCI#12 Y15 GND#170 GND#80 B13 B
VDDCI#13
1.8V MAX 10K DNI GND#171 GND#81
N20 Y17 B15
N22 VDDCI#14 Y20 GND#172 GND#82 B17
R12 VDDCI#15 AL31 TS_A Y22 GND#173 GND#83 B19
R13 VDDCI#16 TS_A Y24 GND#174 GND#84 B21
R16 VDDCI#17 Y27 GND#175 GND#85 B23
T12 VDDCI#18 R4019 GND#176 GND#86 B25
0805 T15 VDDCI#19 A39 GND#87 B27
VDDCI#20 10K DNI VSS_MECH#1 GND#88
4V C1313 C1314 C1315 C1285 C1316 C1301 C1305 C1307 V15 AF28 AW1 B29
VDDCI#21 FB_VDDC FB_VDDC p.12 VSS_MECH#2 GND#89
X6S 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF Y13 AW39
VDDCI#22 VSS_MECH#3
AG28 AH29 FB_GND p.12 JUNIPER XT A12 HF MVD SLT BIN1 TSMC FB12
FB_VDDCI FB_GND
A A

50
Title Doc No.
5 4 3 2 1
8 7 6 5 4 3 2 1
(12) VDDC PHASE 1 PHASE 2

PHASE 3
Output Bulk CAPs
+12VBUS_SOURCE +12VEXT_SOURCE +12VEXT_SOURCE

+VDDC +VDDC +VDDC
***
C670 C641 C657
C674 C669 C654 820uF_2.5V 820uF_2.5V 820uF_2.5V
10UF_16V 10UF_16V 100nF *** *** ***
D
6.3 x 8 mm, TH 6.3 x 8 mm, TH 6.3 x 8 mm, TH D
C664 C665
C621 C631 C600 10UF_16V 10UF_16V
10UF_16V 10UF_16V 100nF Mirrored on PCB Minimum
1206 1206 603 +VDDC +VDDC +VDDC +VDDC +VDDC
Load
Mirrored on PCB +VDDC
Mirrored on PCB *** *** *** *** ***
C666 C667 C642 C643 C644 C680 C681
10UF_16V 10UF_16V 820uF_2.5V 820uF_2.5V 820uF_2.5V 820uF_2.5V 820uF_2.5V R696
*** *** *** *** *** 300R
C640 C663 C639 C689 C633 6.3 x 8 mm, TH 6.3 x 8 mm, TH 6.3 x 8 mm, TH 6.3 x 8 mm, TH 6.3 x 8 mm, TH 805
10UF_16V 10UF_16V 100nF 10UF_16V 10UF_16V
1206 1206 Mirrored on PCB
Mirrored on PCB Input MLCC

Mirrored on PCB
Input MLCC Output MLCC
Input MLCC
+VDDC
C634
C632 470UF_16V
C630 470UF_16V 8x 8 mm, TH C645 C646 C647 C648 C679 C659 C683 C685 C686 C687
470UF_16V 8x 8 mm, TH 10uF_X6S 10uF_X6S 10uF_X6S 10uF_X6S 10uF_X6S 10uF_X6S 10uF_X6S 10uF_X6S 10uF_X6S 10uF_X6S
2
2
8x 8 mm, TH 0805 6.3V 0805 6.3V 0805 6.3V 0805 6.3V 0805 6.3V 0805 6.3V 0805 6.3V 0805 6.3V 0805 6.3V 0805 6.3V
Q601 Q611 Q621
Input Bulk CAPs
UGATE1_CTR UGATE1_1 1 UGATE2_CTR UGATE2_11 Input Bulk CAPs UGATE3_CTR UGATE3_1 1
R601 0R NTD4909N Input Bulk CAPs R611 0R NTD4909N R621 0R NTD4909N +VDDC
3
3
+VDDC +VDDC +VDDC
MR601 MR611 MR621
10K 10K 10K C682 MC682 MC675 C675 MC673 C673 C684 C688 C693 C692
L601 L611 L612 10uF_X6S 10uF_X6S 10uF_X6S 10uF_X6S 10uF_X6S 10uF_X6S 10uF_X6S 10uF_X6S 10uF_X6S 10uF_X6S
PHASE1 1 2 PHASE2 1 2 PHASE3 1 2 TH 1108 0805 6.3V 0805 6.3V 0805 6.3V 0805 6.3V 0805 6.3V 0805 6.3V 0805 6.3V 0805 6.3V 0805 6.3V 0805 6.3V
PCMB105T-R47MS PCMB105T-R47MS PCMB105T-R47MS
R606 TO252 DPAK PKG R616 TO252 DPAK PKG R626 TO252 DPAK PKG
2.2R 2.2R 2.2R +VDDC +VDDC
805 805 805
PR604 PR607 PR614 PR617 PR624 PR627 C658 C661 C662 C649 C650 C656
C606 0R 0R C616 0R 0R C626 0R 0R 100nF 15nF 390pF 100nF 15nF 390pF
4.7nF 4.7nF 4.7nF 402 402 603 402 402 603
603 603 603
2
2
Place across Q603 Q602 Place across Q613 Q612 Place across Q623 Q622
CCSN1
CCSN2
CCSN3
CCSP1
CCSP2
CCSP3
Q603, Q604 Q613, Q614 Q623, Q624
1 1 1 1 1 1
RC snubber values NTD4906N NTD4906N RC snubber values NTD4906N NTD4906N RC snubber values NTD4906N NTD4906N
LGATE1_1
LGATE2_1
LGATE3_1
shown are for reference shown are for reference shown are for reference
3
3
only, tuning is required only, tuning is required only, tuning is required
LGATE1_CTR LGATE1_CTR LGATE2_CTR LGATE2_CTR LGATE3_CTR LGATE3_CTR

C R603 0R NR603 0R R613 0R NR613 0R R623 0R NR623 0R C
MR603 MR613 MR623
10K 10K 10K
Table 1 MODE Pin Definition Table

Phase Operation
VPM Mode Mode Pin Status Mode Pin Voltage
RDD
(V) Phase 1 Phase 2 Phase 3

3-Phase Mode 0 0 Enabled Enabled Enabled
AGND
2-Phase Mode 1 3.3 Enabled Enabled Disabled
Overlap R671
Circuitry that have to be placed close to the device: with 93.1K 1-Phase Mode Floating ~ 1.7 Enabled Disabled Disabled
R663 VSEN Monitoring Droop Temp Comp Connect AGND to PGND
RD
- current sense, R699

p.15
5VCC
+5VCC is generated internally 15.8K VDDC_FB_I

- compensation network, and this is an output with 20mA Overlap R664 RT/DROOP
IOUT/IOCP
MODE
p.17
- thermal compensation network (Droop, OCP, etc) minimum current capability with 0R Connect AGND to PGND AGND PGND
R662 RT at one point close to UR600 R658
0R
Place Rs, Rp, Rs1
AGND
RT/DROOP
Close to U601
MODE
PGND SS/VSEN Rs
NS604
SS/VSEN
VSEN
Iout
5VCC
AGND 1 2 RD
UGATE3_CTR
OPTIONAL C678 NS_VIA DROOP Temp Comp

+12VEXT_SOURCE D621 1uF_6.3V AGND AGND FBRTN
AGND
(Optional) Rs1
R629 2.2R 2 1 BOOT3 C651 C2 Rp
0805 10pF_50V NTC603 10K_1%
AGND
BAT54KFILM AGND C655

C627 100pF_50V C1 R1 NTC
1UF_16V R622 C660 AGND C652 R652
RDD
Close to U601 0R 1uF_6.3V 1nF 22.1K COMP_GND Requi
0603 UR600 Differential FB Traces
0R Type II compensation from GPU core
SS/VSEN
C622
30
29
28
27
26
25
24
23
22
21
100nF U601 R656 R654 R651 RFB1 NS600

0603 0R 1.5K 511R 402 NS_VIA R681
BOOT3
UGATE3
5VCC
TCS
MODE
IOUT/IOCP
AGND
DROOP
SS
COMP
VDDC_FB_I VDDC_FB 2 1 FB_VDDC p.11 0R

C653 C3 R653 R3 R632 603 share pad VR_HOT/EN Circuit
100pF_50V 301R 0R AGND
+12V_BUS PHASE3 31 20 FB
PHASE3 FB Type III compensation +3.3V_BUS
FB p.17 p.17 HOT_INT
Close to U601 VID_G
R672
2.2R LGATE3_CTR 32 19 FBRTN For test only UR608 0R 2 1 FB_GND p.11 Overlap +3.3V_BUS
0805 LGATE3 FBRTN UR605 100R with TR603
FBRTN p.17
3
NS601
NS_VIA 1Q_BASE_1
VCC2 33 18 CSP3 Place Sensing TQ605 Q2 Overlap
VCC2 SC3+ R624 33.2K CCSP3 Point at ASIC side. MMBT3904 with TR602
2
C697 C694 C624 1/10W 0603
B B
+12VEXT_SOURCE 1UF_16V 1UF_16V 10nF CCSN3 Overlap Q_BASE VR_HOT/EN
UGATE2_CTR 34 17 CSN3 X7R R627 0R with TQ603
UGATE2 SC3- R625 2.2K R649/R607 Share Pad Share Pad
C625 share pad with TR607 with TR606
D611 100nF_6.3V
R619 2.2R 2 1 BOOT2 35 16 CSP2 CSN1 LCSN1 VREF_R1R2R3 p.17
0805 BOOT2 SC2+ R614 33.2K CCSP2
1/10W 0603 p.16,18 VDDC_EN
BAT54KFILM R612 C614 VREF
C617 0R 10nF CCSN2
1UF_16V OPTIONAL 0603 0603 PHASE2 36 15 CSN2 X7R R617 0R Overlap UP
Close to U601 C612 100nF PAHSE2 SC2- R615 2.2K R647/R605, C698/C605.
Close to U601 C615 Table 1 VRHOT/EN Table
100nF_6.3V
LGATE2_CTR 37 14 CSP1
LGATE2 SC1+ R604 33.2K CCSP1 Phase 1 Sensing PHASE1 +VDDC
EN Q1 Q2 VR_HOT/EN IC VR_HOT GPIO
C604 1/10W 0603
+12V_BUS 10nF LCSN1 CCSN1 1 on off 0 Disabled / 1
R673 2.2R VCC1 38 13 CSN1 X7R R607 0R
0805 VCC1 CS1- R605 3.01K 0 off on 5V Enabled No Warning 0
C696 C605 CCSP1
Close to U601 1UF_16V 100nF_6.3V 0 off off 0.45V Enabled Warning 1
LGATE1_CTR 39 12 Place close to U601 ST ISEN1
LGATE1 R1
2 1 R1
R1 p.17
PHASE1 40 11 VID_G
NS_VIA PHASE1 R2
AGND
PGND NS602 AGND 45 R683 0R Phase 2 Sensing PHASE2 +3.3V_BUS +3.3V_BUS

2 1 41 PGND5 46 R2
PGND1 PGND6 R2 p.17
VR_HOT
UGATE1
C602 42 47 +3.3V_BUS
BOOT1
NS_VIA Connect AGND to PGND 100nF 43 PGND2 PGND7 48 10K

Q3
VID1
VID0
SDA
R1R2R3_GND p.17
SCL
PGND3 PGND8
2
NS603 at one point close to C696 0603 44 49 TR603
EN
RT
R3
PGND4 PGND9 R3 CCSN2 Q_BASE_1 TQ604 1

R3 p.17 33K
L6788A MMBT3906
1
RT/IREF 9
10
Set PWRON Default "DVT" ISEN2 TR602
3
R602 (See Power Management Page) Q2
3
0R DNI TR607 TR606 VR_HOT/EN
0603 C671 1 Q_BASE 10K 33K
+12VBUS_SOURCE D601 100pF_50V TQ603
R609 2.2R 2 1 BOOT1 402 R655 MMBT3904 1K
2
0805 X5R 12.4K Phase 3 Sensing PHASE3 TR604
VR_HOT/EN
BAT54KFILM Close to U601 402

SDA_VCC
SCL_VCC
C699 OPTIONAL AGND

1UF_16V AGND
Close to U601
p.16,18 VDDC_EN
UGATE1_CTR VID1 CCSP2 SM
VID1 p.17
VID0 Table 1 VRHOT/EN Table
VID0 p.17
ISEN3
EN Q1 Q3 Q2 VR_HOT/EN IC VR_HOT GPIO

+3.3V_BUS
1 on on on 0 Disabled / 0
See Power Management 2 page for DPM Overlap
CCSP3 CSP SR624/PR624, 0 off on on 1.5V Enabled No Warning 0 Overlap
CSP SR627/PR627. with R683
0 off off off 3.3V Enabled Warning 1
A p.15,16 VDDC_PWR_GOOD CCSN3 CSN A
CSN SDA_VCC R4
SDA_VCC p.17 UP SCL_VCC
- R638 to Set PWRON Default "DVT" R4.
- Analog Reference (Refer R to AGND)
SCL_VCC p.17
CASE1, CASE3 Special Case Power Up Detection RT

NOTE: This is for the IC that uses VCC2 for EXT_12V Detection. AGND AGND (For HW ver IC)
AGND
PHASE3
Table 5 MODE Pin & Phase3 Strip Detection Table

Mode VPM © 2007 Advanced Micro Devices Advanced Micro Devices Inc.
App Condition Pin Mode Phase 3 IC Behavior and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
PwrUp without 2-Ph IC enabled without detecting is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
CASE 1 EXT_12V Cable 1 Mode Open EXT_12V (VCC2) voltage. other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind Date: Tuesday, November 10, 2009 Rev
regarding this schematic and design, including, not limited to, 50
PwrUp with 2-Ph Detect EXT_12V (VCC2) any implied warranty of merchantibility or fitness for a particular
CASE 3 EXT_12V Cable 1 Mode Pull Down voltage before IC enable. purpose, and disclaims responsibility forany consequences resulting Sheet 12 of 21
from use of the information included herein.
Title Doc No.
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
(13) VDDCI +12VBUS_SOURCE
C933 C915 C916 C917 C919 C920 C921 C931

150nF_16V 10UF_16V 10UF_16V 10UF_16V 10UF_16V 10UF_16V 10UF_16V 100uF_16V
603 1206 1206 1206 1206 1206 1206 6.3x7 TH
D D
Mirrored on PCB Mirrored on PCB Mirrored on PCB
Input MLCC Input Bulk CAP
2
Q901
VDDCI_UGATE_CTR R921 0R VDDCI_UGATE 1

402 NTD4909N
3
+VDDCI
L901
VDDCI_PHASE 1 2 Sense Point
1.0uH
TO252 DPAK PKG
805 C923 C924 C929 C930 C925

C C
100nF 15nF 10uF_X6S 10uF_X6S 820uF_2.5V
402 402 0805 6.3V 0805 6.3V 6.3 x 9 mm, TH 6.3 x 9 mm, TH
2
Q902
603
VDDCI_LGATE_CTR R922 0R VDDCI_LGATE 1
603 NTD4906N Output MLCC Output Bulk CAPs DNI
3
Place across
LS MOSFET
RC snubber values shown

are for reference only,
tuning is required
B B
+12V_BUS
VDDCI_EN p.16
+VDDCI
Type III Compensation
C905 VDDCI_PHASE
1
100nF C911 R912 R909 0R R714,R709 NS905
33nF_16V10K share pad NS_VIA
U901 Sense Point
VDDCI_BOOT 1 8 C912 82pF
BOOT PHASE R913 C913 2
2
VDDCI_UGATE_CTR 7 VDDCI_COMP 0R 1.8nF_50V
UGATE COMP
3 6 VDDCI_FB R911 10K VDDCI_SV R900 0R VDDCI_FB_TRACE
GND FB RFB1 603
4
VDDCI_LGATE_CTR 5 VDDCI_VCC
LGATE VCC Reserve for
A R915 uP6101BU8-A R907 2.2R Loop Measurement CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC. A
42.2K 805 © 2007 Advanced Micro Devices Advanced Micro Devices Inc.
C903 and is provided only to entities under a non-disclosure agreement
0.22uF FB_VDDCI 1 Commerce Valley Drive East
805 VDDCI_FB p.17
+12V_BUS is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
50
purpose, and disclaims responsibility forany consequences resulting Sheet 13 of 21
Title Doc No.
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
(14) MVDDQ
D D
+MVDDQ_S
U701 C715 C716 C717 C719 C720 C721 C732

+MVDDQ_B 1 8 +PW_MVDDQ_M 10UF_16V 10UF_16V 4.7uF_16V 4.7uF_16V 10UF 10UF 6.3 x 8 mm, TH
BOOT PHASE 603 1206 1206 805 805 1206 1206 470UF_16V
+PW_MVDDQ_HGD 2 7 MVDDQ_COMP
UGATE COMP
3 6 MVDDQ_FB Mirrored on PCB Mirrored on PCB Mirrored on PCB
GND FB MVDDQ_EN p.16
R715 4 5 +MVDDQ_VCC Input MLCC Input Bulk CAPs
LGATE VCC
2
42.2K uP6101BU8-A C703 Q701
0.22uF
+PW_MVDDQ_LGD +PW_MVDDQ_HGD R721 0R +PW_MVDDQ_HGDR 1
402 NTD4909N
3
+MVDD
L701
+PW_MVDDQ_M 1 2TH 1108
1.0uH
1
NS700
C Layout guideline TO252 DPAK PKG NS_VIA C723 C724 C722 *** *** *** C
Sense Point 100nF 15nF 390pF C725 C726
402 402 603 820uF_2.5V 820uF_2.5V
Rs
2
*** *** ***
2
1-Position the controller (U703) such that LGate(pin4) is the closet to gate of 6.3 x 8 mm, TH 6.3x 8 mm, TH 6.3x 8 mm, TH
the MOSFETs. You can place the gate resistors R721 and R722 next to the gate of Q702
the MOSFETs. Make the gate drive traces(PW MVDDC LGD and PW MVDDC HGD) as short MVDDQ_FB_TRACE
and as wide as possible to reduce the trace inductance. +PW_MVDDQ_LGD R722 0R +PW_MVDDQ_LGDR1 1
Cs
2-Place the bypass capacitors for Vcc as well as Boost caps as close to the 603 NTD4906N
controller as possible. They are as follows;
Output MLCC Output Bulk CAPs
402 R700
3
Vcc bypass cap is C703, and Boost cap is C705. X7R 0R
3-Voltage amplifier compensation network. Place C714 close to the pin 7. Place 25V 603 Reserve for
the rest of the compensation network close to the pins 7 and 6. These are R710, Loop Measurement
R711, R713, C713 and R712, C711 and C712. Place Rs and Cs across QL
RC snubber values shown
are for reference only, +MVDD
tuning is required
MVDDQ_SV
C713 C727 C728

2.7nF_50V_5% 10uF_X6S 10uF_X6S
402 16V
10% X7R
R1
RFB1
R711 R713
10K 0R
402 402
1% 5%
p.17 MVDDQ_FB
Place R1 and R4 close to
PWM and routed with
separate 20mil trace to
the ASIC
B B
COMPENSATION CIRCUIT FILTERED SMPS VCC BOOT CIRCUIT
+12V_EXT
MVDDQ_COMP +12V_EXT
C711
10nF
402 10V 402 402 10V R707
X7R 10% X5R 10% 2.2R
C712
R712 56pF_50V
15K +MVDDQ_VCC
402 603 +MVDDQ_B
1% C707 X7R
MVDDQ_FB 100nF 5% C705
100nF
A +PW_MVDDQ_M A
R709 603 X7R
0R 5% 16V
share pad of R714,R709

50
Title Doc No.
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
(15) Linear Regulators

Regulators for +5V, +5V_VESA and +5V_HDMI
+12V_BUS
D LDO #1: Vin = 3.00V to 3.60V (3.3V +/- 9%) Vout = +1.8V +/- 2%; Iout = 1.6A (TBV) RMS MAX F400 D
+12V_VESAIN
PCB: 50 to 70mm sq. copper area for cooling nanoSMDC020F 1206

R400 1/4W 100mA
33R 5%
U400 +5V_VESA
AZ78L05RTR-G1
+VESA_VIN 3 1
+3.3V_BUS IN OUT
GND
C400 0603
2
R310 3.6R 1UF_16V 16V C401
1uF_6.3V
R309 3.6R
1.8V_LDO_POK
R308 3.6R VDDC_PWR_GOOD LDO1_FB
LDO1_VIN +1.8V
R307 3.6R +5V LDO1_REFIN
R306 3.6R
R305 3.6R
+1.8V
1/2W 1% 1210 TP301 TP300
1.5W dissipated in resistors
OVERLAP U300 AND MU300
+5V +1.8V
U300 R302 DNI DNI

1 8 13.0K C304 C300 C303
p.6 1.8V_LDO_POK 2 POK GND#8 7 LDO1_FB 33pF_50V 10uF 100nF_6.3V
p.12,16 VDDC_PWR_GOOD EN FB 1% R5
LDO1_VIN 3 6
4 VIN VOUT 5 LDO1_REFIN
CNTL NC 9 R301
C305 GND#9 10K R4
C 10uF C306 uPI7701U8 1% 100mA C
1uF_6.3V
DNI 1210
VOUT = Vref x (1 + R5/R4) 1/2W
5% +5V_HDMI
+HDMI_VIN
0603
16V
LDO #2: Vin = +1.32V to 1.84VMAX Vout = +1.01V +/- 2% Iout = 1.7A (TBV) RMS MAX
PCB: 50 to 70mm sq. copper area for cooling
DNI!!! +5V
+MVDD
+5V_VESA +5V_HDMI
R356 +1V
0R R353
TP350 10K R452 0R
U350 R351 DNI DNI

1 8 2.67K C354 C350 C353
p.1,6,18 1V_LDO_POK LDO2_EN 2 POK GND#8 7 LDO2_FB 33pF_50V 10uF 100nF_6.3V
EN FB 1% R5
LDO2_VIN 3 6
4 VIN VOUT 5
CNTL NC 9 DNI R350
B
C355 GND#9 10K R4 B
10uF C356 uPI7701U8 1% +5V
1uF_6.3V
VOUT = Vref x (1 + R5/R4)
R451 0R
p.12 5VCC
Memory VREF: Vin = MVDDQ Vout = 0.7xMVDDQ
+MVDD
+MEM_VREF
+5V
+MEM_VREF +MVDD
MREF_REFIN MREF_VCNTL
C363 R363
5.49K
2.37K
OPTIONAL CONNECTION TO PULL
VREFD TO MVDDQ FOR x16 DETECTION
There must be one 100nF at each VREF pin

A A
Place U360 (VIN - PIN#1) close to 10uF on MVDDQ in the middle point of memory devices

50
Title Doc No.
8 7 6 5 4 3 2 1
5 4 3 2 1
(16) Power Management - Power Gating 12V_BUS, 12V_EXT & 3V3_BUS POWER SEQUENCING

+12V_BUS
+12V_BUS
+12V_EXT R1042
12V_EXT Connector 5.11K VDDC_EN p.12,18
3
J1000 Q1008
6P_HDER OVERLAP
OPTIONAL BUZZER R1041 12_OK 1 MMBT3904
1 (client request only) 11.3K Place close
+12V_1
3
2 DNI to its CTLR
2
+12V_2 3 C1000 +3.3V_BUS 12BUS_OK 1 Q1011 C1014
+12V_3 47pF_50V +12V_BUS MMBT3904 100nF
D D
+12V_EXT 16V
2
R1050
1K
4 1206
GND_1 6 R1026
GND_2
11.3K
3
LED_EXT
5 SENSE_GND_PIN 12EXT_OK 1 Q1015
Sense MMBT3904
C1007 p.18 BUZZER_NEG
2
47pF_50V R1030
1K
+3.3V_BUS
SENSE_GND_PIN
C +12V_EXT C
+3.3V_BUS R1043
10K VDDC_EN
3
Q1012
R1029 3_OK 1 MMBT3904
2.32K Place close
3
DNI to its CTLR
2
3BUS_OK 1 C1010
Q1017 100nF
MMBT3904 16V
2
R1034
1K
POWER SEQUENCING CIRCUIT
FOR MVDD & VDDCI
(ENABLES CANNOT BE SHARED SINCE IT IS ALSO THE COMPENSATION PIN OF THE SMPS REGULATOR)
B B
+3.3V_BUS
+3.3V_BUS VDDCI_EN p.13

R1008
5.1K
3
DNI
R1031 V_EN R1024 5.1K V_ENB 1 Q1013
1K MMBT3904
2
3
C1013
R1025 VBASE_OK 1 Q1006 100nF_6.3V
p.12,15 VDDC_PWR_GOOD MMBT3904
5.1K
2
LDO 1V8 ENABLED
DIRECTLY BY VDDC_POK
Place close to its CTLR
+3.3V_BUS
MVDDQ_EN p.14
R1010
5.1K
3
M_EN R1023 5.1K M_ENB 1 Q1007

MMBT3904
3
Place close to its CTLR

2
R1011 5.1K MBASE_OK 1 Q1002 C1012

MMBT3904 100nF_6.3V
2
C1009
100nF_6.3V
A A

50
Title Doc No.
5 4 3 2 1
5 4 3 2 1
(17) Power Management 2 VDDC Setting

Analog Reference (Refer R to AGND)
Close to U601
Be careful when changing R655 value (VDDC IREF)
+12V_BUS SET DEFAULT VOLTAGE POWER-ON TABLE
p.12 R1
p.12 R2
p.12 R3
R608 12.1K
R1
C608 100pF_50V
D D
R618 12.1K
R2
p.12 VREF_R1R2R3 R1R2R3_GND p.12
C618 100pF_50V
+12VBUS_SOURCE R628 12.1K
R3
L623
(VDDCI SOURCE) C628 100pF_50V
1 2
TH
(VDDC PHASE 1 SOURCE)
Toroid For IC Source # 2: For IC Source # 1:
C690 0.47uH Assume VREF_R1R2R3 = 2.1V. Assume 100uA injection current.
100uF_16V
TH
6x7mm DAUL FOOTPRINT OVERLAP
1206
+3.3V_BUS
For Testing Only
1206
R241
p.6,18,19 GPIO_17_ThermINT p.12 FB
10K
RFB2
R242 For testing only:
p.6 GPIO_5 HOT_INT p.12 Need to be installed for
NOTE: Use ML623 with Fansink P/N 7120084000G 0R
402 VDDC>1.35V
DNI
p.12 FBRTN
+MVDDQ_S +3.3V_BUS
+12V_EXT
L624
R677 R678
VDDC DPM through GPIOs (PVID)
1 2 10K 10K
C TH (MVDD SOURCE) R644 0R C
0.47uH p.12 VID1 GPIO_20_PWRCNTL_1 p.6
C695 Toroid R645 0R
p.12 VID0 GPIO_15_PWRCNTL_0 p.6
100uF_16V
TH
6x7mm
1206
1206
AGND
DAUL FOOTPRINT OVERLAP Close to U601
+12VEXT_SOURCE
L625 VDDC I2C INTERFACE
1 2
(VDDC PHASE 2 SOURCE) p.12 SDA_VCC R643 0R
SDA p.6
0.47uH_7A R639 0R
(VDDC PHASE 3 SOURCE) p.12 SCL_VCC SCL p.6
ALL 0R RESISTORS TO BE REMOVED FOR PRODUCTION;
DAUL FOOTPRINT OVERLAP
C691
100uF_16V
IF MVDD IS 5A, MAX 1.4% DROP THROUGH R‐PAKS;
MAX CURRENT LIMIT FOR EACH RESISTOR IN THE PAK IS 1A;
B B
VDDCI Low Side Divider
+VDDC +VDDCI
MODE Pin Detection Circuit
+VDDC +VDDC
+VDDC
+3.3V_BUS
p.13 VDDCI_FB
C1216 C1219 C1225
1uF_6.3V 1uF_6.3V 1uF_6.3V
MVDDQ_FB p.14
Rb MODE
p.12 MODE
RFB2 R685
Rb1 R710 0R
9.76K +12V_BUS +12V_EXT
RFB2 402
R910 1%
24K
402
+12VBUS_SOURCE +12VEXT_SOURCE
A A

50
Title Doc No.
5 4 3 2 1
8 7 6 5 4 3 2 1
(18) Mechanical and Thermal Management 2‐WIRE FAN SPINUP CIRCUIT

PLEASE CHECK BOM FOR VALUES
Pfb FANOUT_P
For 2-WIRE FAN ONLY
+12V_BUS
C201 Fan Control (New)
1UF_16V
FANOUT_N
+1.8V U1O DVI/DVI SCREWS with top tab +12V_BUS +12V_BUS
PART 15 OF 15
AJ32 AF29 This circuit provides a minimum voltage for the fan,
C200 TSVDD DPLUS R202
independent of PWM input -> check if needed for RV740
T 2.7K
1uF_6.3V AJ33 AG29 FAN_SPINUP
TSVSS S DMINUS +12V_BUS
D D
S p.1,6,15 1V_LDO_POK
FAN_SU
+3.3V_BUS MJ200
2
F Q201 Q202 FAN_POWER FANOUT_P 1
Pfb 1 1 Nfb R204 820R FANOUT_N 2
D R200 MMBT3906 MMBT3906
O 2.61K R205
3
2
619R
AK32 TS_FDO PWM R207 33R D200 DNI
TS_FDO DNI
BAT54KFILM BU ONLY
1
3
Warning: TS_FDO is not 5V tolerant. MAX sink current 1.65mA PWM_r 1 Q203 R209
MMBT3904 1.3K Vdiff
2
Add Copper under pad 4
2
If Critical Temperature is reached this will force the fan to run at full 1 4 (at least 1cm^2)
R210 0R
speed while power is removed from GPU & rest of the board. overlap C204 C205 R211 Q205
3
100nF 1uF 1K PBSS4350Z
This is an open collector signal. Active level is hard pull down to ground. footprints for FAN_VE
D4101 and
MD4101 R212
0R
Critial Temperature Fault

PWM_b
+12V_BUS +12V_BUS +12V_EXT
+12V_BUS
CTF
To maximize fan output B200
+3.3V_BUS TEST CIRCUIT during CTF trigger.
R215 3.9R R216 26R_600mA
R214 5.1K
3
20K 1%
C 2N7002E R217 FAN_POWER C
Q207 C206 C207 22.1K
Overlap cap pair foorprints 1 1uF_6.3V 1uF_6.3V C208
3
2
1UF_16V
R218 1K PERST#_CTFIN 1 Q208 1 Q209 Place close to its CTLR 16V C209
p.1,2 PERST#_buf
2
MMBT3904 CTF_SET2 MMBT3906 1% Y5V 1uF

805 0805
VDDC_EN p.12,16
2
3
16V
3
3
R223
1 R224 5.1K 470K R225 R221 1K VDDC_ENB 1 Q210
1K MMBT3904
Q211
2
2
MMBT3904
+3.3V_BUS +3.3V_BUS +12V_BUS Header is 2mm, and
CTF_VCNTL p.19 it does not follow
DNI 2.54mm spacing as 4-pin
BUZZER_NEG p.16
CTF_VCNTL PWM Fan Specification
3
+3.3V_BUS BUZZ_ENB
CTF_GATED2 R230 1K CTF_SET3 1 Q213 R231
MMBT3904 100K
p.6 GPIO_6_TACH
DNI FAN_POWER
2
R233
5.1K
DNI
6,17,19 GPIO_17_ThermINT
3
DNI (bypass for fan Overlap MJ200 and J200

R236 2.2K CTF_TRIP 1 Q215 Q216 1 CTF_FB_CNTL R237 5.1K
p.6 GPIO_19_CTF MMBT3904 MMBT3904
with 3.3V PWM)
1%
PWM
2
R238 For 4-WIRE FAN ONLY

1K
1%
B B
CTF_VCNTL
DVI/DVI SCREWS with top tab
ASSY-SCREW200 ASSY-SCREW201
SCREW SCREW
M2_x_4mm_BLK JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT
<3rd part field> <3rd part field>
ASSY-SCREW202
SCREW
RH Juniper XT Fansink for AIB DS Circular AL Fin 2 ASSY201 SCREW, PAN HD, PHILLIPS, 4-40 X 3/16L
HEATSINK H1A H1B H1C H1D BRACKET
DUAL
7120084000G
7120574000G Juniper_XT_Fansink
7120674000G 8020050000G
MT200 MT201
7120384000G MT_Hole_0.136_in. MT_Hole_0.136_in_6VIA
STACKED DVI, HDMI, DP
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
A A

50
purpose, and disclaims responsibility forany consequences resulting Sheet 18 of 21
Title Doc No.
8 7 6 5 4 3 2 1
5 4 3 2 1
(19) Debug Circuits
D D
+3.3V_BUS
JTAG
U1A R4003
1K
PART 1 OF 15
AD28 +3.3V_BUS
TESTEN AM23
J JTAG_TRSTB AK23
T JTAG_TCK AN23
JTAG_TDI AM24
A JTAG_TDO
DNI
AL24
G JTAG_TMS
TESTEN
p.1 TESTEN
TESTEN
R4002
JTAG_TRSTB 1K
JTAG_TRSTB p.1
DNI
LM96163 FOR BACKUP THERMAL CONTROL
C C
+3.3V_BUS
p.6,17,18 GPIO_17_ThermINT
LED RED "ON" shows Fault +3.3V_BUS
D4000
Q4000 LED 1 2 LED_PWR R4023
3
MMBT3904 499R
B B
R4024 1K LED_ON 1 SML-010-L
p.18 CTF_VCNTL
2
A A

50
Title Doc No.
5 4 3 2 1
5 4 3 2 1
MEMORY CHANNEL A & B
GDDR5 8pcs 64Mx16 (1GB)
D D
External Connector
+12V_EXT
CH A/B
TMDPC AC Coupling Caps

DisplayPort
DDC2 AUX2
Connector
JTAG/I2C HPD4
Debug
POWER REGULATORS CrossFire
CrossFire DVOCLK
Interlink DVPCNTL_[0..2] Overlapped
From +12V DVPDATA[23:0] AC Coupling Caps
DVP_MVP_CNTL[1:0] TMDPD DisplayPort/
+VDDC, +VDDCI, GPIO[2:1]
GENERICC, D
HDMI
+MVDDC, +MVDDQ, FAN DDC1 AUX1 Connector
HPD5
From +12V LINEAR:
+5V_VESA, +5V_HDMI Straps
GPIO STACKED DVI-I Connector
C C
From SMPS: AC Coupling Caps

DL TMDS DVI-I &
TMDPAB w/ SI inductors
+5V BIOS ROM Slim-VGA
(as needed)
Connector
From +MVDDQ Linear: Thermal
TVDAC RGB Filters
PCIE_VDDC, DPLL_VDDC, DDC6
DPx_VDD10, SPV10, MEM_VREF Speed control DDC4
GPIO17
& temperature INTERRUPT
From +3.3V Direct: HPD1 5V_VESA
sense Temp. Sensing D+/D-
FAN
VDDR3, A2VDD
TS_FDO
Built-in PWM
From 3.3V Linear (1.8V) LVTMDPEF

PCIE_PVDD, PCIE_VDDR, VDDR4,
DPLL_PVDD, SPV18, MPV18, Dynamic Power Management
VDD1DI, VDD2DI, AVDD, AVDDQ,
DPx_PVDD, DPx_VDD18, VDD_CT, CRTDAC
TSVDD POWER DELIVERY
DDC3
HPD6
B B
Juniper
XO_IN2 100MHz
Clock
XO_IN 27MHz
XTALIN
Temperature Critical
CTF
PCI-Express
Power Sequencing
Circuit
Optional +3.3V_BUS
RH PCIE JUNIPER 1GB GDDR5
Buzzer PCI-Express Bus
+12V_BUS
DP DP [HDMI] DVI-I DVI-I FH
REV 0
A A

50
Title Doc No.
5 4 3 2 1
5 4 3 2 1
Title Schematic No. Date:

RH JUNIPER GDDR5 1GB DP+DP/HDMI+DVI /sVGA 102-C01301-00 Tuesday, November 10, 2009
NOTE: This schematic represents the PCB, it does not represent any specific SKU.
Rev
REVISION HISTORY For Stuffing options (component values, DNI’s, …) please consult the product specific BOM.
Please contact AMD representative to obtain latest BOM closest to the application desired.
50
D D
Sch PCB Date REVISION DESCRIPTION
Rev Rev
00 00A 2009/07/14 JUNIPER GDDR5 1GB - BASED ON C010; VDDC/VDDCI/MVDD SMPS CHANGES; OTHER CIRCUITS UPDATED;
p. 1 - add reset gate circuit (C159,C160,C161,C162,MU101,R109,R110,R111,R112,U101);

p. 2 - remove FB_VDDCI (NC U1.AG28);
P. 11- add C670, C657,C673,C675,C682,C684,C688,C692,C693,MC673,MC675,MC682;
01 00B 2009/09/10 p. 13- remove FB_VDDCI off-page;
p. 19- remove J4004, add TESTEN/JTAG_TRSTB off-page;
p. 8- connect AUX1P/AUX1N DDC1CLK/DDC2DATA to DDCCLK_AUX5P/DDCDATA_AUX5N

02 00C 2009/09/25
C C
B B
A A
5 4 3 2 1

Electrical Circuits Amd-Ati-Radeon-Hd5770/6770

Загружено:

Сведения о документе

Оригинальное название

Авторское право

Доступные форматы

Поделиться этим документом

Поделиться или встроить документ

Параметры публикации

Этот документ был вам полезен?

Это неприемлемый материал?

Авторское право:

Доступные форматы

Electrical Circuits Amd-Ati-Radeon-Hd5770/6770

Загружено:

Авторское право:

Доступные форматы

8 7 6 5 4 3 2 1

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

(2) JUNIPER PCIe Interface

JUNIPER XT A12 HF MVD SLT BIN1 TSMC FB12

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

(3) JUNIPER MEM Interface Ch A&B

R3611 NOT FOR PRODUCTION ‐ FOR BACKUP ONLY; R3612

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

U2000 GDDR5 +MVDD U2100 GDDR5 +MVDD U2200 GDDR5 +MVDD M2 B1

© 2007 Advanced Micro Devices Advanced Micro Devices Inc.

other than evaluation requires a Board Technology License Agreement

(5) GDDR5 x16 MEM Channel B U2400 +MVDD

+MVDD +MVDD +MVDD

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

with AMD for evaluation purposes. Further distribution or disclosure

(06) JUNIPER GPIOs Strap CF XTAL OSC

GENERICA_100M GENERICA B2 BLM15AG121SN1D

(07) JUNIPER DAC1 and DAC2

JUNIPER XT A12 HF MVD SLT BIN1 TSMC FB12

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

74VHCT125 © 2007 Advanced Micro Devices Advanced Micro Devices Inc.

(08) JUNIPER TMDP A&B dDVI-I TOP

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

(09) JUNIPER Display Port C & Display Port/HDMI D

AT23 DPD_C0P C1822 100nF_6.3V DPD_0P

(10) JUNIPER LVTMDP E&F

JUNIPER XT A12 HF MVD SLT BIN1 TSMC FB12

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

(11) JUNIPER Power & GND

JUNIPER XT A12 HF MVD SLT BIN1 TSMC FB12

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

(12) VDDC PHASE 1 PHASE 2

Output Bulk CAPs

+12VBUS_SOURCE +12VEXT_SOURCE +12VEXT_SOURCE

Mirrored on PCB Input MLCC

LGATE1_CTR LGATE1_CTR LGATE2_CTR LGATE2_CTR LGATE3_CTR LGATE3_CTR

Table 1 MODE Pin Definition Table

(V) Phase 1 Phase 2 Phase 3

- current sense, R699

+5VCC is generated internally 15.8K VDDC_FB_I

OPTIONAL C678 NS_VIA DROOP Temp Comp

BAT54KFILM AGND C655

100nF U601 R656 R654 R651 RFB1 NS600

VDDC_FB_I VDDC_FB 2 1 FB_VDDC p.11 0R

PGND NS602 AGND 45 R683 0R Phase 2 Sensing PHASE2 +3.3V_BUS +3.3V_BUS

NS_VIA Connect AGND to PGND 100nF 43 PGND2 PGND7 48 10K

PGND4 PGND9 R3 CCSN2 Q_BASE_1 TQ604 1

Set PWRON Default "DVT" ISEN2 TR602

BAT54KFILM Close to U601 402

C699 OPTIONAL AGND

EN Q1 Q3 Q2 VR_HOT/EN IC VR_HOT GPIO

CASE1, CASE3 Special Case Power Up Detection RT

Table 5 MODE Pin & Phase3 Strip Detection Table

(13) VDDCI +12VBUS_SOURCE

C933 C915 C916 C917 C919 C920 C921 C931

Mirrored on PCB Mirrored on PCB Mirrored on PCB

Input MLCC Input Bulk CAP

VDDCI_UGATE_CTR R921 0R VDDCI_UGATE 1

TO252 DPAK PKG

805 C923 C924 C929 C930 C925

RC snubber values shown

U701 C715 C716 C717 C719 C720 C721 C732

C713 C727 C728