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CHAPTER-1

Answer Key …………………………………………………………………………………………………………………..12

C

O

Solution …………………………………………………………………………………………………………………... 12-21

CHAPTER-2

Answer Key ………………………………………………………………………………………………………..……... 26

Solution ………………………………………………………………………………………………………………... 26-29

N

CHAPTER-3

Answer Key ……………………………………………………………………………………………………….………. 35

Solution …………………………………………………………………………………………………………..……. 36-42

CHAPTER-4

T

Current Mirror Circuits ……..……………………………………….. 44-49

Answer Key ………………………………………………………………………………………………………..………. 46

Solution ……………………………………………………………………………………………………………….. 46-49

CHAPTER-5

E

BJT Amplifiers ………………………………………………..………………. 51-63

Answer Key ………………………………………………………………………………………………………..………. 55

Solution ……………………………………………………………………………………………………………….. 56-63

CHAPTER-6

N

Answer Key ………………………………………………………………………………………………………..………. 66

Solution ………………………………………………………………………………………………………………... 67-69

CHAPTER-7

Answer Key ………………………………………………………………………………………………………..………. 77

Solution ………………………………………………………………………………………………………………... 77-86

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CHAPTER-8

Answer Key ………………………………………………………………………………………………………………… 93

C

O

Solution ……………………………………………………………………………………………………………….... 93-97

CHAPTER-9

Answer Key ……………………………………………………………………………………………………….………. 101

Solution ………………………………………………………………………………………………………..……. 102-105

N

CHAPTER-10

Answer Key ……………………………………………………………………………………………………….………. 107

Solution ………………………………………………………………………………………………………..…….. 108-110

CHAPTER-11

T

Differential Amplifiers …..……………………………………………. 111-114

Answer Key …………………………………………………………………………………………………….…..…..…. 112

Solution …………………………………………………………………………………………………….…….…... 112-114

CHAPTER-12

E

Answer Key ………………………………………………………………………………………………………..…….. 124

Solution ……………………………………………………………………………………………………………... 124-137

CHAPTER-13

Answer Key ………………………………………………………………………………………………………………. 140

N

Solution …………………………………………………………………………………………………….……….. 141-144

CHAPTER-14

Answer Key ………………………………………………………………………………………………………...……. 146

Solution …………………………………………………………………………………………………………….. 146-148

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Chapter

1 Diode Circuits

1. Assuming diodes are ideal in the figure the If the diode D is ideal, then the transfer

current in diode D1 is___ characteristic curve of the circuit can be

represented as

A.

A. 8 mA B. 5 mA

C. 0 mA D. - 3mA

B.

2. In the given circuit

C.

with RF = 35Ω and V = 0.6 V

______

A. 0.621 V B. 0.738 V D.

C. 0.137 V D. 0 V

3. Consider the circuit shown in the figure

4. The function of the following circuit, if the

below:

input is a sine wave, is that it

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is above +8V and below +4V.

B. Transmits that part of sine wave, which

C.

lies between +4V and +8V.

C. Transmits that part of sine wave, which

lies above –4V and below +V.

D. Transmits that part of sine wave, which

lies below +4V and above –8V.

D.

5. For the circuit shown below the input

voltage vi is as shown in figure.

shown in figure below will be behave as

a (Assume that diode is ideal).

B. clamper with sine wave clamped at +2 V

C. clamper with sine wave clamped at 0 V

Assume the RC time constant large and

D. clipper with sine wave clipped at +2 V

cut-in voltage of diode Vr = 0. The output

7. In a half wave rectifier; if on AC supply is

voltage v0 is

60 Hz, then what is the a.c ripple at

output?

A. 30 Hz B. 60 Hz

A.

C. 120 Hz D. 15 Hz

8. A half-wave rectifier having a resistance

load of 1 kΩ rectifier an a.c. voltage of 325

V peak value and the diode has a forward

resistance of 100Ω. The RMS value of

B.

output current is

A. 295.4 mA B. 94 mA

C. 147.5 mA D. 28 mA

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doubler circuit are C. 132 mA D. 154 mA

A. 2 diodes and 1 capacitor 12. Determine Vo in the following circuit.

B. 4 diodes and 1 capacitor Assume all diode to be ideal.

C. 2 diodes and 2 capacitors

D. 4 diodes and 2 capacitors

10. For an ideal diodes P1 and P2, the transfer

characteristics of the circuit will be:

A. Vin B. –Vin

C. 2Vm – Vin D. Vin – 2Vm

13.

A.

A.

B.

C. B.

D.

C.

of each diode are 0.7 V and 1 ohm

respectively, the current through 48 ohm

D.

resistor is

signals of figure are impressed on the input

terminals.

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for the input voltage. The diode in circuit

has cut-in voltage Vγ = 0

The waveform of output voltage v0 is

A.

A.

B. B.

C.

C.

D.

D.

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wave rectifier is 500Ω and the necessary

voltage is 60 sin (100 πt). Peak, average

and RMS value of current are respectively A.

(given forward resistance is 50 Ω)

A. 0.077 A, 0.0695 A, 0.109 A

B. 0.032 a, 0.043 A, 0.12 A

C. 0.109 A, 0.0695 A, 0.077 A

D. None of these

B.

17. The i-v characteristics of the diode in the

circuit given below is,

v − 0.7

A, v 0.7 V

i = 500

0 A, v 0.7 V

The current in the circuit is, C.

D.

A. 10.2 mA B. 8.3 mA

19. The minimum and maximum output

C. 5.67 mA D. 6.2 mA

voltage of the given clamping network

18. Let Vγ = 0.7 (diode forward drop), Assume

provided the Vi square wave input is given

the input varies over the range -

to the circuit is:

10 < Vi <10 V.

Plot V0 versus Vi is:

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A. 38 V and -2 V B. -42 V and 2 V 23. For the following diode circuit, what will be

C. 42 V and 2 V D. -38 V and 2 V the output waveform circuit [Given,

20. In the voltage doubler circuit shown in the Vo (ON) = 0.7 V]

figure, the switch ‘S’ is closed at t = 0.

Assuming diodes D1 and D2 to be ideal,

load resistance to be infinite and initial

capacitor voltages to be zero. The steady

state voltage across capacitor C1 and

C2 will be

A. Vc1 = 10 V, VC2 = 5 V

B. Vc1 = 10 V, VC2 = –5 V

C. Vc1 = 5 V, VC2 = 10 V

D. Vc1 = 5 V, VC2 = –10 V A.

21. In a half wave rectifier the forward value of

resistance of the diode is 30 Ω. The half

wave rectifier was connected to load

RL1 =300 Ω and the efficiency nRL1 was

measured. Now load resistance is

B.

connected to RL2 = 3 KΩ and efficiency was

nRL2. The value of nRL2 – nRL1 is ______%.

A. 4.28 B. 33.2

C. 3.28 D. 3.78

22. The input to full-wave rectifier shown

below is vi = 120 sin 2π60t V. The diode

cut-in voltage is 0.7 V. If the output C.

voltage cannot drop below 100 V, the

required value of the capacitor is ………….

μF.

D.

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24. Consider the waveform shown below: 26. The transfer characteristics for the clipper

circuit shown below. Assume the diodes

are ideal.

with a period of 20 ms. The output of the

wave is so designed that it has a maximum

value of 35 and minimum of –165 V at the

steady state, then the circuit which can

perform this function can be represented

as.

A.

A.

B.

B.

C.

C.

D. None of these

25. For the ideal diodes as shown, DC

component of output voltage Vo is

______V

D.

following circuit, for the output voltage to

be clipped the range of input voltage

should be :

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B. DC component of output is –4 V

C. Maximum output voltage is 2 V

D. Minimum output voltage is –13V

31. Consider a clipper circuit as shown in figure

A. Vi > -5V, or Vi < -7 V

below:

B. -7V < Vi < -5V

C. -14 < Vi < -10

D. Vi > -10V or Vi < -14 V

MSQs:

28. While comparing FWR {Fullwave Rectifier}

with Bridge Rectifier which of the following

quantities do not remain same? Here all Diodes are ideal, then

(Keeping input and diode conditions same) A. It input voltage is 5 V, then first Break

9 V.

32. Consider the following diode circuit having

cut-in voltage 0.7 V for both diodes, then

Tripler

B. VC1 = Vm

C. VC2 = Vm

D. VC3 = 2Vm

30. In the circuit shown, diode is ideal and

input is 3+ 9sinωt then choose the correct

option(s)?

A. ID2 = –0.787 mA

B. ID2 = 0 mA

C. Vo = 10.1 V

D. Vo = 9.53 V

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ANSWER

1. B 2. A 3. D 4. B 5. B 6. B 7. B 8. C 9. C 10. D

11. C 12. B 13. D 14. B 15. C 16. C 17. D 18. C 19. C 20. D

21. C 22.(20.6) 23. B 24. B 25. (15.11) 26. D 27. D 28. C,D 29. A,B&D 30. A,B&D

SOLUTION

As given diode are ideal, = 5 - 4.262

From the given circuit, it can be observed = 0.738 V

that D2 is OFF and D1 is ON. 3. (D)

∴ D2 = Reverse biased Case I: When Vin(t) > 0

D1 = Forward biased The diode will conduct; thus the equivalent

5 circuit can be given as,

∴ Current through D1 = = 5 mA

1K

2. (B)

If V1 = V2 = 0, both the diodes will be

forward biased &

the equivalent circuit will be

The diode will not conduct, thus the

equivalent circuit can be given as

I

VCC = IRL + V + (R + R1 )

2 F

I

5 = I 4.7 103 + 0.6 + (35 + 270)

2

5 − 0.6 R V

I= Vout = Vin = in = 0.5Vin

4700 + 152.5 R +R 2

= 9.067 × 10-4 A

Output voltage, Vout = VCC - IRL

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4. (B) 7. (B)

Vi < 4V, D1 – OFF & D2 – ON For half wave rectifier a.c. ripple at output

⇒ V0 = 4V is equal to input frequency.

For Here, input frequency = 60 Hz

4V < Vi < 8V, D1 – OFF & D2 – OFF ∴ A.C ripple = 60 Hz

⇒ V 0 = Vi 8. (C)

For The peak load current

Vi > 8V, D1 – ON & D2 – OFF 325

Im = = 0.295A

⇒ V0 = 8V (1000 + 100)

reference voltage.

2. When the diode is in upward direction

the total signal will be clamp above the

reference voltage.

In the given circuit, the diode is in upward

direction and the reference voltage is zero ∴ It requires 2 diodes & 2 capacitors

then the total signal will be clamp above ∴ Option C

the 0V. So, the output voltage is: 10. (D)

For a very small, input voltage, both

D1 and D2 diodes will be OFF because of

12V on cathode side.

6. (B)

The given circuit is,

From figure, V0 = 12 V

For diode D1 to be ON, (Vi > 12V)

Diode D2 will be OFF

and the diode is in downward direction the

total signal will be clamp below the

reference voltage.

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Hence, the transfer characteristics will be,

During negative half cycle D1-on, D2-on,

D3-off, D4-off

Vm with the polarity as shown

Now the the circuit is

Now to calculate output voltage consider

the circuit as shown below

(8 − 1.4)V 6.6

I= = = 132 mA Apply KVL in the circuit shown

(48 + 1 + 1) 50

Vo = -Vin

12. (B)

13. (D)

Given

Case (I) for Vi < 2V

Diode is ON ∴ equivalent ckt would be,

D3-on, D4-on.

∴ Vo = 2V

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Case (II) for Vi > 2V 15. (C)

Diode is OFF ∴ equivalent ckt would be CASE I:

If vi + 6 < 0 or vi < –6 diode D1 is OFF and

diode D2 is ON. So, the equivalent circuit is

∴ V o = Vi

v0 = –6V

CASE II:

If –6V < vi < 8V, then both didoes D 1 and

D2 are OFF. So, the equivalent circuit is

14. (B)

Given circuit diagram

v0 = vi

CASE III:

In this case at output side only that When vi > 8V, then diode D1 is ON and

voltage appear which is maximum in input D2 is OFF. So, the equivalent circuit is,

So

Vo = max (V1, V2, V3)

So Output voltage will be

v0 = 8V

Step 5: From the result obtained in the

above step, we sketch the output

waveform as shown below.

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i=0.66 mA

then Vo = 10 - 6.66m(10k)

Vo = 3.33 V

Diode will on

if Vi>V0+0.7

Diode will off

if Vi<V0+0.7

16. (C) so

Maximum value of supply voltage, Vsmax = If Vi < 3.33 + 0.7

60V Vi < 4.03 V, Diode will off

Forward resistance, RF = 50Ω ⇒ V0 = 3.33 V

⇒ V0 = Vi – 0.7 V

Vs max 60

Peak current, Imax = =

RL + RF 500 + 50 19. (C)

The Capacitor would provide the clamping

= 0.109 A

by Vi as it is directly connected to the

2I 2 0.109

Average current, Idc = max = source voltage.

Due to the battery, the capacitor would

= 0.0695 A

charge. However, this battery would let the

lmax 0.109

RMS value of current, Irms = = capacitor to charge up to 22 V.( During

2 2

negative cycle)

= 0.077 A During positive cycle of V i,

17. (D) (Vi + VC) = 42 = Vmax and During negative

It is given that for v>0.7 volt cycle of Vi, (-Vi + VC) = 2= Vmin in the

i = (v-0.7)/500 output waveform.

or v = 500i + 0.7 .......(i) 20. (D)

Apply KVL in the given circuit then we get, The given circuit is

-10 + 1x103 (i) + v = 0

or, v = 10-1000 i .........(ii)

From (i) and (ii) we get,

10 – 1000i = 500i + 0.7

1500 i = 9.3

i = 9.3 / 1500 = 0.0062 Step 1: We have the input waveform, vi =

i = 6.2 mA 5 sin wt. So, we draw, the waveform as

18. (C)

Let consider diode is not connected

Apply KVL from +10V to -10V

i=[10-(-10)/(10k+20k)]

i=20/30k

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Step 2 : For half part of the circuit. When 21. (C)

positive half cycle of input is applied, diode 40.5

% =

R

D1 is ON and D2 is OFF. So, capacitor 1+ f

RL

C1 will charge upto +5 Volt

40.5

VC1 = +5 Volt RL1 = = 36.81

30

1+

300

40.5 40.5

RL2 = = = 40.09

30 1.01

1+

3000

∴ % Increase = 40.09 – 36.81 = 3.28%

22. Ans.

Given the input to full-wave rectifier,

Vi = 120 sin 2π60t V

So, we have the voltage across both the

This is a clamper circuit, So, output of the

secondary transformer as

circuit is

Vs = 120 sin 2π60t V

Therefore, the maximum voltage across

the capacitor is

Vmax = (Vs)max – VD,on = 120 – 0.7 =

119.3V

Since, the input cannot drop below 100 V,

so we have

In this clamper, diode is in downward Vrip = 119.3 – 100 = 19.3V

Step 3 : Second part of the circuit is peak Thus, the capacitance is obtained as

C= = = 20.6F

2fRVrip 2(60)2.5 103 19.3

23. (B)

Case I : when, vi > 5v

⇒ Diode D1 will be ON and D2 will be OFF.

Thus, from the results obtained in the

above step, the output voltage is Vi − 5

ii = A

VC2 = –10 Volt 5 103

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Voltage across 3 kΩ resistor, 24. (B)

Vi − 5 Since, the output is reproduced in the

V3k = −3

3 103 V

5 10 negative cycle, i.e. the clamper is used to

So, diode must be short circuit for the

Peak value, Vi = 10 V

positive voltage applied at the input.

V0 = 0.6 (10) + 2 = 8 V

Now after deciding the polarity of the diode

Case II: When Vi < - 5 V

we have to make sure that the diode is

→ Diode D1 will be OFF, D2 will be ON

forward biased if the input is lower than 35

Vi + 5

i= A V.

5 103

Thus, the circuit will look like it is given in

Voltage across 3 K Ω resistor: option B figure.

Vi + 5 25. Ans.15.11V

V3k = 3 103 V

5 103 During +ve half cycle D1 ≡ ON, D2 ≡ OFF

Vo = -5 + 0.6 (Vi + 5)

6.8 6.8

Negative peak value of Vo (when Vi = -10 V0 = Vi = V

6.8 + 2.2 9 i

V);

6.8

Vo = -5 + 0.6 (-10 +5) V0 = 10 sin wt …(i)

9

Vo = -8V

During –ve peak cycle: D2 ≡ ON, D1 ≡ OFF

Case 3:

When -5 V < Vi < 5 V

Diode D1 and D2 will be OFF

⇒ V o = Vi

So, output voltage waveform will be: 6.8

VO = −Vi

6.8 + 2.2

6.8

V0 = − 10 sin wt …(ii)

9

Vo = ±7.55 π sin wt

Vm = 7.55 π

2Vm

VOaVg = = 15.11V

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26. (D) 40

i= = 1mA

For +ve clipping, diode D1 will be ON and 30 + 10

This condition continues till D1 conducts

when Vi≥ 30V

∴ For Vi ≤ 30V D1 – off, D2 – ON and Vo =

30V

So the transfer characteristics is a straight

line with zero slope for Vi ≤ 30V

Vo = -5V

When Vi > 30V

For Diode D1 to be OFF, Vi should be less

D1 is ON

than -5V,

D2 is ON

For, -7V < Vo < -5V

Equivalent circuit diagram

Both diodes D1 and D2 will be OFF

1 V

V0 = Vi = i

1+1 2 Output is same as input

Hence, output is not clipped [Vo = Vi]

Vi 28. (C, D)

i.e. −7 −5

2 Sol.:

⇒ -14 < Vi < -10 (output is not clipped) FWR Bridge Rectifier

So, for clipping input voltage should be

outside to this range FF 1.11 1.11

27. (D)

When Vi ≤ 0, D1 – off PIV 2Vm Vm

D2 — ON

Vo, avg –2Vm/π –Vm/π

Equivalent circuit diagram

29. Ans. A, B & D

Sol.: For the first Half circle D 1 is S.C.

Hence

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For the next negative Half cycle D1 is O.C. 32. Ans B, D

while D2 is S.I. Hence –VC1 – Vm + VC2 = 0 Sol.

Sol.: Vi = 3 + 9 sinωt

Maximum input voltage = 12 V

When Diode is in FB, capacitor charges

through Diode up to 12 – 4 = 8 Volt

In Steady state Vc = 8 volt

V o = Vi – V c

Vo = (3 + 9sinωt) – 7

Vo = –4 + 9sinωt Applying KCL at node 1,

DC maximum output voltage = –4 + 9 = 5 15 − 0.7 − Vo Vo

+ ID2 =

V 5k 10k

Minimum output voltage = –4 – 9 = –13 V Vo 14.3 V

ID2 = − + o ...(1)

31. Ans A, B, D 10k 5k 5k

Sol. Applying KCL at node 2,

Case 1:

15 − V2 V

For Vi < 0, then diode D1 is OFF, & diode = ID2 + 2

10k 5k

D2 is ON,

3V2

V0 = 10 – (20k)I ID2 = 1.5 10−3 − ...(2)

10k

10 − 2.5

where I = = 0.25 10−3 A Equating both equations 1 and 2, we get,

30 k

So, V2 – V0 = 0.7

So, V0 = 10 – (20k) x (0.25 mA) = 5 V

Vo V0 14.3 3V2

Therefore, diode D1 will be OFF, up to 5 V + − = 1.5 10−3 −

5k 10k 5k 10k

of input voltage Vi

Therefore, Vo = 6.91 V

Case 2:

For 5 < Vi < 10, the diode D1 is ON, and 3Vo

ID2 = − 2.86 10−3

diode D2 is ON So, 10k

= −0.787 10−3 A = −0.787 mA

So, Vo = Vi

The current through diode from anode to

Vi = 5 V cathode is negative that means the diode

Case 3: D2 is in reverse bias.

If Vi = 9 V, then diode D1 is ON, and diode So, ID2 = 0 A

D2 is ON,

So, option B is correct.

Therefore, Vo = Vi

0k

So, Vo = 9 V Also, Vo = (15 − 0.7) = 9.53 V

15k

Therefore, option A, B and C are correct. So option D is correct.

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Chapter

2 Voltage Regulators

1. A 10V regulated DC power supply has a 4. The Zener diode shown in the figure has

regulation of 0.002. Find the magnitude of the specifications Vs=15V,Vz=5.2 V and PD

variation in output voltage max = 260 mW. Assume Rz = 0, the

A. 0.02 V B. 0.2 V maximum allowable current iz and the

C. 0.002 V D. None of these minimum value of Rs for which Zener

2. A 24 V, 600 mW Zener diode can be used diode remains in constant reverse

for providing a 24 V stabilized supply to a breakdown region with no longer of failure

variable load. Assume that for proper zener are

action, a minimum of 10 mA, must flow

through the zener. If the input voltage is

32 V. What would be the value of R and

maximum load current?

Vs

A. 50mA, 196kΩ B. 50mA, 196Ω

C. 100mA, 98kΩ D. 100mA, 98Ω

assumed to require a minimum current of 2. The zener voltage Vz does not vary with

Iz(min) due to limited power dissipation

capacity.

4. In a simple zener diode regulated

circuit, amplification is not possible.

Which of these statements are correct ?

A. 80Ω B. 160Ω A. 1 and 3 B. 2 and 4

C. 90Ω D. 180Ω C. 1 and 4 D. 1, 2 and 4

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6. Consider the circuit shown in the figure 8. Calculate the regulated voltages Vo1,

below Vo2 and source current Is in the network

shown.

The zener diode has a zener breakdown

B. 2.3, 2.3V and 2.5mA

voltage of Vz = 10V and has the maximum

C. 3V, 10V and 2mA

amount of zener current Iz(max) = 20 mA.

D. 3.2V, 6.8V and 4mA

The zener diode turns on when the voltage

9. In the circuit shown below Zener voltage is

of 10V is applied over it with nearly zero

VZ = 5V and β = 100. The value of IC and

Knee current, then the value of load Q

resistance RL for proper regulation should VCEQ are (assume VBE = 0.7V)

be in the range

A. RL > 100Ω

B. 10Ω < RL < 100Ω

C. 250Ω < RL < 500Ω

D. 2500Ω < RL < 500Ω

7. A zener diode is used in the circuit as

shown below which has zener dynamic

resistance of 15 ohms. The zener knee A. 12.47 mA, 4.3V B. 12.47 mA, 5.7V

voltage is 5 V. If the input voltage has a C. 10.43 mA, 5.7V D. 10.43 mA, 4.3V

range from 10 V to 20 V then find the 10. In the following limiter circuit an input

output voltage range if R = 200 Ω voltage Vi = 10 sin(100πf) is applied.

Assume that the diode drop is 0.7 V when

it is forward biased. The Zener break down

voltage is 6.8V. The maximum and

minimum values of the output voltage

respectively are: -

A. 5.348 to 7.2 V

B. 6.04 V to -5.348 V

C. 5.348 V to 6.04 V

D. 6.04 V to 7.2 V

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A. 7.5v and 0.7v B. 0.7v and –7.5v 14. Consider the circuit shown in the figure.

C. 7.5v and –0.7v D. 1.4v and —3.25v Input voltage varies from 20 V to 30 V and

12. The three terminal linear voltage regulator the load current varies from 0 to 100 mA.

is connected to a 10 Ω load resistor as

shown in the figure: -

and at least a knee current of 10 mA flows

through diode and Calculate the power

If Vin = 10V, the power dissipation in the

rating of the zener.

transistor, (in watt) is_____________

A. 90.9 Ω and 2.2 W

(Assume (VBE)ON = 0.6V

B. 181.81 Ω and 2.2 W

12. The transistor used in the circuit shown

C. 90.9 Ω and 1.1 W

below has β of 30 and ICBO negligible. If

D. 181.81 KΩ and 1.1 W

the forward voltage drop of diode is 0.7V,

MSQs:

then the current through collector will be

15. Consider a Zener Regulator circuit as

shown in the figure below:

(i) Knee current = 5 × 10–3 A

(ii) Maximum allowed power dissipation =

13. A Zenner diode rated 10V, 32 mA can be

300 mW

considered ideal i.e Rz = 0Ω. A source

(iii) Output voltage that is to kept = 6 V

voltage of 50V with RS = 1kΩ is shown in

Then which of the following statement

the following figure. The ratio of maximum

is/are correct with respect to zener

to the minimum value of RL is._____

regulator circuit?

A. Minimum load current is 10 mA

B. Maximum load current is 55 mA

C. Zener diode is working in forward biased

condition

D. Output voltage cannot be maintained at

6V

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ANSWER

1. A 2. D 3. A 4. B 5. C 6. C 7. C 8. C 9. B 10. C

SOLUTION

1. (A) V0 = Vz = 10V

Full load voltage VFL = 10V Iz min = 25 mA

Regulation = 0.002 20 − 10

I=

VNL − VFL R

Voltage regulation =

VFL V0 V 10

But IL = = Z =

Variation in output voltage = V NL – VFL 100 100 100

= 10 × 0.002 ∴ I = Iz + I L

= 0.02 V I = 125 mA

2. (D) 10 10

R= = = 80

Vz = 24 V, I 125 10−3

Pz = 600 mW 4. (B)

Izmin = 10 mA

PD max 260 10−3

Then, maximum current through resistance iz(max ) = Iz = = = 50mA

VZ 5.2

R

By KVL,

600 10−3 32 − 24

I= = Vs = Riz max + Vz

24 R

Vs − Vz

8 24 Rmin =

Hence, R = = 320 iz max

600 10−3

Minimum current through zener diode is 10 15 − 5.2

Rmin

mA. 50 10−3

15 mA 5. (C)

3. (A) A zener diode degrades the input signal at

high frequencies due to its transition

capacitance and for simple zener diode

regulated circuit, amplification is not

possible.

So, only these two statements are correct.

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I= 15/215

6. (C) Vo= 5 + 15(15/215) = 6.046 V

The minimum value of load resistance can 8. (C)

be calculated when maximum current flows Cut in voltage of Si diode = 0.7 V

through the load. ∴ V01 = 0.7+2.3

Thus, IL(max) = Iin – Iz(min) ∴ V01 = 3v

Iz(min) = 0 knee current nearly V02 = 7 + V01

equal to zero =7+3

IL(max) = Iin ∴ V02 = 10 V

50 − 10 And

Iin = = 40mA

1k Vs − V02

Is =

10 Rs

RL (min) = 103 = 250

40

20 − 10

=

Now, for maximum value of load 5

resistance, we will calculate minimum Is = 2mA

value of current through load. 9. (B)

IL(min) = Iin – Iz(max) Using KVL equation in the input loop

IL(min) = (40 – 20) × 10–3

10

RL (max ) = 103

20

= 500 Ω

7. (C)

12 = (IC + IB) RC + 5.7

6.3 = 0.5 × 103 × IE

IE = mA = 12.6mA

0.5

Vo = Vz + I (R+rz) The current in the loop

Ic = IE = 12.47mA

is given by, + 1

Vi − Vz

I= VCE = VCC – (IB + IC) RC

R + rz

= 12 × (0.5 × 12.6)

(i) If Vi=10 V

= 5.7V

I= 5/(200+15)

VCE = 5.7V

Vo= 5 + 15(5 / 215) = 5.348 V

ICQ = 12.47mA, VCEQ = 5.7V

(ii) If Vi=20 V

10. (C)

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In positive half cycle, D2 will be off Power dissipated in the transistor

(

If 0 Vi VD + Vz

1 ) then PT = VCE × IC

PT = 4 × 0.6 = 2.4 W

V o = Vi

12. (D)

( )

If Vi VD + Vz = 0.7 + 6.8 = 7.5V

1 Zener diode is used as stabilizer.

∴ for Vi < 0

Vo = −VD = 0.7V

2

11. Ans.

Power dissipated in the transistor is

PT = VCE × IC

VB =-11.3

Using KVL equation in loop.

5 -103 (IB) – 0.7-0.7 = 0

103 (IB) = 3.6

3.6

IB = A = 3.6mA

103

IC = βIB = 30 × 3.6 = 108 mA

VC = 0 –ICRC = (–108 × 2.2)= (–237.6)V

We can analyze that the transistor is VB > VC , transistor is in saturation region

operating in active region Note, In saturation IC I

(VBE)ON = 0.6V

So collector current using KVL in outer

VB – VE = 0.6V

loop.

6.6 – VE = 0.6

0 – (–12) – (VCE)sat = ICRC

VE = 6.6 – 0.6

12 − 0.2

IC =

VE = 6V 2.2 103

At Emitter by applying KCL equation IC = 5.36mA.

IE = Iβ + IL 13. Ans. 5

VE − VB 6 − 6.6 The circuit with Zener diode regulator is

I = =

3 3

10 10 drawn below as

VE 6

and IL = = = 0.6A

RL 10

6 − 6.6 6

IE = + = −0.0006 + 0.6 = 0.6A

3 10

10

VCE = VC – VE = 10 – 6 = 4V

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When Zener diode conduct then voltage Rsmin = 90.9 ohm

across resistance RL is VZ. Power rating of zener diode means

VZ maximum power dissipation of zener diode

IL =

RL which is given by

For RL to be minimum Pz(max) = VzIz(max) ----------------------(1)

IL should be maximum. Iz(max) implies minimum current through load

IS = IL + IZ, resistance i.e., IL(min) = 0 A

When IL max the IZ will be minimum. Vin(max ) − 10V

Iz (max ) = I(max ) =

Vs − Vz 50 − 10 Rs (min)

Is = =

Rs 103

=

(30 − 10) V = 0.22A

IS = 40mA 90.9 ohm

(IL)max = IS = 40 mA Pz(max) = 10x0.22 = 2.2W

vz 10 15. Ans A, B

So (RL ) min = =

(IL ) max 40 10−3 A Zener diode is always operating in its

For RL to be maximum reverse Biased condition. As such a simple

IL should be minimum è IZ should be voltage Regulator circuit can be designed

maximum i.e IZ = 32mA using a Zener Diode to maintain a constant

40 mA = (IL)min + 32 mA DC output voltage across the load in spite

è (IL)min = 8mA the variation in the input voltage or change

vz 10 in the load current.

(RL ) max = = = 1250 ohm

(IL ) min 8 10−3 So, option C is wrong.

(RL ) max =

1250

=5

Given I2K = 5 mA

(RL ) min 250 Pd(max) = 300 mW

14. (A) VL = 6 V

I2 max = =

IL(min)=0 A, IL(max)=100 mA, Vin(min)= 20 V V2 6

= 50 mA

, Vin(max)= 30 V

Ii = IZ + IL

I = Iz + IL

9−6

Now, Ii = = 0.06 = 60 mA

50

Vin(min) − 10V

Rs(min) = So, IL min = I1 – I2 max = 60 – 50 = 10 mA

I(max )

So, option A is correct

Vin(min) − 10V IL max = Ii – Imin = 60 – 5 = 55 mA (I2 min =

=

Iz (min) + IL (max ) I2k = 5 mA)

20V − 10V So, option B is correct

=

( + 100) mA

10

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Chapter

3

BJT Biasing & Stabilization

the figure is biased using a 1 mA ideal

current source. The approximate base

current value is

A. 1 mA

B. [3.3/(3.3+0.33)] mA

C. [3.3/0.33] mA

D. [3.3(33+3.3)] mA

4. Consider the circuit shown below:

A. 0 Μa B. 10 μA

C. 100 μA D. 1000 μA

2. The stabilization factor (S), for the circuit

shown below is

silicon, then the region of operation of the

transistor is

A. forward active region

B. reverse active region

C. saturation region

D. Cut-Off region

101 5. For BJT configuration as shown β = 200

A. 505/6 B.

4

5 10 then base current will be ___ μA

C. 0 D. 1

3. In the circuit of figure, assume that the

transistor has β = 99 and VBE = 0.7 V. The

value of collector current IC of the

transistor is approximately

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If IQ = 2mA, (VCE)sat = 0.2V the value of

Vo (in V) is _____

B. 1.013 mA, 2.96 kΩ

C. 0.946 mA, 4.18 kΩ

7. In the collector to base bias circuit shown

D. 1.057 mA, 3.96 kΩ

in figure, the value of the RC for

10. The common-emitter current gain of the

VCC = 15V, VCE = 5V, IC = 5 mA,

transistor is β = 75. The voltage VBE in ON

hFE = 100 and VBE = 0.7V.

state is 0.7 V. The value of IE and RC are

(Use VBE(ON) = 0.7V, VCE(sat) = 0.2V for npn

transistor)

A. 10 kΩ B. 10.52 kΩ

B. 0.987 mA, 3.04 kΩ

C. 5.68 kΩ D. 1.98 kΩ

C. 1.13 mA, 5.98 kΩ

8. For the circuit shown in figure, all Si

D. None of the above

transistor are identical, VBE = 0.7V, β

11. Consider the circuit shown in figure below.

=125, Then the value of ICN (in mA)

Given that saturation current I = 5 × 10 –

is_____.(take N = 10)

17

Amp, VBE = 800 mV and β = 100

(Vthermal = 26 mV).

The transistor Q1 is operating in

transistor is β = 75. The voltage VBE in ON

state is 0.7 V. The value of IC and RC is

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A. Saturation region

B. Cut of region

C. Reverse active region

D. Forward active region

12. For the circuit shown below, let β = 75.

The Q-point (ICQ, VCEQ) is

A. 10 and 57 B. 20 and 67

C. 30 and 87 D. 40 and 107

15. The circuit in the fig , assume that the

transistor is in active region. It has a large

β and its base-emitter voltage is 0.7 V. The

value of IC is

A. (4.68 mA, 16.46 V)

B. (3.12 mA, 186 V)

C. (3.12 mA, 8.46 V)

D. (4.68 mA, 5.22 V)

13. For the circuit shown in figure given that

IS = 8 × 10–16 A, β = 100 and VBE = 0.8 V.

What is the operating point value?

B. 1 mA

C. 5 mA

D. 10 mA

A. IC = 1.5 mA, VCE = 1.5 V 16. For the circuit shown β = 50, VBE = 0. The

14. A silicon transistor with β = 45 and

negligible reverse saturation current is

used in the circuit shown. If VCE = 5V, base

current in micro amps and resistance R in

kΩ, respectively, are

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17. In the silicon BJT circuit shown below A. 12.47 mA, 4.3 V

assume that the emitter area of transistor B. 12.47 mA, 5.7 V

Q1 is half that of transistor Q2. C. 10.43 A, 5.7 V

D. 10.43 A, 4.3 V

20. For the circuit shown below

(assume (VBE)ON = 0.7V)

Assume transistors to be identical and VT =

A. 0.5 mA B. 2 mA

25 mV at room temperature, the output

C. 9.3 mA D. 15 mA

voltage Vo in mV is _____. (given I1 = 10

18. For the transistor shown β = 25. Find the

mA I2 = 2mA)

range of V1 Such that

MSQs:

1.0 ≤ VCE ≤ 4.5.

21. For the given power-temperature current

[VBE (ON) = 0.7V]

(power derating curve) for a BJT choose

the correct option(s)?

A. 1.86 ≤ V1 ≤ 3.96

B. Slope of the curve gives the value of

B. 2.81 ≤ V1 ≤ 4.46

thermal resistance

C. 1.43 ≤ V1 ≤ 7.96

C. The case to ambience thermal

D. 2.18 ≤ V1 ≤ 3.69

resistance between case to ambience will

19. In the circuit shown below Zener voltage is

be 2°C/W for a junction to case

VZ = 5 V and β = 100. The value of ICQ and

temperature of 1° c/w.

VCEQ are

D. To prevent Heat accumulation inside

BJT, thermal resistance should be smaller.

22. A PNP Si transistor has base width 6 μm

and it is operating at emitter current of 2.2

μA and it is operating at emitter current of

2.2 mA. If Dp = 48 cm2/sec. Then choose

the correct option(s)? (β = 100)

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kΩ current gain

B. Resistance of emitter junction = 11.6 C. Stability factor with respect to Reverse

kΩ saturation current has a value lies between

C. α cut-off frequency = 43.35 MHz 1 & (1 + β)

D. α cut-off frequency = 43.35 GHz D. Stability factor for a collector to base

23. For the below power BJT choose the bias circuit depends on collector Resistance

correct option(s) while independent on Base resistance.

25. For the following circuit as shown in figure

below:

B. Required current Rating is 4A

C. Maximum power dissipation is 24 W

1+

D. Maximum power dissipation is 18 W A. Stability factor is

I

24. Read the following options regarding the 1+ B

IC

stability factor and choose the correct

1+

one(s)? B. Stability factor is

I

1− B

A. For better stability, stability factor must IC

be small

C. If β = 99 then stability factor is 1.43

B. Stability factor is determined with

D. If β = 99 then stability factor is –1.47

respect to Reverse saturation current, Base

ANSWER

11. D 12. D 13. C 14. D 15. D 16.(-2.52) 17. B 18. A 19. B 20.(40.23)

21. C,D 22. B&C 23. A,C 24. A,B &C 25.B,,C

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SOLUTION

From the circuit, emitter current IE is 4 – IB(33k) – VBE – 3.3 k × IE = 0

IE = 1mA 4 – IB(33k) – 0.7 – (1 + β) IB × 3.3k = 0

So, the equivalent DC model is 4 − 0.7

IB =

33k + 100 3.3k

So, the collector current is

IC = βIB

3.3 99

= mA

( 3.3 0.33) 100

IC of the transistor is approximately

3.3

= mA

3.3 0.33

Therefore, the base current is obtained as 4. (C)

IE Assume transistor is in active region

IB =

+1 Apply KVL –10 + 100k IB + 0.7 = 0

1m 9.3

= = 9.9 A IB = = 9.3 10−5 Amp

100 + 1 100k

≃ 10 μA IC = IB = 9.3 10−5 100 = 9.3 10−3 A

2. (A) −10 + 4k IC + VCE = 0

1+ VCE = 10 – 4 × 103 × 9.3 × 10–3

S=

RC

1 + . VCE = —27.2

R C + RB

∵ VCE = –ve

101 101 501 50501

= = =

1K 601 601 ∴ Transistor is in saturation region.

1 + 100

501K 5. Ans.

=505/6(nearly)

3. (B)

For dc analysis, we have the circuit

VE – VB = 0.7

VB − VE

IB =

500K

−0.7

= = −1.4A

500K

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∵ Emitter junction is reverse biased 8. Ans.

So transistor is in cut-off region VE = 0, VB of all transistor is 0.7V

So IB = 0 9 − 0.7

I3K = = 2.767mA

6. Ans. -0.5 V 3K

I3k = IC + IB + IB1 + IB2 + …….IBN

= IC + IB + N.IB

(As transistor are identical,

Therefore, IB = IB1 = ……IBN, IC = IC1 = ….

= ICN)

I3k = IC + (N + 1)IB

= IC + (N + 1) IC/β

N + 1

VB = 0 V (grounded) = IC 1 +

VQ = IE = 2mA

Assume BJT is in active region. IC = I3k

+ N + 1

125

IC = IE = 2.67 10−3

1 + = 2.543mA

136

Or IC ≃ IE [for higher β]. ∴ IC = IC1 = …….. = ICN = 2.54 mA.

Using KVL equation 9. (A)

5 = (5 × 103) (2 × 10–3) + VC Given the common emitter current gain, β

5 = 10 + VC = 75

VC = –5V Base-emitter voltage, VBE = 0.7 V

VB = 0 V and VC = –5V Collector voltage, VC = 2 V

VB > VC So BJT is operating under Now, we obtain the required parameters in

saturation region not in active. Then under following steps:

saturation Step 1: For dc analysis, we redraw the

VCB + VBE + (VEC)sat = 0 given circuit as

VC = – (VEC)sat – VBE

VC = (VCE)sat – VBE

VC = 0.2 — 0.7

VC = – 0.5V

7. (D)

VCC − VCE V − VCE

RC = = CC

IB + IC 1

IC 1 +

15 − 5

RC = = 1.98K

−3 101 Step 2: The emitter current (IE) is

5 10

100 IQ = IE = 1mA

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Step 3: The collector current (IC) is given

by

75

IC = I = 1

1 + E 75 + 1

= 0.986 mA

Step 4: We obtain the collector resistance

(RC) as

Step 2: Assume the transistor in active

5−2 5−2

RC = = = 3.04k region, then determine the collector

IC 9.986

voltage (VC), emitter voltage (VE), base

10. (C)

voltage (VB). By using transistor collector

From the given circuit, we have,

current equation, we have

VEC = 6 V

VBE

(VEC)sat = 0.2 V VT

IC = Ise

Since VEC > (VEC)sat, so the transistor is

800m

operating in active region. Now, we obtain = 5 10−17

26m

the required parameters in following steps:

= 1.153 mA

To determine the emitter current (IE), we

Step 3: So, we obtain the base, collector,

apply KVL in emitter-base section as

and emitter voltages as

12 – IE × 10k – 0.7 = 0

VB = VBE = 0.8 V

VC = VCC – ICRC

= 1.13 mA

= 2 – 1.153 m × 500

The collector current (IC) is given by

= 1.424 V

Ic = I = 1.12mA VE = 0 (Emitter connected to the ground)

1+ E

Step 3: Now, we check either our

Applying the KVL in emitter-collector loop,

assumption (active region) is correct or

we obtain the collector resistance (RC) as

not. The required conditions for operating

12 – 10kIE – VEC – IC × RC + 12 = 0

region of transistor is

12 – 10k × 1.13 – 6 – 1.12 × RC + 12 = 0

VC > VB, VB > VE Active region

24 − 11.3 − 6

RC = = 5.98k VB > VC, VB > VE Saturation region

1.12

11. (D) In above steps, we have determined

Step 1: We redraw the given circuit as i.e. base to emitter is forward biased and

base to collector junction is reverse biased.

Thus, the transistor operates in the

forward active mode.

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12. (D) Reverse saturation current, IS = 8 × 10–

This is a voltage divider circuit. We obtain 16

A

the operating point in following steps: Now, we obtain the operating point values

Step 1: To determine the operating point, in following steps:

we redraw the given circuit as Step 1: we redraw the given circuit for dc

analysis as

Step 2: The modified circuit parameters Step 2: From the circuit, base current is

are IB = 10 μA

R1 = 25k, R2 = 8kΩ So the collector current is obtained as

RTh = R1 || R2 = 25k || 8k = 6.06 kΩ IC = βIB = 100 × 10μA = 1 mA

8k Step 3: Now, we determine the collector to

VTh = 24 = 5.82 V

25k + 8k emitter voltage (VCE) by applying KVL in

Step 3: Applying KVL in input loop, we collector-Emitter loop as

determine the base current (IBQ) as VCE = VCC – ICRC

VTh – IBQ × 6.06k – VBE – (β + 1)IBQ × 1k = = 2.5 – (1m)(1k) = 1.5 V

0 14. (D)

IBQ = 62.4 mA Applying KVL in the output loop

Step 4: So, the emitter and collector –VCC+ (IB +IC)RC + VCE + IERE = 0

current is –24 + IE(10K) + 5 + IE(0.27K) = 0

IEQ = (β + 1) IBQ = 4.74 mA IE = 1.85 mA

ICQ = βIBQ = 4.68 mA IE

IB = = 40.2A

Step 4: Therefore, the collector to emitter 1+

voltage (VCEQ) is obtained by applying KVL Applying KVL in the base input loop

in collector-Emitter loop as –VCC + IERC + IBR + VBE + IERE = 0

24 – ICQ × 3k – VCEQ – IE × 1k = 0 –24 + (1.85 × 10–3)(10k) + (40 × 10–6)R

VCEQ = 24 – 4.68 × 3 – 4.74 × 1 = 5.22 V + 0.7 + (1.85 × 10–3)(0.27k) = 0

13. (C) –24 + 18.5 + (40 × 10–6)R + 0.7 + 0.5 =

Given the base to emitter voltage, VBE = 0

0.8 V 24 − 19.7

R = = 107

40 10−6

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15. (D) VB 9.3

IC = = = 1mA

1 R 9.3k

Given it has large β. So, IB≅ 0A

By using voltage division principle IB = IB + IB (KCL at node A)

1 2

R1 5

VB = VCC = (15) Since (Q2)Area = 2(Q1)Area

R1 + R2 1 + 10

D Dp 2

VB = 5V Io = Aq n + ni

LnNA LpND

VBE = VB – VE = 0.7

Io∝ Area

VE = VB – 0.7 = 4.3 V

IB = 2I1

VE 4.3 2 B1

IC IE = =

RE 430V IC

1

IB = 3IB1 and IB1 =

IE = 10 mA 1

16. Ans. 1mA

IB =

700

VBE = VB – VE = 0.7

2 10−3

VB = 0.7 IB2 = 2IB1 =

700

2mA

IC2 = 2I = 715 2mA

2 700

18. (A)

For VCE = 4.5V

KVL in the outer loop

10 − 5

IC = = 1mA

5

IC

IB = = 20A

−10 − 0.7 Vi − 0.7

+ = IB = 20 10−6

150 20

VCC − VCE

Vi = −2.52V IC =

RC

IC = = 0.5 m.A

1

IC 0.5

I = = = 0.02mA.

25

IR = =

2 RB 100K

2

IR = 0.057mA

2

VB –(–10) = 0.7

IR = I + IR = 0.077mA

VB = –9.3V 1 2

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1 1 E

ground, i.e. VE = 0. So, we determine the

So V1 = (0.077)15 + 0.7

collector to emitter voltage (VCEQ) as

So V1 = 1.855V

VC = VE + VBE + VZ

For VCE = 1.0V

= 0 + 0.7 + 5 = 5.7

5 −1

IC = = 4mA Step 5: Thus, the collector to emitter

1

IC 4 voltage is

I = = = 0.16mA

25 VCE = VC – VE = 5.7 – 0 = 5.7 V

IR = = 0.057mA

2 RB As collector and base shorted so it is diode

2

connected BJT mode

IR + I + IR = 0.217mA.

1 2

I1 = I0 e BE1 t

V /V

V1 = IR .RB + VBE

1 1

I2 = I0 e BE2 t

V /V

= (0.217)15 + 0.7

= 3.96 V

VBE = VB − VE = VB − 0 = VC

So, range of V1 = 1.86 ≤ V1 ≤ 3.96 1 1 1 1 1

2 2

We obtained the operating point in

lo e BE2 T

V /V

following steps. l2

=

l1

lo e BE1 T

V /V

Step 1: We redraw the given circuit as

l2 VBE2 − VBE1

= e / VT

l1

l

VBE − VBE1 = VT / n 2

2

l1

l

V0 = VBE − VBE2 = −VTln 2

1

l1

2

Step 2: Applying KVL in collector-base- = −25 10−3 ln = 40.23mV

10

emitter, we determine the emitter current

21. (C, D)

(IEQ) as

•ׇThermal resistance

12 – 500(IC + IB) – VZ – VBE = 0

12 − 5 − 0.7

1 200 − 50

IE = = 12.6mA = = = 3C / w

500 Slope 50

Step 3: So, the collector current is given • Inverse of slope will give the value of

by thermal Resistance

IE = I = 12.47mA

+1 E

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22 (B & C) So it depends on both RB & RC.

VI 26 mV 25. Ans B, C

re = = = 11.6

IE 2.2 mA For the circuit shown,

𝑤𝛽 2 (6×10−4 )2 Applying KVL in the Base emitter loop and

Base Transit time (τ) = =

2𝐷𝐵 2×48

Let IC = current through collector

360

= n sec IB = Current through Base

98

1 98

cut-of = = 109 = 43.35

2 2 360

MHz

23. Ans. A & C

VCE =VCC – IC – ICRC = 24 – 8IC

=0

Differentiating w.r.t. (IC),

RCE = (VCC – ICRC)IC

For maximum power dissipation I I I

0 + 1 + B R C + B RB + 1 + B RE = 0

IC IC IC

PC V

= 0 → IC = CC

IC 2R C

IB R C + RE 69

24 =− =−

IRating = = 2A IC R c + RB + RE 99

26

Pmax = (VCC – ICRC)IC = (24 – 2 × 6) × 2 1+

Stability factor (S) =

I

Pmax = 24 W 1− B

IC

24. Ans. A, B & C For β = 99,

Sol.; For collector to base bias circuit 1 + 99 100 10

S= = = = 1.43

69 70 7

1 + 99

99

Therefore, option B and C are correct.

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Chapter

assume that the emitter area of transistor C. 80 µA, 1.4V D. 64 µA, 1.4 V

Q1 is half that of transistor Q2. 4. Consider the emitter follower circuit as

shown in figure. All transistors are

matched with parameters (VBE)ON = 0.7V ,

(VCE)Sat = 0.2V and VA = ∞. Neglecting

base current |Vo max| + |Vo min| is equal to

____ V

[Q2 & Q3 should always be in linear mode].

A. 0.5 Ma B. 2mA

C. 9.3 mA D. 15mA

2. For BJT current mirror as shown β-is very

large. VBE = 0.7, The emitter area of Q1 is

thrice to that of Q2. The value of I(through

Q1)______(mA)

are connected as shown in the figure.

Assuming the β of the transistors to be

very high and the forward voltage drop in

3. Find IX and VX if both transistors are diodes to be 0.7V, the value of current I

identical ? is_____

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C. 4.3mA D. 5.7mA 100, VBE = 0.7. Then the value of

6. For the devices in the circuit |Vt| = 1V Vx is_____

λ = 0, µncox = 50 µA/V2, L = 1 µm and W =

10 µ m. Find V2 and I2.

A. 4.35 V B. 4.92 V

C. 5.26 V D. 5.56 V

9. If β is very large and thermal voltage V T =

25 mV, then the value of R (in kΩ) is

A. 5V, 1.125 mA

__________

B. 2.5V, 1.125 mA

C. 2.5V, 562.5 µA

D. 5V, 562.5 µA

7. For the circuit shown below current mirror

circuit, find the current Ic2?

given that IS1 = 2IS2 = 4 × 10–16 A, β1 =

β2 = 100, and I1 = 1 mA. What is the value

of

VCC − VE − 2VBE VB voltage (in mV)?

A. IC =

2

2

R 1 +

(1 + BR )

VCC − VE − 2VBE

B. IC =

2

1

R 2 +

R (1 + B )

VCC − VE − 2VBE

C. IC =

2

1

R 1 +

(1 + BR ) 11. Choose the correct option(s) regarding

current mirror?

D. None of these

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A. For proper operation of BJT current 0.8 V, β = 100), then choose the correct

mirrors all transistors must be in saturation option(s)?

region.

B. For proper operation of BJT current

mirror, all transistors must be in active

region

C. For MOSFET current mirror, all MOSFETs

must be in linear region for proper

operation.

D. For MOSFET current mirror, all

MOSFETS must be in saturation region for A. IC10 = 0.86 mA B. IC2 = 0.86 mA

proper operation. C. I = 1.8 mA D. IC3 = 0.86 mA

12. Below figure shows a modified current

mirror circuit (other parameters are VBE =

ANSWER

SOLUTION

The given circuit is a current mirror circuit half that of transistor Q2,

li/l0=1/2

image of the input current if both the

Therefore, l0= 2 mA

transistors are identical.

2. Ans.

∵ VBE = 0.7

VB – VE = 0.7

VB = 0.7 + (–6) = –5.3V

I’ = current through 1.5K resistor

0 − ( −5.3)

I' = = 3.533mA (emitter current

1.5

through Q2)

To calculate Ii 9.3 Ii + 0.7 = 0-(-10) = 10 Emitter area of Q1 = 3 × emitter area of Q2

⇒Ii= 1Ma I = 3 × I’ = 10.6 mA

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3. (C) Since the two transistors are matches

Initially assume that 1st transistor is IB1 = IB2 = IB

saturation region. VGS is same in both Also, IC = βIB

transistors therefore, ID remains same if IB = I1/ (β+2)

both transistor are identical. Current I is the collector current for Q2.

Ix = ID= 80 μA I = βIB = (β/ β+2) × I

Vx = 3 — Ix (20 kΩ) It β is larger I = I1 = 3.6mA

= 3 – 1.6 = 1.4 V 6. (C)

By substituting Ix and VX, we can conclude V G = VD

that our assumption is true. For Q1, Q2, Q4 (transistor in saturation)

4. Ans. Assume Q3 also in saturation

For Vo to be max, Q1 need to be in 5 = VGS + VGS and ID = ID

1 2 1 2

saturation (for minimum voltage drop

VGS = VGS = 2.5V

1 2

across it)

Q3 and Q4 have the same drain current

(VCE)Q1 = 0.2V

Vo = 5–0.2 = 4.8V VGS = VGS and VGS = VGS = 2.5V

max 3 4 3 4

For Vo min = –5 + 2

V − VT

(VCE)Q2 min ……………………………… from current ID = nCox GS

L 2

mirror property.

2

(VCE)Q2 min = 0.7V 10 (2.5 − 1)

6

ID = 50 10

1

1 2

so Vo min = –5 + 0.7 = –4.3V.

So |Vo max| + |Vo min| ID = ID = 562.5A

1 2

1 3 4

5. (B)

V2 = 2.5 V I2 = 562.5 µA

7. Ans. C.

Iref = Ic1 + IBR

IER

Iref = IC +

1 (1 + BR )

The circuit in the figure shows a current IER = IB1 + IB2

2

Iref = IC +

Applying KVL, we get

1 (1 + BR )

I1 = IC1+IB1+ IB2 Iref

IC =

1 2

(1 + BR )

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Iref =

R For dc analysis, we redraw the given circuit

Vcc − VE − 2VBE as

Iref =

R

Vcc − VE − 2VBE

IC =

2

2

R 1 +

(1 + BR )

8. (A)

Emitter is connected to the ground, i.e.

For matched transistor

VE = 0, so

IB1 = IB2, IC1 = IC2

VBE1 = VBE2 = VBE

Since, the collector current in a transistor

is defined as

VBE

VT

IC = Ise

VBE1

VT

So, IC1 = I1 = Is1e

VT

2IC1 2 IC2 = I2 = Is2e

y = IC + 2IB1 = IC + = IC 1 +

1 1 1

Therefore, we get

VBE1

100

IC = y = 1.86 = 1.823mA I1 I e VT

1

+ 2 102 = s1

I2 VBE2

IC =IC2=1.823 mA Is2e VT

1

Vx =8 – 2(1.823) I1

or = 2 (IS1 = 2IS2, VBE1 = VBE2)

= 4.353 V I2

9. Ans. or I1 = 2I2

Vbe1 = Vbe2 + 5μ(R) Again, we have

R=

5 So, I1 = β1 IB1, I2= β2 IB2,

Since β1 = β2, so we obtain

I 10m

VT n C1 25m n IB

I I1

= C2 = 5 = 38k = 1 =2

5 5 I2 IB

2

Hint: IC = IS e Vbe/VT

Therefore, the base currents are obtained

⇒ Vbe = VT ln (IC/IS) as

Vbe1 = VT ln (IC1/IS) I 1 10−3

IB1 = = = 10A

Vbe2 = VT ln (IC2/IS) 1 100

I IB1

Vbe1 = Vbe2 = VT ln C1 and IB2 = = 5A

2

IC2

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Also, we obtain the base-emitter voltage I = IC1 + IB1 + IC2 + IB2 + IB3

as 1 1 IC

I = IC1 1 + + IC2 1 + + 3

I

VBE = VBE1 = VBE2 = VT ln 1

IS1 Due to mirror action

1 10−3 IC1 = IC2 = IC3

= 26 10−3 ln = 742mV

4 10−16

3

I = IC1 2 +

Applying KVL in base emitter loop, we get

VB – (IB1 + IB2)5k – VBE = 0 1.74

IC1 = = 0.86 mA

Or VB = 15 × 10–6 × 5 × 10–13 + 0.742 = 2 + 0.03

0.817 V = 817 mV IC3 (1 + )

IE3 = = IC3

11. (B & D)

12. (A, B & D) 101

IE3 = 0.86 0.86 mA

For the gives circuit 100

9.08 8.2

I= = = 1.74 mA

4.7k 4.7k

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Chapter

5 BJT Amplifiers

A. B. –gm RL

1

+1

gm

−R C

C. D. gm RL

1

+1

gm

a CE BJT amplifier is to

A. increase the mid band voltage gain of

the amplifier

−R C −RE

A. B. B. provide a stable biasing for the amplifier

RE RC

C. place the Q-point of the transistor in

R C.hfe R C .hfe

C. D. active region

R1 || R2 R1 + R 2

D. prevent saturation of the amplifier

2. An amplifier with input resistance of 15 kΩ

−VC

is driven by current source of 2μA and 5. Find the voltage gain A V = of the

Vs

source resistance is 150 kΩ, has a short

given amplifier circuit.

circuit output current of 12 mA and open

(Assume VT = 25 mV)

circuit voltage of 24V. When driving a load

of 2 kΩ load, the voltage gain in dB is

______

3. For the BJT configuration shown below

V i

find o if gm = c

Vs Vbe

A. 20 B. 75

C. 95 D. 150

6. The transistor in the circuit of figure is

biased at a dc collector current of 0.5 mA.

(Assume VT= 25 mV)

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circuit is ___ (VT = 26mV)?

A. –150 B. 150 10. In the ac equivalent circuit shown, the two

C. 100 D. –100 BJTs are biased in active region and have

7. For the following given circuit, find the identical parameters with β >> 1. The

small signal voltage gain for β = 80 & VA = open circuit small signal voltage gain is

∞ and VT = 26 mV. approximately___________

A. – 61.7 B. – 47.4

A. 1 B. -1

C. – 144 D. – 166.23

C. 0 D. 2

8. For ‘Si’ transistor circuit shown α =0.98,

11. Consider the circuit shown below. The

VBE = 0.7V, VT =25mV. Then the value of

transistor parameters are β = 120 and VA

Ri (in Ω) as shown in figure

= ∞ (Assume VBE = 0.7 V and VT = 25.9

is____________.

mV)

(Rounded upto two decimal point)

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rπ and ro are :

A. 24 mA/V, ∞, 5 kΩ

B. 24 mA, 5 kΩ, ∞

C. 48 mA/V, 10 kΩ, 18 kΩ

D. 48 mA/V, 18.4 kΩ, 10 kΩ

12. If the parameters of the transistor are β =

100 VT = 25 mV & IC = 0.5 mA 1) Large output resistance

4) No early effect

5) No miller effect

A. 1, 3 and 5 B. 1, 4 and 5

C. 2, 3 and 5 D. 1, 3, 4 and 5

15. Consider the transistor amplifier circuit

shown below. The transistor parameters

are given as β = 100, VBE = 0.7, VA = ∞.

A. 5KΩ B. 10kΩ io

Find the current gain ? (VA = 26mV)

C. 2.5kΩ D. 7.5kΩ i1

figure. If the transistors θ1 and

θ2 parameters gm1, rπ1 and gm2,

rπ2 respectively then voltage gain |Av| is

npn transistor is 1 + 0.1 cos(10000 πt)

mA. At 300 K, the rπ in the small signal

model of the transistor is

gm2r2 gm1r1

A. B.

1 + gm2r2 1 + gm2r2

gm1r2 gm1r1

C. D.

1 + gm2r2 gm2r2

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Consider the circuit shown below. The If the lowers out off frequency is 20 Hz ,

transistor parameters are β = 120 and then the value of capacitror CC is ----μF

VA = ∞. (Vthermal = 0.0259 V) A. 0.53 μf B. 0.62 μF

C. 0.78 μF D. 0.67 μF

MSQs:

=∞

18 The small signal voltage gain AV = V0/VS is

19. The transistor in the amplifiers circuit

shown in figure is biased at IC = 1mA.

(Use VT = KT/q = 26mV, β0 = 200)

mv/A

What is the required value of CE (in mF) for

D. Value of voltage gain of small signal = –

the circuit to have a lower cut off

1.88 V

frequency of 10 Hz?

22. For the below high frequency π model,

20. Consider an amplifier circuit shown in

figure below having Vthermal = 26 mV. Read all the options and choose the correct

current is 10 μA.

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A. β cut off frequency of the BJT will be 24. Consider h-parameters of shown common

10.2 Hz emitter amplifier shown as

B. Unit gain frequency of the BJT will be hie = 1500 Ω, hfe = 100, hoc = 0, hre = 0

10.2 Hz

C. β cut-off frequency of the BJT will be

1.02 kHz

D. Unity gain frequency of the BJT will be

1.02 kHz

23. For the below amplifier having hfe = 120 hi

= 2.2 kΩ.

Choose the correct option(s)? For the above configuration, which of the

following statement is/are correct?

A. Input impedance is 8.3 kΩ

B. Output impedance is 2.8 kΩ

C. At mid band frequency voltage gain is –

1.4

D. Input characteristic is shown as

163.64

B. Overall input Resistance will be (Seen

by Vi) 2.18 kΩ

C. Lower 3 dB frequency will be 6.63 Hz

D. Ro (Output Resistance) will be 3 kΩ

ANSWER

11. B 12. C 13.C 14. D 15. (0.98) 16. C 17. (5) 18. (-1.88) 19. (0.2652) 20. A

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SOLUTION

1. (A) 3. (D)

The small signal equivalent circuit of given

transistor is

Vo =—hfe ib Rc ……(i)

Vs = – Vbe (by KVL in loop 2)

Apply KVL for i/p loop

Vo −i R

Vi = (hie + (1 + hfe) RE)ib……..(2) = c L = gmRL

Vs −Vbe

Vo −hfeibR c

Ao = = 4. (A)

Vi (hie + (1 + hfe ) RE ) ib The purpose of emitter bypass capacitor in

−RC a CE BJT amplifier is to increase the mid-

A

hie

+ RE band voltage gain of the amplifier.

h

fe

5. (D)

(1 + hfe = hfe) Using DC analysis,

hie

As RE

hfe

−R C

A =

RE

2. Ans.

24

Ro of amplifier = = 2k

12mA

Vin = 2 × 10–6 (150k || 15k)

IE = 0.5 mA

= 0.02727

IB = 0

2

Vo = 24 = 12V IC = IE = 0.5 mA

2+2

12 IC 0.5mA

AV (dB) = 20 log10 gm = =

= 52.86dB VT 25mV

0.02727

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Small signal equivalent circuit So, we get the transistor parameters as

IC = IB = 0.743mA

VT 80 0.026

r = = = 2.79k

ICQ 0.743

VA

ro = =

ICQ

is

Vπ = –VS

Output voltage VC is given as

VC = –gmVπRC

⇒ –gmVπ × 7.5 K = gmVS × 7.5 × 103

VC

AV = = 20 7.5 103 10−3 = 150

VS

From the circuit, the output voltage is

6. (D)

Vo = (βIb (3.7 k || 10k))

AV = -gm(RC // RL)

Applying KVL in the input loop,

= –gm[10k // 10k]

= 5K ( gm = = )

25mV VT 25mV So, voltage gain is obtained as

= –100

Vo

AV = =− (3.71k || 10k )

7. (B) Vs 2k + 2.79k

For the given circuit, the dc model is 80 2.85k

=− = −47.4

shown in figure 4.79k

8. Ans.

0.98

Given α = 0.98 , = = = 49

1 − 0.02

VB = 0, VE = -0.7 V

−0.7 + 9

IE =

6k

=1.383mA

VT

re =

Applying KVL in emitter-base loop, IE

9 — 11k × IE — VEB — 2k × IB = 0 25

=

9 − 0.7 1.383

Or IB = = 9.29A

81 11k + 2k

=18.07Ω

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10. (B)

Since VBE (Emitter-Base Voltage) = 0.7V

AC equivalent circuit to

VBE = 0.7V

Vin = −VE = 0.7V

Vin = 0.7V

Vout −0.7

So, = = −1

I'e = -(1+β) Ib Vin 0.7

Ve reIb 11. (B)

Zi = = = r

Ie (1 + ) Ib (1 + ) e Using dc analysis

49

Zi = 18.07 = 17.71

50

Ri=6k||zi=6000||17.71

= 17.65Ω

9. Ans.

Apply DC analysis

IB = (2.7 -0.7)/(100x103) KVL equation in the input side loop

= 20 μA VBB – VBE = IBRB

IE = (1+β)IB 1.3

IB =

250k

= 2mA

IB = 5.2 µA

re= VT / IE

IC = βIB = 120 × 5.2 µA = 0.642 mA

= 26/2

IC 0.642mA

= 13 Ω gm = = = 24mA / V

VT 0.0259V

Then the gain AV = (-β/1+β) RC/re VT 120

r = = =

= -228.46 IC gm 24mA / V

=∞

A= -3

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12. (C) = gm1re2 (1)

VT

r = now,re = &=

IC gm +1

25

= 100 & r =

gm

(2 )

0.5

r = 5k r

so, =

re

Drawing AC equivalent ckt,

r = re = re

+ 1

rπ = (β + 1) re

r

re =

∴ Vin = Ii × (R1||R2||rπ) + 1

Ri = = R 1 || R2 || r

Ii r

re =

= (10kΩ || 10kΩ) || 5kΩ 1 + gmr

13. (C) gm1r2

Av =

draw the small signal equivalent model of 1 + gm2r2

It is a wide band amplifier i.e. cascade

amplifier.

It has the following properties.

Vo

1. A V = = −gmR C

Vin

Since, the above current source is short 3. Large output resistance (No early effect)

circuited, then can be remove 15. Ans.

So, equivalent circuit is For the DC equivalent circuit

10 − 0.7

IE = = 0.93mA

So, vo = – gm1vin × re2 10k

IC = α IE = 0.921 mA

Vo

Av = = −gm1re2

Vin

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IC 17. Ans.

gm = = 0.03542A / v

VT For the given circuit, first draw the dc

re = = 27.94

gm hybrid-π- parameters.

Now, draw the ac equivalent circuit. Step 1: For dc analysis, replace all the AC

sources by their internal resistance.

10k

i1 = i1

10k + 27.94

I1’ = 0.9972 i1

vbe = – 27.94 i1’ Step 2: Now, apply KVL in input loop to

= – 27.94 × 0.9972 i1 find base current (IB)

= – 27.86 i1 2 – IB(250k) – VBE = 0

io = – gmvbe

2 − 0.7

= – 0.3542 × – 27.86 i1 IB = = 5.20 A

250k

io = 0.986 i1

Step 3: For the given value of β, the

i0 collector current is given by

= 0.98

i1 IC = βIB = 120 × 5.20μA

IC 0.624m

V

rx = ( + 1) T gm = = = 24mA / V

Ie Vt 0.0259

VT 120

rx = ( + 1) r = re = = = 5kΩ

( + 1)I b gm 24m

VT 18. Ans.

rx =

Ib For ac analysis, we modify the given circuit

Where lb is d.c. current through base so as

Ib = 1mA a. All the capacitors are short circuit

VT = 25mV at room temperature b. All the dc supplies are removed.

So, rx = = 25Ω

110−3 circuit as

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Putting the value of Ib in equ (i), we get

1 1

I = + +

RE RB + rz RB + rz

1 ( + 1)

= +

Apply KVL in output loop, RE ( RB + r )

V0 = –gmVπRC

R eq =

( RB + r ) RE

By voltage divider rule in input loop,

( RB + r ) + RE ( + 1)

r

V =

r + R B

Vs ( RB + r )

+1

Substituting the value Vπ, = RE

( RB + r ) + R

V0 = −g m R c

r

Vs +1 E

r + R s

R +r

Thus, the small signal voltage gain is = RE B

+1

V0 r

AV = = − g m RC 26mV

Vs rz + RB r = re = 200

1mA

5k = 5200 = 5.2kΩ

= −(24m)(4k ) = −1.88

5k + 250k

30.2k

19. Ans.

R eq = 100

201

As given circuit consist of both dependent

= 100 || 150.25

and independent sources so find equivalent = 60.06 Ω

resistance across RE, we apply 1V source 1

f0 =

across RE by short circuit existing voltage 2 Req CE

source as

1

CE = = 0.2652mF

2 60.04 10

20. (A)

1 1 Thevenin equivalent of the given circuit,

−I x + + + ( − Ib ) = 0

RE RB + r

1 1

Ix = + − ( I b ) …………(i)

RE ( RB + rz )

−1

Ib =

RB + r

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VTh = = 1.2V

200k 2 − 0.7

RTh = 20k 180k = 18k IBQ = = 5.2 A

250k

Step 1: KVL for input loop ICQ = βIBQ = 120 × 5.2 = 0.694 mA

VTh − VBE 1.2V − 0.6v

IB = = = 6.06 A 𝑔𝑚 =

𝐼𝑆𝑄

=

0.624

= 24 𝑚𝐴/𝑉

RTh + (1 + ) RE 18 + 81k 𝑉𝑇 0.0259

𝑟𝜋 = = 𝑘𝛺

𝑔𝑚 24

I E 0.49mA

⇒ gm = = = 0.0188

VT 26mA rπ = 5 kΩ

80 VA = ∞ ⇒ rD = ∞

hie = r = = = 4.255kΩ

gm 0.0188 Small signal equivalent

as

1

fL = ..............(i)

2 R eq CC

Where Req is the equivalent resistance Vo r

= −9m(4 k)

across capacitance cc. Vi (r + RB )

To determine the value of Req, use redraw

Vo 5

the circuit as = −24 4 = −1.88

Vi (5 + 250)

22. (A & D)

IC 1 mA 1

Im = = =

VT 26 mA 26

From the equation we obtain

Im 1

Req = RB || (rϖ+(1+β) RE)

fT = =

2(c + c ) 26 2 6 10−6

(∴ rϖ = 4.25kΩ)

= 18k||(4.25k + 81×1k) 106

fT = = 1.02 kHz

312

= 14.88 kΩ

Substituting it in equ (i), we get fT f 1.02 kHz

f = = T =

1 IC 100

fL =

2R eqCC IB

1 f = 10.2 Hz

CC =

2 3.14 14.88k 20

= 0.53 μ F

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23. (A & B) Zin = [hie + (1 + hfe)RE] || (10k || 100k) =

[1.5 + (101) × 2] || (10 || 100)

= 8.35 kΩ

So, option A is correct.

Output impedance,

Z0 = RL || RC = (10 || 4)

ℎ𝑓𝑒 (6||6) 𝑘𝛺 120 × 3 10 4

𝐺𝑎𝑖𝑛 = − =− = = 2.85 k

ℎ𝑖𝑐 2.2 14

Gain = –163.64 So, option B is correct.

Ri = RB || hie = (250 || 2.2) kΩ Voltage Gain

Ri = 2.18 kΩ Vo −hfe ib (Z0 )

=+ =

1 1 Vi ib (hie + (1 + hfe )RE )

fL = =

2(R L + R L )C 2 (6 + 6) 0.5 10−3 2.85 k

= −100 = −1.4

000 1.5 + (202) k

fL = = 26.52 Hz

12

So, option C is also correct.

Ro = 6 kΩ

Input characteristics of amplifier is input

24. (A, B, C)

current Vs input voltage keeping output

The small signal equivalent model of circuit

voltage constant.

is

Input current = IB; Input voltage = VBE

Output voltage = VCE

So option D is incorrect.

So input impedance

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Chapter

JFET Biasing & Amplifiers

6 (Only ESE)

JFET depletion mode only.

A. It has large input impedance Statement (II): The input resistance of a

B. value of current through gate terminal MOSFET is several orders of magnitude

is zero greater than that of a JFET

C. JEFT is always operated in saturation A. Both Statement (I) and Statement (II)

region for amplification are individually true, and Statement

D. It is used as a wideband amplifier (II) is the correct explanation of

2. When the controlling voltage of an n- Statement (I).

channel JFET is kept at 0 V, and a voltage

B. Both Statement (I) and Statement (II)

greater than the pinch-off voltage is

are individually true but Statement (II)

applied between the drain and the source

is not the correct explanation of

terminal, the JFET:

Statement (I).

A. Gets into the cut-off region

C. Statement (I) is true but Statement

B. Has a constant output voltage

(II) is false.

C. Acts as a current source

D. Statement (I) is false but Statement

D. Acts as a variable resistor

(II) is true.

3. The main drawback of a JFET is its:

7. Which of the following symbol correctly

A. high input impedance

represents a p-channel JFET?

B. low input impedance

C. higher noise

A. B.

D. lower gain

4. Compared to BJT, the JFET has a much

higher

A. voltage gain B. Input resistance

C. supply voltage D. Current

5. The transconductance of a JFET is C. D.

computed at constant VDS by:

A. Ratio of change in Id to change of Vgs

B. Ratio of change in Vgs to change of Id

C. Product of change in Vgs to change of Id

D. Ratio of change in Vds to change of Id

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IDSS = 10mA is used in the circuit of figure. C. 6.4 D. 8.0

The parameter values are VDD = 18V. RS = 10. Determine the trans-conductance for a

2kΩ, RD = 2kΩ R1 = 450 kΩ , R2 = 90 kΩ . JFET at VGS = –2V,

Determine ID and VDS. if gm0 = 8 mS and ID = IDSS/6

A. 2.6 Ms B. 3.2 mS

C. 4 mS D. 4.8 mS

11. Determine the value of the trans-

conductance for a JFET at VGS = 0V,

If gm = 2 mS

at VGS = –4V.

Given, VP = –6V

A. 2 mS B. 4 mS

A. 4.9 mA, 1.6V B. 4.9 mA, 8V C. 6 mS D. 8 mS

C. 2.5 mA, 8V D. 2.5 mA, 1.6V 12. An n- channel JFET having pinch off

9. Determine the maximum drain current in voltage Vp = -2V, is biased such that, the

mA for the JFET in the given network, if

drain current is 2 mA and saturation

VGS = –3V and VP = –8V

current IDSS = 8 mA. The transconductance

of JFET is

A. 4 mA/V

B. -2 mA/V

C. -4 mA/V

D. 1.414 mA/V

ANSWER

1. D 2. C 3. D 4. B 5. A 6. B 7. D 8. C 9. C 10. B

11. C 12. A

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SOLUTION

1. Ans. D. 3. Ans. D.

→ FET has zero input current i.e IG = 0 JFET has relatively low gain-bandwidth

Vi product compared to conventional

now Ri = =

IG

transistors. JFET’s theoretically are ideal

So, it has large input impedance. voltage amplifiers with high input

It is used as resistance in linear region &

resistance and low output resistance. But it

used as amplifier in saturation region.

is seldom used in amplifier circuits due to

As it has small gain – bandwidth product, it

its low gain bandwidth product compared

cannot be used as wideband amplifier

to Bipolar Junction Transistors.

2. Ans. C.

4. Ans. B.

The transfer characteristics for an n-

Compare to BJT, JFET has very small input

channel JFET when the controlling voltage,

VGS = 0V is shown below. current approximately zero so it has very

large input resistance.

5. Ans. A.

Transconductance is the electrical

characteristic that relates the output

current to the input voltage. For a JFET,

the transconductance is computed as the

ratio of the change in drain current to the

It can be seen from the characteristics that

when the voltage between the drain and change is gate-to-source voltage.

gm =

VGS

pinch-off voltage (Vp),the drain current

remains essentially the same, as the It expresses the performance of a JFET.

region between the two depletion regions Larger the trans-conductance, greater the

will increase in length. gain it can deliver.

The drain current ID is fixed at the value ID 6. Ans. B.

= IDSS, where IDSS is the maximum JFET is operated only in depletion mode

draincurrent. while depletion type MOSFET can be

Hence, the JFET acts as a current source

operated in both depletion and

as shown below, for VGS = 0V, VDS > Vp

enhancement modes.

7. Ans. D.

A p-channel JFET with applied voltages is

shown below.

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VGS = 3 — 2 × 2.5 = —2V

VDS = 18 × 4 × 2.5 = 8V

Since VDS > (VGS – VP)

So, ID = 2.5 mA

VDS = 8V

9. Ans. C.

Considering input loop,

Since, IG = 0A and IS = ID,

As it can be seen that when the p-n VGS = –IDRS

junction is forward-biased, the gate current VGS 3

ID = − = = 2.5mA

RS 1.2k

IG is flowing out of the p-channel device.

Similarly, the drain current ID will also flow Since,

2

out of the device. V

ID = IDSS 1 − GS

Hence, a p-channel JFET is correctly VP

2

−3

2.5mA = IDSS 1 −

−8

25

2.5mA = IDSS

64

64

IDSS = 2.5mA = 6.4mA

25

10. Ans. B.

The drain current for a JFET is given as,

2

V

8. Ans. C. ID = IDSS 1 − GS

VP

90

VGG = 18 = 3V V ID

540 1 − GS =

VGS = VGG − IDR S VGS = 3 − 2ID V I

p DSS

V

2

ID = IDSS 1 − GS ID = 10 1 +

(3 − 2ID ) Since, the trans-conductance for a JFET is

VP 4 given as,

2

IDS = 10 1 +

(3 − 2ID ) V

gm = gm0 1 − GS

VP

4

ID

On solving we get gm = gm0

IDSS

IDS = 4.9 mA, 2.5 mA

Substituting values,

For IDS = 4.9 mA

IDSS / 6

VGS = 3 — 2 × 4.9 = —6.8V gm = 8 mS

IDSS

VDS = 18 – (4) × 4.9 = —1.6V

1

gm = 8 mS = 8mS 0.4 = 3.2mS

6

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2 mS = gm0 1 − = gm0

Trans-conductance for a JFET is given as, −6 3

gm0 = 2 3 = 6mS

V

gm = gm0 1 − GS

Vp 12. Ans. A.

2

where gm0 is the trans-conductance at VGS gm = − ID IDSS = 16 10−6

Vp

= 0V

= 4mA / V

Hence,

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Chapter

7 MOSFET Biasing

B & Amplifiers

V0

AV = ?

Vs

A. 1.231 B. 9.679

C. 1.034 D. 0.517

kn = 0.4 mA / V2 , Vt = 1V and λ = 0

L

A. V1 > V2

B. V1 < V2

C. V1 = V2

3. Find voltage gain of the circuit

Vin operate in saturation mode. Ignoring

shown, if gm = 2 × 10–3 S and rds = 30 kΩ. channel length modulation, the output

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The parameter of MOSFET follows Vt =

0.6V

The parameter of NMOS is given

kn = 60A / V2 ,

W 220

= ,

L 6

VTN = +1V For the value of drain current ID = 0.8 mA

and a transconductance gm = 10 ms, the

value, of resistor RD is …. kΩ (rounded up

to three decimal place)

9. Consider the amplifier circuit shown in

figure below:

So the value of RD is in kΩ is ……...

(rounded up to two decimal value) If effect of channel length modulation is

7. Consider a circuit shown in figure, If IREF = negligible, then input resistance R in of

2mA, VDD = 3V, Vth, = 0.4V, Kn' = 400 equivalent circuit of amplifier?

micro Ampere/volt and R = 1kΩ

2

A. gm

1

B.

gm

1

C. (RL RD )

gm

1

D. R si

gm

To generate, output current. I0 = 10mA,

nCox W

ratio of (W/L)2 is ………. (rounded up to two = 0.5 mA/V2 , VT = 2V and λ = 0.

2L

decimal value)

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to______

and kn = 2mA / V2 ( = 0)

L

Kn = 0.25mA / V2 , VA = 50V

L A. V1 = 5.56, V2 = 1.55

B. V1 = 2.44, V2 = 1.55

C. V1 = 2.44, V2 = –2.56

D. V1 = 5.56, V2 = –2.56

14. The NMOS and PMOS transistor are

matched with

kn = kp = 1mA / V2 ; Vtn = −Vtp = 1V ,

L L

A. 1.5V B. 0.34 V Assume λ = 0 for both devices.

C. 4.3 V D. 4.4 V Calculate the output voltage Vo (in Volt) for

Vo

AV = ?

VS

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Transistor parameters are given as:

tenth (1/10) of ID (Drain current). For the

λ = 0, Vth = 0.4V

value of Drain current ID = 0.5mA, the

µncox = 200 µA/V2.

value of resistors R1 and R2 are

RD = 1.4 kΩ to maintain the M1 in

respectively?

saturation.

A. 5.32k,10.65k

If the voltage gain AV = 5, then parameter

W

B. 1.068k,14.932k

L is

C. 10.68k,3.32k

A. 63.80 B. 31.90 D. 3.32k,10.68k

C. 22.56 D. 15.95 18. Consider the common source circuit shown

16. Which one of the following statements below.

is/are true with regards to channel Length

modulation in a MOSFET device.

i) It is similar to base width modulation

in BJTS.

ii) The Pinch-off point relocates with

respect to applied drain voltage

iii) Drain voltage influences the current-

voltage characteristics of a MOSFET in

If the Transistor parameter are given as λ

saturation.

= 0, VTH = 0.6V, μn CoX = 120 μA/V2. If

A. only I

resistance RD= 800 Ω and voltage gain.

B. only ii

AV = 8.0, than parameter. (W/L) is

C. only (i) and (ii)

A. 410.8 B. 520.8

D. only (i), (ii) and (iii)

C. 350.8 D. 702.2

17. In the circuit shown below, the MOSFET

19. Consider the circuit shown in figure below.

parameters are as follows:

If the Lower corner Frequency due to

VTN = 0.4V

coupling capacitor CC is fL = 25 HZ, then

μnCox = 200μA/V2

the value of coupling capacitor CC is ____

W

= 278

L

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μF (Answer should be correct up to three 22. A transistor amplifier is fed with a signal

decimal value). source having an open circuit voltage

Vsig of 10 mv and an internal resistance

Rsig of 100 kΩ. The input voltage Vin and

the output voltage V0 are measured both

without and with load resistance RL = 10

kΩ connected to amplifier output. The

measured results are as follows:

shown in figure is _____ kΩ. Assume VTN =

0.5V, Kn = 2mA/V2 λ = 0

21. Consider the circuit shown in the figure then the value of output resistance R0 of

below: the amplifier is ____ kΩ (rounded up to

two decimal value)

23. For the circuit shown below transistor

parameter are VT = 1V Kn = 0.75

mA/V and λ =0, If The transistor is in

2

saturation

The DC biasing of the circuit is such that

the circuit is always in saturation region for

all values of small signal input source Ii.

The frequency of input source Ii is such

that all the coupling capacitors acts as

short circuit. If the value of output

resistance RL and the drain resistance (RD)

is equal; then the value of current gain.

I0

Ai = is equal to:-

Ii

The small signal voltage gain of the

A. 4 B. 2

MOSFET amplifier is |Av|_______.

C. 0.5 D. 0.25

(rounded up to two decimal value)

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24. In the circuit shown, transistors are 27. For the circuit shown. Choose the correct

characterized by |Vt| = 2V, K’W/L = option(s) if IDSS = 6 mA and Vp = –4 Volt?

1mA/V , and λ = 0. If both of the

2

value of V2 is ………………

A. ID = 2.34 mA

B. ID = 3.75 mA

A. 6V B. 2V C. VDS = 7.98 V

C. 4V D. 5V D. VDS = 3.75 V

25. In the circuit shown, below, the transistor 28. For the given MOSFET

parameter are as follows?

ID = 0.5 mA,

Threshold Voltage VTN = 1V

VD = 0.6 V

Conduction parameter Kn /2= 0.4 mA/V

The NMOS transistor have

VY = 0.7 V, μncox = 120 μA/V2

w = 33 μm

L = 1.1 μm

(Neglect the channel length modulation)

A. 6.40V B. 5.89 Volt

C. 3.20V D. 2.40 Volt

26. Consider a n-channel MOSFET with W =

15μm L = 2μm, and Cox = 69 nF/cm2,

Assume that in the non-saturation region

with VDS = 0.1V, the drain current is 35 μA

for a gate-to-source voltage of 1.5V, and

75μA for a gate to source voltage of 2.5V Choose the correct option(s) regarding the

compute the threshold voltage of the NMOSFET parameters?

MOSFET form the given data. A. VGS = 1.22 V

(Use small-VDS approximation in the drain B. RS = 3.65 kΩ

current equation). C. RD = 4.8 kΩ

A.0.3V B. 0.1V

D. Circuit works in triode region.

C. 0.935V D. 0.625V

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ANSWER

11. B 12.-8.01 13. C 14.B 15. B 16. D 17. D 18. B 19. 0.424 20. 0.5

21. D 22. 1.43 23. 6.12 24. B 25. B 26. D 27. A,C 28. A,C

SOLUTION

1. Ans. – 8.01 VO

Ro = = rO rs

gm = 1mA/V, vi

ro = 50k = 100k 500

Draw the equivalent small signal circuit for

R o = 0.498K

the given amplifier

3. Ans. D.

Vo V V − Vin V

+ o + o

1.2k 1k 1M 30k

( )

− 0.002 Vgs + o = 0

300k || 60k

vgs = v AC equivalent circuit

300k || 60k + 2k in

= 0.9615 vin

vo = – gmvgs × 10k || 50k

= – 1mA × 0.9616 × [10k || 50k]

= – 8.01

2. Ans. C.

gm = 2ms

ro = 100k

1 1

rs = = = 500

gm 2 ms

Vo V V − Vin V

Draw small signal equivalent circuit for + o + o − 0.002 Vin − Vo + o = 0

1.2k 1k 1M 30 k

finding ro 1 1 1 1

Vo + + + 0.002 +

1.2k 1k 1M 30k

1

= Vin + 0.002

1M

⇒ Vo[0.003867] = Vin[0.002001]

Vo 0.002001

Voltage gain = = = 0.517

Vin 0.003867

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For figure (a) → VGS = VG – VS = 0 – V1 M3 and M4 in saturation region

= –V1

( V − VT )

2

ID = Kn GS

L 2

2

−V − 1

10A = 0.4 10−3 1

2

⇒ V1 = –1.22V

For fig (b)

VGS = VG – VS = 0 – V2 = –V2 ID3 = ID4

K(8–V0–Vt)2 = K(V1–Vt)2

( VGS − Vt )

2

L 2

V0 = 8–3.5

2

−V2 − 1

100 A = 0.4 10−3 V0 = 4.5 Volt.

2

6.

V2 = –1.7V

By Voltage division Rule.

So, V1 > V2

18 22M

And max (V1, V2) = – 1.22V VG =

22M + 22M

5.

VG = 9V

In given circuit, all the MOSFET are

And

identical.

VGS = VG – ID RS

VDD

VGS = VG –

3

VGS = 9 – 6 = 3V

And we know that if VDS ≥ VGS – Vt MOSFET

is in saturation region.

I2 = 1.5mA. 1 W

( V − Vt )

2

ID = k

V1 = 8 – 3KΩ × I2 2 n L GS

ID = 60 (3 − 1) A

V1=3.5v 2 6

ID = 4.4 mA

And. VD = VS = ID RS = ID RD

6 = 4.4 mA. RS

6

RS = 103

4.4

R S = RD = 1.36k

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7. 8.

The drain current of the two transistors can For dc analysis, we redraw the circuit as,

be expressed as

I0 (W / L)2

=

IREF (W / L)1

(W / L)2 = 5(W / L)1

MOSFET. For the MOSFET we have

IG = 0

So, VD = VG

VDS > VGS – VTh.

i.e. the MOSFET is operating in saturation.

V1 = VDD – IREF × RD So the train current, and transconductance

gm = 2Kn. (VGS – Vt)2

V1 = 1V

ID V − Vt

And V1 = VG. = GS

gm 2

VDS > VGS – Vt, transistor is in saturation 0.8 mA VGS − 0.6

=

10 ms 2

region.

0.16 = VGS − 0.6VGS = 0.76

Saturation Current.

Ans VG = VD.

W

ID = K1n ( VGS − Vt )

2

At the drain terminal we have.

L 1

2.5 − VD

A

W ID =

ID = 400 2 ( VGS − Vt )

2

RD

V L 1

2.5 − 0.76

W RD =

2mA = 400 (0.6)2 10−6 0.8mA

L 1

RD = 2.175k

W

L = 13.88 9. B.

1

By drawing the small signal equivalent

W W

And = 5 = 69.44 circuit by de activating all DC supplies, we

L

2 L 1

get

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V0 = –gmVgsRD

From figure, V0 = –(gmRD)Vin = –[1 × 10–3 × 10 × 103]

−Vgs × 3 sin ωt × 10–3

Rin = and Ii = –gmVgs

Ii V0 = –30 sinωt mV

−Vgs 1 11. B.

Rin = =

−gmVgs gm

10. D.

First applying the D.C. analysis, we have

No DC gate current

IG = 0

VGS = VDS (saturation region)

W ( VGS − Vt )

2

ID = kn L

Now, assuming MOS to be in saturation 2

2

region 15 − 10ID − 1.5

ID = 0.25

nCox W 2

( VGS − VT ) = 0.5 10−3(3 − 2)2

2

ID =

2L ID = 1.06 mA

ID = 0.5 × 10 –3

A VD = 15 – 10.6 = 4.4V

VDS = 10 – 10 × 10+3 × 0.5 × 10–3 VGS = VDS = VD = 4.4V

= 10 – 5 = 5V The maximum allowable input signal is

VDS > VGS – VT determined by the condition to keep the

5>3–2 MOSFET in saturation

Hence, our assumption was true. Vgs – Vt = Vds

nCox W VGS + Vgs − Vt = VDS + Vds

Now, gm = 2 .ID

2L (DC) (AC)

−6

= 2 0.5 0.5 10

⇒ 4.4 + Vin – 1.5 = 4.4 + Vo

gm = 1 mA/V ⇒ Vin – 1.5 = Vo

Now, drawing the small signal equivalent ⇒ Vin – 1.5 = –3.3 Vin

circuit, we get ⇒ 4.3 Vin = 1.5

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1.5 −2.56 + 5

Vin = = 0.34V ID2 = = 2.44mA

4.3 1k

( )

2

AV

V

= O = −gm ro || RD||RL = −3.3 VGS1 − Vt

ID1 = ID2 = kn

Vin L 2

2

VA −3 5 − V1 − 1 V2 − (−5)

ro = = 47k 2 10 =

ID 2 1k

2

ID 4 − V1

−3

gm = = 0.725mA / V 2 10 = 2.44 10−3

VGS 2

For Vin = +2.5V

300k || 60k

vgs = v

300k || 60k + 2k in

= 0.9615 vin

vo = – gmvgs × 10k || 50k

= – 1mA × 0.9616 × [10k || 50k] NMOS

PMOS

( VGS − Vt )

2

2

Transistor is in cut off

( −V2 − 1)

2

V − (−5)

2 = 2 10−3

1k 2 V2

2

IDN = ID = kn ( VGS − Vt ) VDS − DS

V2 + 5 = V2 + 2V2 + 1 L 2

V22 + V2 − 4 = 0

Assuming VDS is small

By solving

IDN = ID = kn ( VGS − Vt ) VDS

V2 = 1.55V and –2.56V L

As VG = 0V IDN = 1 10−3 (5 − 1) ( VD − VS )

Therefore V2 = 1.55V = 10−3 4 ( −ID ) 10k − (−2.5)

Vgs<0 → wrong

= 1[4[–10ID + 2.5]]

V2 = –2.56 V

We get ID = 0.244 mA

Vgs>0 → acceptable

VD = –ID (10k) = –2.44V

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15. B. 17. D.

Small signal analysis of given figure as: For dc analysis, we redraw the circuit as

1 W

( V − VTh ) (let assume

2

Vo = –gmVGSRD Vi = VGS ID = C

2 n ox L GS

Vo MOSFET is in Saturation region)

AV = = gm RD [given AV = 5]

Vi

1

200 (278) ( VGS − 0.4 )

2

Or 0.5m =

5 2

gm = = 3.57 mA/V [given RD = 1.4 kΩ]

RD

Or VGS = 0.534V

In saturation region

Since, source is connected to ground, i.e.

ID = Kn(VGS – VT)2

VS = 0

ID

= 2Kn ( VGS − VT ) From above data

VGS

Vds>Vgs-Vth ( our assumption is correct)

ID

= 2Kn So, the voltage across R2 is

Kn

VG = 0.534 V = VGS

= 2 KnID

Since the gate current in MOSFET is IG = 0,

1 so current ID/10 flows through

Kn = 2 ncox L

Resistances R1 and R2. Therefore, we have

gm = 2nCox ID VG − 0 0.534

L R2 = = = 10.68 k

1 0.05m

lD

10

3.57 10−3 = 2 200 10−6 10−3

L Applying KVL in loop 1, we get

11 1

L = 31.9 1.8 − I (2k) − I (R + R2 ) = 0

10 D 10 D 1

16. D. Or R1 + R2 = 14k

All statements are correct. Thus, R1 = 3.32 kΩ

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For Ac Analysis capacitor are shorted, the In the given circuit.

dc sources are replaced by their internal VTN = 0.5V

resistance. Kn = 2mA/V2.

Id= 1 mA

And,

gm = 2KnId

gm = 2 2 1(mA / V2 ) = 2mA / V

And equivalent circuit of MOSFET.

|Av| = gmRD

AV 8

gm = = = 10 mA/V

RD 800

gm = 2KnID

W

gm = 2nCOX ID

L

W 1 1

10 10−3 = 2 120 10−6 0.8 10−3 Zi = = = 0.5k

L gm 2mA

W 21. D.

L = 520.83

Drawing the small signal equivalent of the

19. above circuit, we get

We draw, the small signal model of given

circuit as

RD

Now, I0 = − gmVgs

RD + RL

Applying KCL at the input, we have

Corner frequency due to coupling capacitor

Vgs

CC is defined as] Ii + gm Vgs + =0

R si

1 R si

fL = Vgs = −Ii

2R eqCC 1 + gmR si

Req = (7.2 + 7.8)kΩ = 15 kΩ I RD R si

Ai = 0 = gm

Ii R

D + R L 1 + g R

m si

So the coupling capacitor is

1

Now, RD = RL andR si =

1 gm

=

2 15 25 103 I0 1 1 1

Thus, Ai = = = = 0.25

CC = 0.424 μF. Ii 2 2 4

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22.

The amplifier can be modelled as shown in

fig below

RL

Now, Vout = A v0 Vin

RL + R 0

connected

From the circuit, we have output voltage,

V0 = -gmVGS × 10 k

At the input VGS = Vi

V0 = -gmVGS × 5 × 103

V0

AV = = −1.22 5 103

Vi

90

Thus, A VO = = 10V / V = – 6.12

9

|Av| = 6.12

Vout RL

= A 0

Vin RL + R 0 24. B.

Considering the upper MOSFET

70 10 103

= 10

8 10 103 + R 0 knW

(10 − V1 − 2)

2

I0 =

2L

⇒ R0 = 1.43 kΩ

1

(10 − V1 − 2 )

2

23. 2=

2

For the MOSFET transconductance is given

by.

2= (

1 2

V − 16V1 + 64

2 1

)

Id

gm = V12 − 16V1 + 60 = 0 V1 = 6V or10V

VGS

We choose 6V for which VSG > |Vt| to avoid

= 2 kn (VGS - VTN)

cut off.

gm = 2 × 0.75(VGS - VT)

For the lower MOSFET.

VT = 1V

And, I = kn(VGS -Vt)2 Kn W

(6 − V2 − 2)

2

ID =

2L

0.5 × 10-3 = 0.75 mA/V2 (VGS - Vt)2

1

( 4 − V2 )

2

VGS – Vt = 0.816 2=

2

gm = 1.22 mA/V

1 V22 − 8V2 + 16 = 4

And r0 = =

D V22 − 8V2 + 12 = 0

In AC analysis, the dc sources are

V2 = 2V V2 = 6V

replaced, by their internal resistance and

We choose 2V for which VSG > |Vt| (to

capacitor, are shorted. So we have the

avoid cut off)

small signal equivalent circuit as.

option B. is correct.

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For the analysis, we have the circuit 4.66 − 2.37

ID = = 0.76mA

3K

And,

14K

VG = 12 = 4.66V

22K + 14K

Applying KVL in train source loop

10 – ID × 4K – VDS – ID × 2K = 0

MOSFET Gate current IG = 0. VGS = VG –

VDS = 12 – ID (5k + 3k)

V S. VDS = 5.89

VG − VGS VDS>VGS-Vth (Assumption is correct)

ID =

Rs

26. D.

Assume that MOSFET in saturation region. Given

2

VG − VGS

= kn ( VGS − 1) / 2

2

ID2 = 75μA VGS2 = 2.5μA

RS

Given MOSFET is in non-saturation, region.

4.66 − VGS

= 0.4 mA / V2 ( VGS − 1)

2

So

3k

V2

ID = K VDS ( VGS − Vt ) − DS

4.66 − VGS = 1.2

mA

V 2 (

103 VGS

2

)

− 2VGS + 1 2

2

VDS

V 2 And VDS is small 0

3.88 − GS = VGS − 2VGS + 1 2

1.2

2

Drain current equation for VGS = 1.5V

VGS − 1 16VGS − 2.88 = 0

35 × 10–6 = K[0.1(1.5 – Vt)] … (i)

Solving the quadric equation we obtain. And drain current equation for Vgs = 2.5V

VGS =

2 ID1 35 0.1 (1.5 − Vt )

= =

VGS = 2.37V, −1.21V ID2 75 0.1 (2.5 − Vt )

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(VGS − VT )2 =

2 120 33

1 − VGS

ID = IDSS (VGS = –VT) = 0.52

VP

VGS = 0.52 + 0.7

2 2

1.5 5

ID = 6 mA 1 − = 6 VGS = 0.52 + 0.7

4 8

ID = 2.4 mA −1.22 + 3

RS = k

0.5

VDS = VPD – IDRD = 15 – 3 × 2.34 = 7.98 V

28. A & C

1.78

RS = = 3.56 k

0.5

Since VD > VS, Hence circuit works in

3 − VD 2.4

saturation region RD = = = 4.8 k

ID 0.5

1 w

so, 30 = ncox (VGS − VS )2

2 L

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Chapter

8 Multi-Stage Amplifiers

1

= is used then lower and upper cut

100

B. 300 Hz, 6 Hz stage of an amplifier. If each having a gain

5. If the lower 3dB frequency of an amplifier

D. 8.33 Hz, 6 KHz

is 100 Hz then the lower 3dB frequency of

2. Consider the given amplifier circuit shown

the cascade structure of three such

below. The circuit has following parameters amplifiers will be,

rπ = 0245 kΩ , Vt = 26mv A. 50.98 Hz B. 196.14 Hz

what is the value of 3 – dB frequency C. 155.37 Hz D. 64.35 Hz

f1(Hz) of the amplifiers due to coupling 6. An ideal voltage amplifier has voltage gain

of –1000 and has 1 pF capacitor connected

capacitor CC ?

between input and output terminal. If the

voltage source feeding amplifier has

internal resistance of 100Ω, the upper 3-

dB frequency will be ______ MHz.

7. Find the transfer function of the amplifier

shown assume that rds = ∞ & gm =

1ms for all MOSFET and R = 10KΩ and

C = 100 nF

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A. B.

S

3 S voltage gain AV. If β = 99 and rπ = 1 kΩ for

3 + 1 3 + 1

10 10

BJT and µ = 60, rds = 30 k for JFET.

−1000 −100

C. 3

D. 2

S S

3 + 1 3 + 1

10 10

8. For the multistage amplifier given below,

o

find its voltage gain ?

vin

(considering large β)

figure below as:

−R C

A.

1 / gm2 + RE || r1

B.

1 / gm1 + RE || r2

parameter hfc = 100, RE = hie = 1 kΩ. If

−R C z parameter of the circuit diagram is given

C.

1 / gm1 + RE || r1

as

−RC V1 Z11 Z12 i1

D.

1 / gm2 + RE || r2 =

V2 Z21 Z22 i2

9. The voltage VD (in V) for the given network

Z11 − Z21

shown below is. Then is

Z12

A. 100 B. 50

C. 75 D. 25

12. The two-stage system of figure employs a

transistor emitter-follower configuration

prior to a common base configuration to

ensure that the maximum percentage of

the applied signal appears at the input

terminal of the common base amplifier. In

figure the no load values are provided for

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each system, with the exception of Z I and 15. Read the following option and choose the

Z0 for the emitter follower, which are the correction option(s) if lower cut-off

loaded values. frequency of each amplifier is 50 Hz.

A. For a Cascade of 2 non interacting

amplifier, the overall cut off frequency

is 77.7 Hz.

B. For a cascade of 2 interacting

amplifier, the overall cut-off frequency

The total gain of the system is

is 77.7 Hz

A. 96.54 B. 0.714

C. For a cascade of 2 non-interacting

C. 104.21 D. 89.11

amplifier, the overall cut-off frequency

13. A frequency compensated OP-amp has an

is 77.5 Hz

open loop transfer function with signal pole

D. For a cascade of 2 interacting

106

A= . It works as non-inverting amplifier, the overall cut-off frequency

S

1 +

10 is 77.5 Hz.

16. For the below high frequency π model,

amplifier. The unity gain frequency is

Read all the options and choose the correct

Wt and 3 dB band width (W3dB) of the

option(s)?

closed loop non- inverting amplifier is ____

KHz.

and collection current is 1 mA. Base

current is 10 μA.

A. β cut off frequency of the BJT will be

14. Identical non interacting amplifier having

10.2 Hz

cutoff frequencies of multiple stage circuit

B. Unit gain frequency of the BJT will be

will be>

10.2 Hz

(More than one option may correct)

C. β cut-off frequency of the BJT will be

fL = lower cut-off frequency

1.02 kHz

fH = Higher cutoff frequency

D. Unity gain frequency of the BJT will be

A. fL = 31 Hz

1.02 kHz

B. fH = 31 Hz

17. For the below amplifier having hfe = 120 hi

C. fL = 12.9 Hz

= 2.2 kΩ.

D. fH = 12.9 kHz

Choose the correct option(s)?

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–163.64

B. Overall input Resistance will be (Seen

by Vi) 2.18 kΩ

C. Lower 3 dB frequency will be 6.63 Hz

D. Ro (Output Resistance) will be 3 kΩ

ANSWER

11.A 12. D 13. 100 14. A, D 15.B,C 16. A,D 17. A,B

SOLUTION

1. D. 2.

Am = open loop gain = 500 So, we have to find the 3dB frequency f1,

fL = 50 Hz, fH = 1 KHz due to CC. so, we will short remaining

If feedback is used, then gain decreases. capacitances

So, small signal equivalent circuit is

τ1 = rc Cc

The lower cut off will decrease and upper rc = (1.9k || 9.1 k || 0.248k) + 400Ω

cut off frequency will increase by using = 211.96 + 400

negative feedback. = 611.96 Ω

fL τ1 = rc CC

fL = [∵ 1 + βAm = 6]

(1 + Am ) = 611.96 × 20 × 10–6

50 = 0.0122

= = 8.33Hz

6 1

f1 =

21

fh = fh (1 + Am )

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3. 6.

Here device parameter is not given and we The amplifier can be like

Cm = C[1 – AV] = 1 pF [1 + 1000]

= 1001 pF

1 1

Cn = C 1 − = 1pF 1 − 1pF

A V 1000

so, τ = ro co

τ = (10k + 6.7k) 1 1

So, fH = =

2R sCm 2 100 1001 10−12

1

f = = 1.58 × 106 Hz

20

7. C.

1

20 = Let us consider the first stage of the

2 16.7 103 C0

amplifier & then draw the AC equivalent

1 ckt.

C0 = 3

2 16.7 10 20 As given capacitors are small capacitors so

= 0.476 μF their impact will come into picture

4.

Given = Av = 20

Stage = (Av)n

Drawing email signal AC equivalent ckt.

= (20)4

5. B.

FL

fL = 1

1/n

2 −1 z=R

cs

100 1

= R

1

= cs

23 −1 1

R+

FL’ = 196.14 Hz cs

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R 9. A.

z=

1 + RCS 2

VGS

R ID = IDSS 1 −

Vo(s) = −gmVgs VP

1 + RCS

2

V (s) −gmR V

o = ID = 8 1 − GS

vin(s) 1 + RCS 4

Vo (s) −gmR

3 = –2.4ID

=

Vin(s) 1 + RCS −VGS

ID =

2.4

−1000

TF = 3 Upon solving we get,

S

3 + 1 VGS = –2.544 V1 –6.29V

10

VGS is not greater than the Vp(considering

8. B.

Draw the small signal equivalent of this magnitude)

For transistor

IE IC ID = 1.06 mA

0.06

IB = = 0.01325mA

80

VD = 9.07V

10. C.

re1

vbe1 = vin

re1 + RE r2

V0 = – gm1VbeRc

re1 vin

= −gm1 RC

re1 + RE || r2

sin ce, re =

gm

1

v0 gm1

So, = −gm1 Rc

vin 1

+ RE r2 From figure:

gm1

v0 −R C = 100 ib [2k]

=

vin 1 Vin = Vgs + ib [1k] + 100ib [2k]

+ RE || r2

gm1

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ib [30k] − 60 Vgs + ib [1k] + 101ib (2k) = 0 Z11 = (1 + 1 × 101 + (101)2) k

ib [30k + 1k + 101(2k)] = 10.3 MΩ

Vgs =

60 Z21 = (101)2 × 1 kΩ = 10.2 MΩ

Vgs = ib [3.883 k] Z12 = Z22 = RE = 1 kΩ

Vin = ib [3.883k] + ib [1k] + 100ib (2k)

Z11 − Z21 (10.3 − 10.2) 103 k

Vin = ib [204.88k] =

Z12 1k

Vo 100ib [2k]

Voltage gain = A V = = = 0.976 = 0.1 × 103 = 100

Vin ib [204.88k]

12. D.

11. A.

For the emitter-follower configuration the

Drawing the hybrid model of two transistor

loaded gain is

together.

Zi2 25

V01 = A V = (1)Vi1

Zi2 + Z01 VNL i1 25 + 10

V01 = 0.714Vi1

V01

And, A vi = = 0.714

Vi1

RL

V02 = A

RL + R OL VNL

9.6k

Given hie = 1 kΩ, RE = 1kΩ Vi2 = 200Vi2

9.6k + 4.6k

Ib2 = I1 (1 + hie ) → from circuit V02 = 135.21Vli2

A V2 = = 135.21

Vi2

IRE = Ib2 + hfc Ib2 + I2

A VT = A V1 A V2

→ apply KVL to the loop containing

= 0.714 × 135.21

V1, RE etc we get

= 96.54

(

V1 = hie Ib1 + hie Ib2 + Ib2 + hfc Ib2 + I2 RE ) Zi1

A VS = A VT

( ) ( )

2

V1 = hie + hie 1 + hfc + 1 + hfc RE I1 + I2RE Zi1 + R S

→ apply KVL to the loop containing V2 12k

= 96.54

12k + 1k

(

V2 = Ib2 + hfC Ib2 + I2 RE ) AVS = 89.11

( )

2

= 1 + hfC I1RE + REI2 Option (D) is correct.

13.

( ) ( )

2

V1 hie + hie 1 + hfc + 1 + hfc RE RE I

1 AO 106

= I A= =

V2

( )

2

1 + hfc RE RE 2 1+

S

1+

S

W3dB 10

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Im = = =

Gain bandwidth product = 106 × 10 = VT 26 mA 26

107 rad/sec Im 1

fT = =

Gain of closed loop 2(c + c ) 26 2 6 10−6

R 990

A V = 1 + f = 1 + = 100 106

R 10 fT = = 1.02 kHz

312

∴ 3dB bandwidth of closed loop system

fT f 1.02 kHz

107 f = = T =

W3dB closed loop = I 100

gain of closed loop C

IB

= 105

14. A & D f = 10.2 Hz

fL = = 31 Hz

21/2−1 0.645

15. B & C

For interacting amplifiers

𝐺𝑎𝑖𝑛 = − =−

ℎ𝑖𝑐 2.2

fL = 1.1 502 + 502

Gain = –163.64

For non-interacting amplifier Ri = RB || hie = (250 || 2.2) kΩ

fL1 Ri = 2.18 kΩ

fL = N = 2 Here

1/N−1

2 1 1

fL = =

50 50 2(R L + R L )C 2 (6 + 6) 0.5 10−3

fL = = = 77.5 H2

21/N−1 0.645

000

16. A & D fL = = 26.52 Hz

12

β cut off frequency fs = fI

Ro = 6 kΩ

fT = unity gain frequency

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Chapter

9 Feedback Amplifiers

1. The feedback used in the circuit shown 4. An amplifier have a gain of 80 without

below can be classified as feedback and its input and output

resistance is given by 2kΩ and 5 kΩ. The

amplifier using series-shunt negative

feedback with a feedback factor of 0.05.

The input and output resistance of

feedback system is

A. Rin = 1 k Ω R of = 5 k Ω

B. Rin = 10 k Ω R of = 5 k Ω

A. Shunt – series feedback

C. Rin = 10 k Ω Ro = 1 k Ω

B. Series – shunt feedback

D. Rin = 15 k Ω Ro = 7 k Ω

C. Shunt – shunt feedback

5. Consider the following statements

D. Series – series feedback

regarding the trans-impedance of the

2. Consider the following feedback amplifiers

Amplifier:

whose open loop gain is very high, the

closed loop voltage gain is ______ (i) The input impedance of the circuit

decreases and output impedance of

the circuit increases.

(ii) Amplifier have a shunt-shunt topology.

(iii) At input side current mixed and

voltage sampled at output side.

(iv) Bandwidth of transimpedance amplifier

Increased.

3. If three amplifiers having the same Which of the above statement is /are

bandwidth are cascaded, the bandwidth of

incorrect?

the resulting amplifier will be

A. only (i)

A. Better than that of each stage

B. (i) and (ii)

B. Worse than that of each stage

C. (ii) and (iii)

C. Same as that of each stage

D. (i), (ii) and (iii)

D. None of the above

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applied for unstable system. C. series-series D. shunt-series

Reason (R): Oscillator is a system that 10. An amplifier has an open loop gain 600.

output is infinite at Zero input.

And a feedback 0.04 . If open loop gain

A. Both A and R are true, and R is the

changes by 15% due to change in closed

correct explanation of A

loop gain is _______(Rounded up to two

B. Both A and R are true, but R is not the

decimal value)

correct explanation of A

C. A is true, but R is false 11. Consider an op-amp circuit given in Figure.

7. Consider the amplifier circuit shown find

feedback factor β (in %)?

R1 = 1.8 kΩ and R2 = 200 Ω. So amplifier

8. Given the basic feedback amplifier (op- gain of the circuit is ______ V/V (Rounded

amp) has A = 104, Rin = 105Ω Ro = 1 kΩ. up to two decimal value).

Vo 12. The given circuit has a feedback factor of

Find

VS (Assume Beta value to be very high)

amplifier given below

A. –0.4 B. 0.4

C. 2.5 D. –2.5

MSQs:

13. Which of the following feedback (s0

inverse(s) the overall input Resistance of

an amplifier?

A. Voltage series B. Voltage shunt

C. Current series D. current shunt

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voltage Buffer?

A. Buffer is a circuit which provides

impedance matching between source &

Load

B. Buffer is a circuit, used to transfer

Then which of the following statement

maximum power form source to load.

is/are correct?

C. Input impedance is very large for

A. Input voltage applied to basic

voltage Buffer

transconductance amplifier is 5 mV.

D. Output impedance is very low for

B. Forward gain (without feedback) of

voltage Buffer

transconductance amplifier A is 2

15. An amplifier has high frequency gain given

(A/V).

AM

by AH = where AM = 1000 and ω2 = C. Feedback gain (β) is 9.5 (V/A)

j

1+ D. Overall gain 0.1 A/V

2

17. For shunt-shunt feedback circuit using an

104 Rad/sec.

ideal trans-resistance amplifier consider

Choose the correct option(s) if we increase

IS = 100 μA

the upper corner frequency ω 2 to 105

If = 95 μA

Rad/sec.

Vo = 10 V

A. Feedback factor required is 10

Then which of the following statement

B. Feedback factor required is 0.009

is/are correct?

C. New overall gain of amplifier is 200

A. Input current through amplifier is 5 A

D. New overall gain of amplifier is 100

B. Open loop gain is 2 × 106 V/A

16. A series feedback amplifier using a

C. Feedback factor is 9.5 A/V

transconductance amplifier operates with

D. Feedback factor is 9.5 μA/V.

VS = 100 mV, Vf = 95 mV, and Io = 10 mA,

respectively.

ANSWER

11. 9.99 12.D 13.A,C 14.A,B,C,D 15. B,D 16. A,B,C,D 17.B,D

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SOLUTION

1. C. 4. C.

The small signal equivalent circuit of given For a series-shunt topology, the input

amplifier is shown below. Here the resistance is given by.

feedback circuit samples the output R inf = Ri (1 + Aβ)

voltage and produces a feedback current and output resistance is given by

Ifb which is in shunt with input signal. RO

R of =

(1 + A)

A = 80 β = 0.05

R inf = 2 (1 + 80 × 0.05) K = 10Ω

5K 5K

R of = = = 1K

(1 + A) (1 + 0.05 80)

5. C.

In the input side of transimpedance

So, this is a shunt-shunt feedback Amplifier current mixed in shunt and at

configuration. output side voltage sampled in shunt

2. therefore these is also known as shunt -

Consider only feedback network shunt Amplifier.

In transimpedance Amplifier input and

output resistance decreases.

Bandwidth of feedback Amplifier Always

increases.

6. A.

Vf 100 1

= = =

V0 15000 + 100 151

AV 1

A Vf = = ( A V )

1 + A V If Aβ = 1 So,

A Vf = 151 A V

= 0

1 − AB Vi

3. B.

V0 A

A single stage amplifier has finite = =

Vi 0

bandwidth. If you cascade multiple stages,

Output is unbounded for bounded input

more gain is achieved, but additional

and oscillator is unstable system.

bandwidth limitations occur since each

So, option (A) is correct.

stage has finite bandwidth.

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7. A. 8.

Now, here on input side the feed network

i.e.,

Vd − Vs Vd V − Vo

− − − d =0

Is coming in the input loop, so it is in 1k 100k 1M

series, so it is voltage mixing ⇒ Vo = –1011 Vd – 1000 Vs …(i)

Now, on output side, the feedback n/w KCL at node (2)

with 4R resistance is directly connected to Vo − 104 Vd Vo + Vd Vo

+ + =0

output Vo, 1k 1M 2k

So, it is voltage sampling, and it is in shunt | 50 |

Vd = Vo …(ii)

So, feedback amplifies is 107

Voltage – voltage Substitute 2 in 1

Or series – shunt 1501

Vo = −1011 Vo − 1000VS

Now, the feedback network for finding 107

feedback factor, for finding input loop Vo

= −868.2

output voltage grounded and for finding VS

output loop, input current is zero open 9. A.

circuited so,

vf = vo

6R R + 3R Rf is linked directly to the output, therefore

1 1 it is a voltage sampling.

v f = vo

3 4 Hence it is voltage-series topology which is

also called series-shunt topology.

vf 1

=

vo 12

=100/12 = 8.33%

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10. 𝐴𝐻

𝐴𝐻 𝐹 =

1 + 𝛽𝐴𝐻

A

Given A = 600 β = 0.04 & = 15% A

A AH F =

1 + j/2

Change in closed loop gain A

1+

A f A / A 1 + j/2

=

Af 1 + A

A

AHf =

15 15 1 + A

= = % = 0.6% j

1 + 600 0.04 25 1+

2 (1 + A)

11.

A

A Overall gain =

Af = 1 + A

1 + A

Overall frequency = (1 + βA)ω2

Af = gain with feedback

104(1 + βA) = 105

β = Feedback factor

1 + βA = 10

R2 200

= = = 0.1 1000

R1 + R2 1.8 103 + 200 Overall gain = = 100

10

A = 1000

9

1000 1000 = = 0.09

Af = = = 9.99 1000

1 + 1000 0.1 101

16. A, B, C, D

12. D.

Input voltage to basic transconductance

V

Feedback factor β = f . amplifier,

Vo

Vin = VS – Vf

−ICRE = 100 mV – 95 mV

=

ICR c

= 5 mV

5k So, option A is correct.

=−

2k

From figure,

β = –2.5. A = Io /Vin

13. A & C 10 mA

= = 2 (A/V).

Feedback Rif Rof 5 mA

Voltage series Ri⋅ D↑ Ro/ D↓ So option B is correct.

Voltage shunt Ri/D↓ Ro/D↓ Vf 95 mV

= = = 9.5 (V/A)

Current series Ri⋅ D↓ Ro⋅ D↑ Io 10 mA

Current shunt Ri/D↓ Ro.D↑

So, Option C is correct.

14. A, B, C & D

A 2

15. B & D Af = = = 0.1 A/V

1 + A 1 + 2(9.5)

𝐴𝐻

For negative feedback factor 𝐴𝐻 𝐹 =

1+𝛽𝐴𝐻

So, option D is also correct.

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17. B, D A = 2 × 106 V/A

= =

Vo 10

Given output voltage is 10 V.

= 9.5 × 10–6 = 9.5 μA/A

V 10

So open loop gain A = o = So, option C is incorrect while option D is

If 5 10−6

correct.

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Chapter

10 Power Amplifiers

10W of audio power to the output load. If

the output transformer is 80% efficient

then what is the minimum average

dissipation rating required for each

transistor?

A. 3.4 W B. 1.7W

C. 2.5W D. 5W A. 170 B. 196

2. A class B push-pull amplifier is supplied C. 189 D. 200

with VCC = 50V. The signal brings the 5. Consider the circuit shown in figure below:

collector voltage down to Vmin = 5V. The

total dissipation from both transistors is

30W. Find the total input power?

3. Assertion (A): For class A operation for CE

transistor amplifier, the operating point

cannot be fixed near VCE = 0 point.

Reason (R): During the positive half of the

input cycle, the transistor may be driven

from “active region” to “saturation - The maximum ac output power and the dc

region”, thus losing the class A wave shape input power of the amplifier are

in the output. respectively: (Given Vcc = 20V)

A. Both A and R are true and R is the A. 12.5W, 15.5W

correct explanation of A B. 3.25W, 7.96W

B. Both A and R are true, but R is not the

C. 6.25W, 3.25W

correct explanation of A

D. 6.25W, 7.96W

C. A is true but R is false

6.

D. A is false but R is true

4. Consider the class AB stage amplifier

shown in figure with VT (thermal voltage)

= 25mV. If both transistors have reverse

saturation current Is = 10–15 A, the value of

quiescent current Ic is ______ μA (Assume

beta to be very high)

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complimentary symmetry shown in the

figure,

VCC = 15V, RL = 10Ω

Find the maximum signal output power,

corresponding transistor power dissipation

and conversion efficiency?

A. 14.31 W, 3.07 W, 78.5% What is the value of RB in kΩ that locate

B. 15W, 3.07W, 81.2% the Q point at the center of the load line?

C. 14.31W, 2.07W, 62.5% MSQs:

D. 15W, 2.07W, 78.5% 10. Choose the correct option(s)

7. A single ended class A transformer coupled A. In class B Power amplifier, there is no

amplifier is to deliver a power of 50mW to cross over distortion

the load in the secondary. Given efficiency B. In class AB Power amplifier, there is no

of transformer is 70%, the transistor cross over distortion

chosen should have a power dissipation C. Any amplifier can be analyzed using h-

capability PT given approximate to? parameters

A. 35 mW B. 70 mW D. Any power amplifier can be analyzed

C. 180 mW D. 140 mW using h-parameters

8. A sinusoidal signal of 100Hz is applied to 11. For a class B amplifier, providing 20 V peak

an amplifier. The output current is I0 = 10 signal to 16 Ω load and power supply of 30

sin(628t) + 2 sin (1256t) + 1 sin(2512t) V, choose the correct option(s)?

what is the approximate percentage A. Output power will be = 12.5 W

increase in power due to distortion? B. Output power will be = 25 W

A. 4% B. 5.0% C. Efficiency of amplifier will be = 52.5%

C. 3% D. 6.5% D. Input power will be = 23.9 W

9. Consider a class A power amplifier circuit

given below:

ANSWER

11. A,C,D

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SOLUTION

1. B. 3. A.

Power delivered to load PL = 10 W For class A operation, operating point is in

Pout (ac) =

output transformer efficiency R is also correct because if operating point

will be at VCE = 0, for positive half cycle,

10

= = 12.5W

0.8 transistor will be in saturation so wave

shape will be lost in the output. This is

P (ac) 12.5

Pin(dc) = out = = 15.625W correct reason.

0.8

4. B.

Minimum average power dissipation

For dc analysis, we redraw the circuit as:

Pd = Pin(dc) − Pout (ac)

= 15.625 − 12.5 = 3.125W

required for each transistor

Pd 3.12

= = = 1.56 W

2 2

2.

VCC = 50V

Applying KVL in loop 1, we get

Vmin = 5V

VBE1 + VEB2 =1.3 V

Total power dissipation Pd = 30W IC I

Or VT ln + VT ln C = 1.3

∴Pd = Pin (dc) – Pout(ac) Is Is

30 = VccIm − Vcc − Vc min

2 IC

Or 2VT ln = 1.3

Is

2 I

30 = 50 Im − m [50 − 5] 1.3

2

−15 22510−3

So, Ic = 10 e = 196 μA

100 45

30 = − I

2 m 5. D.

We redraw the given circuit as:

30

= Im

9.33

30

Im = = 3.215A

9.33

2 2

Pin (dc) = Vcc Im = 50 3.215

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VCC

Vout (peak) = VCBQ =

2

20

= = 10V

2

The maximum peak output current is

VCEQ

Iout (peak) =

RL

V0,max = VCC = 15V

10

= = 1.25A

8 V0,max 15

Im = = = 1.5A

So, we obtain the ac output power as RL 10

1 Im

Pout = I V I0,RMS = = 1.06A

4 CQ cc 2

1

= 1.25 20

4 Im

I1,DC = I2,DC = = 0.477A

= 6.25W

The dc input power for the amplifier is (a) P0,AC = I20,RMS RL

Pdc =

= 11.24W

1.25 20

=

PI,DC = 2 × VCC × IDC

= 7.96W = 2 × 15 × 0.477

6. A. = 14.31W

During positive half cycle of input Q1 is ON (b) Total transistor power dissipation

=PI,DC – P0,AC

and during negative half cycle of input,

= 14.31 - 11.24

Q2 is ON, so that we get a full-wave across

= 3.07W

the load RL.

P0,AC

(c) Efficiency = = 100%

PI,DC

11.24

= 100%

14.31

η = 78.5%

7. B.

Pac = 50 mW at the secondary

KCL at the output node:

Transformer efficiency = η = 70%

I1 = I0 + I2

Input power to transformer

Following are the three current-waveforms

Pac 50 10−3

Pin = =

over one cycle 0.70

Pin = 71.42 mW

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Pac 71.42 In class B, there is cross over distortion,

Pdc = = = 142.85mW

0.50 because both transistor of push Pull

Maximum transistor dissipation power amplifier are maintained in cut off state.

= 142.85 - 71.42 = 71.425 ≈ 70 mW

Hence, they take time to come to ON

8. B.

state.

For 1Ω resistance

So option A is incorrect.

Total power:-

In class AB, the transistors are kept in ON

(10)2 (2)2 (1)2

= + + W state at low current value or just ON State

2 2 2

= 52.5 W therefore cross over distortion is

Power due to distortion: eliminated.

2 2 So option B is correct.

(2) (1)

+ = 2.5 W

2 2 Any amplifier can be analyzed using h-

Hence, fundamental power = 50 W parameter model. But the analysis of

Percentage increase due to distortion:

Power amplifier is not about the voltage

(2.5/50) × 100= 5.0%

gain, input resistance and output

9.

resistance. The analysis of Power amplifier

For the Q-point to be at the center of the

load-line, we have is about power delivered by source and

VCE = = = 6V

2 2 Parameters are not analyzed by using h-

12 − 6 parameter model.

And IC = = 60 mA

100

So, option C is correct, but option D is

60 mA

also, IB = = 1mA incorrect.

60

11. A, C & D

for dc-analysis, we redraw the circuit as

VP 20

I= = = 1.25 A

RL 16

2Im 2

INC = = 1.25 = 0.796 A

(Pi)dc = Vdc × Idc = 30 × 0.796 = 23.9 W

VP2 (20)2

Pout = = = 12.5 W

2RL 2 16

Applying KVL in loop 1, we have

12 - IBRB- 0.7 = 0 Pout 12.5

= 100 = 100

12 − 0.7 Pin 23.9

Or RB =

IB

= 52.5%

RB = 11.3 kΩ

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Chapter

11 Differential

B

Amplifiers

1. CMRR (Common Mode Rejection Ratio) of a 4. For an op-amp having a slew rate = 2

differential amplifier is defined as the ratio V/μs, the maximum closed loop voltage

gain that can be used when the input

of

signal varies by 0.4 V in10 μsec is ______?

A. Common Mode gain to the Differential

A. 50 B. 100

Mode gain C. 75 D. 25

B. Differential Mode gain to Common 5. For which of the following amplifier circuit

resistor, Rf, the voltage gain is computed

C. Any one of the above

as:

D. None of the above

Rf

1 +

2. Find differential gain of a dual input R1

unbalanced output differential amplifier if A. Inverting amplifier

Rc=20kΩ and rE=2kΩ. B. Non-inverting amplifier

C. Unity follower

A. 1 B. 2

D. Summing amplifier

C. 3 D. 5

6. In the following Circuit, transistor, M1 and

3. For the differential amplifier as shown in M2 has following parameters.

figure find the magnitude of gain of

=26 mV).

W W

L = L = 20

1 2

( VTH )1 = ( VTH )2 = 1V

(K ) = (k )

n

1

n

2

= 100/μA/V2

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A. 1V, 1V, –1.1V R2 = 4 kΩ,

B. 1V, 2V, 1V R4 = 8.6 kΩ,

C. 2V, 1V, 1.32V R3 = 3.3 kΩ)

D. 1V, 1V, -1.32V V1 = 2.2 V and V2 = 1.2 V

7. The open loop gain of an operational A. Circuit represents differential amplifier

amplifier is 10 . An input signal of 1 mV is

5

B. Output voltage Vo = 2.15 V

applied to the inverting input with the non- C. Common mode voltage gain

inverting input connected to the ground. magnitude = 0.2

The supply voltages are ±10V. The output D. Difference mode voltage gain = 2.5

of the amplifier will be? 9. Choose the correct option(s)

A. + 100V B. – 100V A. Differential Gain is the ratio of output

C. + 10 V D. – 10V voltage to differential voltage

MSQs: B. Common voltage is the average sum of

8. For the given figure, consider the OP-AMP to input voltage

be ideal and choose the correct option(s)? C. If gain is 103 and V2 = 5 V and output

voltage is -10 V, then V1 = 5.005 V

D. If gain is 103 and V2 = 5 and output

voltage is -10 V, then common voltage

is 5.005 V

ANSWER

SOLUTION

1. B. 2. D.

CMRR dB = 20log10 d

Ac differential amplifier,

Differential gain Ad= Rc/2rE

Thus, it’s the ratio of Differential mode

Ad = {20x103}/{(2x2) x 103}

gain to the Common mode gain.

Ad=20/4

Ad=5

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Current through 10K resistor = I10K Hence, using voltage divider,

15 − 0.7 − (−15) R1

I10K = = 2.93mA V1 = V

10 R1 + R f o

Current through Q1 and Q2

Vo R

I voltage gain = = 1 + f

= 10K = 1.465mA V1 R1

2

V0 −l 6. D.

= −gmR C = C R C

Vin VT (VGS)1 = (VGS)2 = –V3

−1.465

= 2500 = −140.86

26

4. A.

V0 V

= ACL l

t t

V0 / t SR

AcL = =

Vl / t Vl / t

2V / sec

= = 50

0.4V / 10S

ACL = 50

Assume FETs are in Saturation using KCL at

5. B. node Voltage V3

A non-inverting amplifier can be ID1 + ID2 = 200A

represented as:

200

ID1 + ID2 = = 100A

2

W

Since is Same for both M1 and M2 So

L

kn W

( VGS − VTH )

2

ID =

2 L

( VGS − 1)

2

100 10−6 =

amplifier can be drawn as: 2

⇒ (VGS – 1)2 = 0.1

∴ VGS = 1.32V

VD1 = 5-ID1(40 x 103) = 1V

(VDS)Sat= VGS - VTH= 0.32

VGS = VG – VS = 1.32

⇒ 0 – Vs = 1.32

⇒ Vs = -1.32V

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(VDS) > (VDS)sat⇒ So the assumption is Vd

V1 = VCM +

true. 2

In the Circuit. V3 = – VGS = – 1.32V Vd

V2 = VCM −

V1 = VD1 = 1V 2

V2 = VD2 = 1V V V

Vo = 2.4 Vcm + d − 2.6 Vcm − d

7. D. 2 2

Output voltage of op-amp is: 5

Vo = −0.2Vcm + V

V0 = Av (V+– V-) 2 d

= 105 [0 – 1mV] Vo = –0.2 Vcm + 2.5 Vd

V0 = -100V |Acm| = 0.2

If the output voltage is greater than the |AD| = 2.5

supply voltage, then the op-amp is 9. A, B, D

saturated, so output voltage: Given A = 103

V0 = +Vsat [non-inverting voltage > V2 = 5 V & V1 = –10 V

Inverting voltage] Vo Vo

Ad = =

= – Vsat [inverting voltage > noninverting Vd V2 − V1

voltage] Hence, option A is correct.

So, V0 = - 10 V −10

103 =

8. A, B, C, D 5 − V1

The given circuit iis a difference amplifier V1 = 5.01 V

R R V1 + V2

Vo = 1 + 4 V1 − 4 V2 As VC =

R3 R3 2

Vo = 1 + 2.2 − 1.2 = = 5.005 V

3.3 4 + 2 3.3 2

= 22.4V1 − 2.6V2 Hence, option B is correct.

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Chapter

12 Operational Amplifiers

1. Find Vo if 5 mv, 1kHz sinusoidal signal is 4. Find the input resistance in the circuit

applied at input terminal. If R = 10 kΩ and shown

C = 10 μF

A. R1 B. 2R1

C. R1+R2+R3 D. 1

−0.1 5. Consider the OP Amp to be ideal the

A. cos (2π×103t) mV

2 103

voltage at inverting terminal V– is _____ V

B. –0.2π cos (2π × 10 t) volt

3

D. − cos (2π × 103t) mV

2

2. For the following circuit. Find the currents

I1& I2? (assuming op – amp to be ideal)

find its cutoff frequency (in KHz)

B. 100 μA, 10.1 mA

C. 10 μA, 101 μA

D. 1 mA, 10 μA

3. An op–amp has common mode gain of 20

and the value of CMRR is 200. Calculate

the output voltage if the input voltages are

7. The diode has forward voltage drop of V o =

200 μV and 140 μV

0.7V else it is ideal. If Vin is –10V then

A. 243.4 mV B. 234.3 mV

find Vo_____

C. 240 mV D. 236.6 mV

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oscillation of frequency 1 kHz in the circuit

of fig is

shown are (assume Vz = 8.3V, Vy = 0.7V).

1

A. F B. 2π μF

2

1

C. F D. 2 6 F

2 6

11. In the circuit shown in fig the op-amp is

ideal. If βF= 60, then the total current

A. 0.8 V and -0.8 V

supplied by the 15 V source is

B. 0.9 V and -0.9 V

C. 0.1 V and -0.1 V

D. 0.75 V and -0.75 V

9. For the transistor in the circuit shown in

figures below, the parameters are β = 100

and VEB(ON) = 0.6 V. The diode is an ideal

zener with VZ = 5.6 V and the op-amp is

ideal. Determine the value of load

resistance RL in kΩ such that the load

A. 123.1 mA B. 98.3 mA

current is a constant. (Take VBC = 0.2 V)

C. 49.4 mA D. 168 mA

12. For the operational amplifier circuit shown

in the figure below, what is the maximum

possible value of R1, if the voltage gain

required is between -10 and -25? (The

upper limit of Rf = 1 MΩ)

A. infinity B. 1 M Ω

C. 100 k Ω D. 40 k Ω

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VBE(ON) = 0.7V and β = 100. Assume op-

amp to be ideal.

C)

Functions

Q – Amplifier

R – Comparator

A. R - S – P B. R - P - S

B. Non-inverting differentiator 17. Assume that the Op-amps are ideal then

C. Non-inverting integrator find Vo as a function of V1 and V2.

D. Low pass filter

15. The OP Amp circuit shown in figure is

R2ZL

A. A sample and hold circuit A. Vo = ( V − V1 )

R1R3 2

B. An integrator

R1ZL

C. A zero crossing detector B. Vo = ( V − V1 )

R2R3 2

D. A half wave precision rectifier

16. Match the following circuit: R 2ZL

C. V0 =

R1R3 1

( V − V2 )

A)

R1ZL

D. V0 = ( V − V2 )

R2R3 1

current io?

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S initially closed and is opened at t = 0.

which of the following is correct regarding

output (assume forward drop of Zener to

be 0)

−in −in

A. B.

10 K Rf

−in

C. D. None of these

RL A. It makes a transition from –5V to +5V

19. For the given op – amp circuit. Find the at t = 12.98 μs

common mode rejection ratio(in db). B. It makes a transition from –5V to +5V

Consuming op – amp to be ideal at t = 2.57 μs

C. It makes a transition from +5V to –5V

at t = 12.98 μs

D. It makes a transition from +5V to –5V

at t = 2.57 μs

22. Given transistors Q1& Q2 are identical. The

output voltage at T = 300K is

Schmitt trigger whose voltage

characteristic is given. Find the time period

of vo(t) in msec.

v R

A. log10 2 1

v1R2

v R

B. 4.605log10 2 1

v1R2

v R

C. 2log10 2 1

v1R2

v R

D. 2303log10 2 1

v1R2

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practical op – amp with input impedance C. –1.25 mA, 2.5V D. 1A, 2V

Rin, and op loop gain Ao1, then what is the 25. For the feedback amplifier as shown the

pole location of this circuit and also find transconductance gm is _____mA/V

the type of the circuit

1 R

A. − 1 + , differentiation 26. In the circuit shown in figure, considering

1 Rin

Rc 1 +

Aol op-amps as ideal, then the value of

V0

is

Vi

1 R

B. − 1 + ,interator

RC(1 + Aol) Rin

1 R

C. − 1 + ,integrator

1 Rin

Rc 1 +

Aol

1 R

D. − 1 + , differentor

RC(1 + Aol) Rin

−1 −1

24. Consider the circuit shown below. The A. B.

sCR sC2R2

transistor parameter are Vth = 2.5 V,

−1 −1

Kn = 0.25A/V2 C. 2 2 2

D.

s CR sCR2

(assuming op amp to be ideal and MOSFET

27. For the ideal op-amp circuit shown in

to be in saturation). Find the output

V0

current ID and minimum voltage VDD for figure below, the value of at very high

Vi

MOSFET to be in saturation

frequencies is___?

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The maximum input frequency for an C.

undistorted output is____kHz?

D.

with a common mode input voltage of +3V

(DC) and a differential input signal of 80

mV peak sine wave. Find V0?

A. -4.04 sinωt (V)

C. High pass filter D. Band pass filter B. – 6.06 sinωt (V)

30. The transfer characteristics of the circuit C. – 8.08 sin ωt (V)

shown below: D. – 10.10 sin ωt (V)

32. The value of R2 in the regenerative

comparator circuit shown in figure A using

the obtained transfer characteristics as

shown in figure B is?

Figure-A

A.

Figure-B

B.

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C. 1 k Ω D. 0.5 k Ω V0 = AV1 + BV2

33. The circuit shown is:

A. A = 9.9

B. A clamper

B. A = –9.9

C. A lag compensated inverting amplifier

D. A narrow band video amplifier C. B = 10

C = 10 μF. The input voltage is a sinusoidal 37. For the following circuit as shown in figure

at 50 Hz. With an RMS value of 10 V. below:

Under ideal conditions, the current Is from

the source is:

is equal

A. 20π mA lagging by 90°

than the input voltage

B. 20π mA leading by 90°

C. The circuit is equivalent to all pass

C. 10π mA leading by 90°

filter.

D. 10π mA lagging by 90°

D. The circuit is Notch filter.

35. The output of op Amp V0 (in volts) is, if

VBE(ON) = 0.7V and β = 100. Assume op- 38. Consider following options for shown

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A. Slew rate is maximum rate of change 41. Consider an ideal op-amp circuit as shown

of an op-amp’s output voltage in figure below:

B. Slew rate is minimum rate of change

of an op amp’s output voltage

C. Slew rate is measured in volts per

microseconds.

D. For the curve shown slew rate is 18

V/µsec. Here, open loop gain is 104.

39. Consider a Schmitt Trigger circuit as shown Suppose we want to obtain closed loop

in figure below gain of 10, then which of the following

statement is/are correct?

A. If R1 = 1 then R2 = 9.01 (Both in kΩ)

B. The Ratio of R2/R1 is 9.01

C. The Ratio of R2/R1 is 10.9

D. If R1 = 1 then R2 = 10.9 (Both in kΩ)

42. For the given wein Bridge Oscillator which

of the following combination(s) of R 1 & R2

A. Upper Threshold point is 2 V

is/are correct?

B. Lower Threshold point is –5 V

C. Hysteretic width is 6 V

D. Hysteretic width is 7 V

40. Consider a lossy integrator circuit as shown

in figure below:

A. R1 = 2 kΩ R2 = 4 kΩ

B. R1 = 4 kΩ R2 = 9 kΩ

D. R1 = 9 kΩ R2 = 4 kΩ

20 dB and Gain = 3 dB down from Peak.

43. Choose the correct option(s) regarding the

Then which of the following statement

below circuit?

is/are true?

A. R1 is 1 kΩ

B. R1 is 2 kΩ

C. Rf is 20 kΩ

D. Rf is 10 kΩ

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B. VA = –300 cos 50t C. Condition to prevent distortion in op-

C. VO = 15 sin 50t dvo

amp is slew Rate

D. Vo = –15 sin 50t dt

44. Choose the correct option(s) regarding D. Slew Rate induced distortion may

slow rate of an op-amp? happen in the op-amp if the input

A. It is the maximum Rate at which the signal has rapid changes.

output of an Op-amp can change

ANSWER

11.C 12. C 13.5.2 14.B 15. C 16. A 17. C 18. B 19. 41.61 20. 8.1

21.D 22. A 23.B 24. D 25. C 26. C 27. 5 28. 39.8 29. B 30. B

31. C 32. B 33. A 34. D 35. 5.2 36. A,D 37. A,C 38.A,C,D 39. A,C 40. A,D

SOLUTION

1. C. d

= – 104 × 10 × 10–6 [5 sin (2π × 103t)

dt

× 10–3]

= – 0.1 × 5 × 10–3 × 2π × 103 cos (2π ×

103t)

∴ Vo = – π cos (2π × 103t) volt.

2. B.

Given Vi = 5 sin (2π × 10 t) × 10

3 –3

volt Draw circuit

& Vo = – Ic × R

dc

Now Ic = C

dt

And Vc = Vi

d i

∴ vo = – RC

dt

Va = Vb = 0 (virtual ground)

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So 4. B.

1−0

I1 = = 0.1mA

10k

I1' = I1 = 0.1 mA

VC = 0 – 10 K × 0.1 mA

Applying KVL at input side

VC = – 1V

∴ –V2 + iin × R1 + iin × R1 + V1 = 0

0 − (−1V)

I2 = = 10mA (V2 – V1) = iin × 2R1

100

V2 − V1

I2 = I2’ + I1 = 2R1

iin

I2 = 10.1 mA ∴ input resistance =2R1.

3. A. 5.

Let V– = 6V

Give Acm = 20,

O − 6 6 − V0

CMRR = 200, =

1K 4K

V1 = 200 μV,

Then

V2 = 140 μV

Vo = + 30V

A dm ∵ Vsat = 12V, so Vo can’t be 30 V

now CMRR =

A cm

So, output Vo = +12V.

∴ Adm = CMRR × Acm By KCL at V–

= 200 × 20 O − V− V − − 12

=

∴ Adm = 4000 1K 4K

v + v2 – 4V– = V– – 12

now Vcm = 1

2 5V– = 12

200 + 140 V–=2.4V

=

2

6.

Vcm = 170 μV

Vdm = V1 – V2

= 200 – 140 = 60 μV

V0 = 243.4 mV

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second order and it is having a cutoff Positive terminal of op-amp will be having

Emitter will have Vcc - Vz. Therefore,

1

f = voltage across emitter will be Vcc - (Vcc -

2 R1C1R2C2

Vz) = Vz

Since,

VZ 5.6

IE = = = 1.12 mA

R1 = R2 = 22K R2 5

C1 = C2 330 PF 100

I0 = I = (1.12)

1 1 + E 101

f =

2 R1R1C1C1 I0 = 1.109 mA

VBC = 0.2 V (Given)

1

= Now simply apply KVL across transistor i.e.

2R1C1

Vcc - Vz - VEB (ON) - VBC - V0= 0

1

= V0= 20 –VZ – 0.6 - 0.2

2 22k 330PF

= 20 – 5.6 – 0.6 - 0.2

f = 21.9 KHz

or V0 = 13.6 V

7. Then,

RL = = = 12.26 k

I0 1.109

Vo' = −ve (Vo’ is more negative than V_)

10. A.

So, diode D1 is ON & D2 is OFF This is Wien-bridge oscillator. The ratio

Equivalent circuit will be R 2 2.1k

= = 2.1 is greater than 2.

R1 1k

8. C.

Let Vo=+ve

1 1

VUTP =V0(R2/R1+R2) =1/10 =0.1 Frequency = 1 103 =

2RC 2(1k)C

VLTP =-V0(R2/R1+R2) = -0.1

1

C= F

2

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IB = = =

v+ = 5V = v– = vE + 1 100 + 1 101

The input current to the op-amp is zero. VB = 4+0.7 = 4.7 V

i+15V = iZ + iC = iZ + FiE V0 − 4.7 0.5 V0 − 4.7

IB = =

15 − 5 60 5 100 101 100

+ = 49.4 mA

47k 61 100

0.5 = V0 – 4.7

12. C. V0 = 4.7 + 0.5

Rf V0 = 5.2 V

Gain A v = −

R1 14. B.

−R f

R1 =

AV R

V0 = 1 + V+

1 1

So, R1 will be sC

Av

V0 = (1 + sCR)

1

So, for Av = -10 R+

sC

R1 will be maximum

V0

−R f = sCR

R1 = Vin

−10

dVin

R 1 106 V0 (t) = RC

= f = = 105 dt

10 10

∴ Circuit is a non-inverting differentiator.

R1 = 100 k Ω

15. C.

13.

The output of op-amp is connected to

B-E junction is forward biased as V0 it

differentiator. The output of differentiator

positive

is connected to diode. So, the circuit

generates positive pulse. It is a zero-

crossing detector.

16. A.

A. Since, there is no feedback in the

circuit hence, it will act as comparator

∴ V+ = V– = 4V circuit

4 − ( −12 ) B. Given circuit is

IE = = 0.5 A

32

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V0 −Z

∴ Voltage gain = =

Vi R

Here

1 R

Z=R =

sC 1 + sRC

Hence,

V0 [R / 1 + sRC] Applying KVL at input side

=

Vi R ∴ –V2 + iin × R1 + iin × R1 + V1 = 0

V0 1 ∴ (V1 – V2) = – iin × 2R1

= −

Vi 1 + sRC V2 − V1

iin = (i)

From above equation: 2 R1

= −1

Vi s −0 Appling KVL across two OP-amps

=0

Vi s − −2R2

iout = iin (iii)

R3

Since, at high frequency gain of op-amp =

0

And gain exists at low frequency. Hence, it From equn (i), (ii) & (iii)

is low pass filter. R2 ZL

V0 =

R1R3 1

( V − V2 )

C. At low frequency:

At low frequency, capacitor = open circuit 18. B.

Draw circuit again

V0

=0

Vi

At high frequency

At high frequency capacitor = short circuit

Va = i O R L

For op – amp (2), virtual short is applicable

as negative feedback is there

So, V+ = V– = VK = iORL

Now, in the input loop of op – amp 1

V0

=1

Vi virtual short is applicable so, current in the

input loop is

Therefore, it is high pass filter.

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vin − V+ + V− v 11 11

i = = in = =

20K 20K 11 + 1 12

A2 = = =

V+ = Vk – i’ 10kΩ v2 v2 12 12

vin 121

= ioRL − 10K

20K A1 − A2 −10 − 12

Ad = =

vin 2 2

V+ = ioRL − = v−

2 = – 10.04166

Vb = V_+[-i' 10K] ACM = A1 + A2

vin V 121

= ioRL − − in (10 K) = −10 +

2 20 k 12

Vb = ioRL – vin = 0.08333

Since io is flowing through Rf& RL −10 − 04166

CMRR =

So, Vb = io (Rf + RL) 0.0833

⇒ioRL – vin = ioRf + ioRL = 120.49

vin CMRR (dB) = 20 log10 120.99

io = −

Rf = 41.61 dB

19. 20.

CMRR =

ACM And

A1 − A2 It is given that output changes from

Ad =

2 0 → 8V

ACM = A1 + A2 When input is greater than 3V and output

Where A1 = gain due to input 1 changes from 5V → 0

A2 = gain due to input 2

when input is lower than 2v

v −10K Investing

now, A1 = 0 = = −10 so, for capacitor, for vo = σv

v1 1 configuaration

VC(t) = VC(∞) – (VC(∞) – VC(0)) e–t/RC

v

A2 = 0 Where VC (∞) = 8V

v2

VC (o) = 2V

vov

= 2 VC (t) = 3V

v2 v2

3 = 5 – e–t/RC

v0 R Non −investing 2 = 3 e–t/RC

= 1 + 2

v2 R1 configration

2

T1 = −RC ln

= 1 + 10 = 11 3

= (voltage _ devided)

v2 R 4 + R3 Now, for Vo = ov,

VC (∞) = 0

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VC (o) = 3V −

t

1K 0.01F

vc (+) = 20 − 20 e

VC (t) = 2V

t

− −5

= 20 1 − e 10

Now, output will move from +5V to –5V

when V– (inverting terminal will exceed the

V+)

And V+ = 4.54V

2 = O + 3 e–t/RC

V– = vc (t)

2

T2 = −RC ln

3 t

− −5

so, 4.54 = 20 1 − e 10

T2 = 4.05 msec

Time period = T = T1 + T2 = 8.1 msec

t

21. D. 4.54 − −5

1− = e 10

20

Initially switch is closed and short – circuit

t

so charge at capacitor is zero + = +0.257

10−5

⇒ when switch is closed, then at inverting

t = 2.57 s

terminal, we have ground which basically

will give high positive output (assuming) 22. A.

So, vout = 5V (as the Zener breakdown will Now redraw ckt

occur & give high output)

100k 10

now, V+ = vout = vout

100k + 10k 11

10

so, initially V+ = 5V

11

= 4.54 V

Now, if we look the input side, then

v1

i1 =

R1

By virtual Ground

v2

i2 =

R2

so, here VC (∞) = 20V

Since current in transistor is

VC (0) = OV

v

And I = I0 exp BE

VT

−t

eRC

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i1 = I0 exp BE1 as both are

VT modification

So, identical so

vBE2 Now, draw the ckt again

i2 = I0 exp I = Io2 = Io

VT o1

i

vBE1 = ln 1 VT = 0 − vE1

Io

i

vBE2 = VT ln 2 = o − vE2

Io

−333k 333k 333k

now, vo = vE2 + 1+ V

20k (333 + 20)k 20k E2

= vE2 + v

20 353 20 E1

−333 333 So, vout = AOL (V+ – V–)

= vE2 + v

20 20 E1 vout = – AOL V–

now, apply KCL at node (a)

= 16.65 (VE1 - VE2) vin − v − v v + AoL v −

= − + −

I I R Rin 1

= 16.65 VT ln o − VT ln o sc

i1 i2

vin V v

I i = − + − + v − (1 + AoL ) sc

= 16.65 × VT ln o 2 R Rn R

i1 Io

vin 1 1

i = + + (1 + AoL ) sc v−

= 16.65 × 0.026 ln 2 R Rin R

i2

vin

v R v− =

= 0.4329 ln 2 1 1 1

R + + (1 + AoL ) sc

R2 v1 Rin R

v R vout = – AOL V–

= 0.4329 ln 2 1

v1 R2 −AoL vin

vout =

Now change loge base to log 10 base 1 1

R + + (1 + Aol)sc

v R R

in R

log10 2 1

= 0.4329 v1 R2 vout Aol

log10 (e) =

vin R

+ 1 + R(1 + Aol)sc

v R R

in

log10 2 1

v1 R2 So, pole is at

23. B. R

+ 1 + R(1 + Aol) sc = 0

Now, assume that if it is ideal op – amp, Rin

then gain will be

R

1 − 1 +

− Rin

SC = − 1 s=

R SCR RC(1 + Aol)

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24. D. 26. C.

Since the op–amp has negative feedback, Step 1: Consider op-amp (1) [A1]

so, virtual ground concept can be used Vi

V0 = − …(1)

here sCR

So, V+ = V– = Vsource = 0 Step 2: Consider op-amp (2) [A2] (VA=Vx)

2RV0 V

VA = Vx = = 0 …(2)

2R + 2R 2

KCL at non-inverting input terminal of A2:

V0 − Vx V − V0

= x + sCVx …(3)

2R 2R

V0 V0 V

V0 − + i

2 = 2 sCR + sCV0 …(4)

VS − (−10V) 2R 2R 2

ID =

10

V0 V V Vi sCV0

0 + 10 − 0 = 0 + 2

+ …(5)

= = 1A 2R 4R 4R 2sCR 2

10

1 1 1 sC Vi

ID = kn (VGS – Vth)2 V0 − − − = …(6)

2 R 4 R 4 R 2 2sCR 2

1 = 0.25 (VG – 0 – 2.5)2

4 = (VG – 2.5)2 sC Vi

V0 − = …(7)

± 2 = VG – 2.5 2 2sCR2

VG = 0.5 , 4.5 V0 1

∴ =− 2 2 2

VG = 4.5 V (for gate voltage greater than Vi s CR

threshold voltage)

27.

Now, for saturation

VDS> VGS – Vth

VDD – 0 > VG – 0 – 2.5V

VDD> 4.5 – 2.5

VDD 2V

So minimum VDD is 2V

25. C

From the concept of virtual ground Step 1: KCL at node V2.

V+= V-

Vi V

V- = IoRE VsC

i 1 + = −V0SCf − 0

R1 Rf

I0 1 1

= = 1 + sC1R1 1 + SCfR f

V − RE 1.5k Vi = −V0

R1 Rf

∵ V+ = V (input current of op Amp is zero)

I0 I 1 V0 R 1 + sC1R1

= 0 = 10−3 = 0.66 mA/V = − f

V− V 1.5 V1 R f 1 + sCfR f

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1 30. B.

+ R1C1

V0 R j Case I:

=− f

V1 Ri 1

+ R f Cf

j

V0 −R f R1C1 −C1

= =

Vi R1 R f Cf Cf

V0 C 1F

= 1 = =5

Vi Cf 0.2F When Vin > 0 (inverting terminal > non-

inverting terminal)

V0

=5 So, D1 = ON, D2 = OFF

Vi

Current through

28. Hence, V0 = 0V

3k Case II:

V0 = 1 + 2 sin t

1k

V0 = 8sinωt

SR = 2πfmaxV0,MAX

2V

= 2fmax (8)

10−6

When Vi < 0, (inverting terminal < non-

→ fmax = 39.8 kHz

inverting terminal)

29. B. D1 = OFF and D2 = ON

1 −R

Vin VA = Vin = −Vin

R

V+ = V− sC = Vin

1 1 + sCR

R+ R

sC V0 = 1 + VA = (2) ( −Vin )

R

By KCL:

V0 = -2 Vin

Vin Vin V0

Vin − − V0 Hence, = Slope = −2

1 + SCR = 1 + SCR Vin

R 1

sC Therefore, Relation between V0 and Vin i.e.

= − V0 (sCR)

1 + sCR 1 + SCR

⇒ V0(sCR) = 0

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31. C. 34. D.

−10 k 10 k VoutputA 2

V0 = Voutput A1 + 1 +

10 k 10 k 2

50k

= − 1 + [3 + 40m sin t]

1k / 2

In ideal op-amp

50k

+ 1 + [3 − 40 m sin t]

1k V + = V-

2

So, V+ = V- = Vs

By applying KCL at inverting terminal,

= – 8.08 sinωt (V)

−

32. B. V − − 0 V − V0 (s)

+ =0

1/sC R

From the transfer characteristics shown in

or (1 + RCs) Vs = V0(s)

figure B.

At non-inverting terminal

+Vsat = 12V Vs − V0 (s)

Is =

Upper threshold voltage R

or Is = -[RCS/R]Vs

R1

= VuT =

R1 + R2

( +Vszt ) = +4V or Is = - jωCVs

So,

R1 4V 1

= = Is = 2f 10 10−6 10

R1 + R 2 12V 3

And ∠Is = -90

∴ R2 = 2R1 = 10 k Ω

Thus, the current from the source is:

33. A.

Is = 10π mA, lagging by 90°

1 35.

For low frequency Zc =

jC

B-E junction is forward biased as V0 it

−R f positive

So, output. V0 = V

Ri i

1

Zc = 0

jC

output , V0 0

∴ V+ = V– = 4V

So, it is a low pass filter

4 − (−12)

IE = = 0.5A

32

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1

= 2Vi

1 + sRC

Using equation (1) & (2),

2Vi

Vo = − Vi +

1 + jRC

Vo 1 − jRC

=

IE 0.5 0.5

Vi 1 + jRC

IB = = =

+ 1 100 + 1 101 Taking magnitude

VB = 4+0.7 = 4.7 V Vo 1 + (RC)2

= =1

V0 − 4.7 0.5 V0 − 4.7 Vi 1 + (RC)2

IB = =

100 101 100

So, |Vo| = |Vi|

0.5 = V0 – 4.7

So, option A is correct.

V0 = 4.7 + 0.5

As |Vo| = |Vi|

V0 = 5.2 V

So, |AV| = 1

36. A, D

Hence, all Pass filter.

Given V0 = AV1 + BV2

So, option C is correct.

−100k

V02 = V2 38. A, C, D

10k

Slew rate is defined as the maximum rate

V02 = –10V2

of change of an op amp’s output voltage

100K 99K

V01 = 1 + (V1 ) and is given units of volts per microsecond

10K 110K

(V/µsec).

V01 = 9.9V1

So, option A, C are correct

So, V0 = 9.9V1 – 10V2

For the given curve,

A = 9.9 dVo change in voltage

So Slew rate ( S.R.) = =

B = −10 dt change in time

37. A, C 9 − (−9)

= = 18 V/μsec

V0 = V01 + V02 1

39. A, C

RF

V01 = − V Consider Node ‘X’ at inverting input,

R1 i

Applying KCL at Node X

= ( −R/R ) (V)

i = −Vi ...(1)

Vx − Vin Vx − 2

+ =0

R 10k 20k

V02 = 1 + F (Vi )

R1 2(Vx − Vin ) Vx − 2

+ =0

1/sC 20k 20k

= 2Vi

R + 1/sC 2Vx – 2Vin + Vx – 2 = 0

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3Vx – 2Vin = 2 Rf

= 10

2Vin + 2 R1

Vx =

3

Rf

If Vo = +10 V R1 =

10

5k

Vref = Vo At 3 dB down,

5k + 20k

1 A = 20 – 3 = 17 dB

= 10 =2V

5 10

20log10 = 17 dB

If Vo = –10 V 4

1 + [10 R f 0.01 10−6 ]2

5k

Vref = Vo R f = 10 k

5k + 20k

R1 = 1 k

1

= −10 = −2 V

5 41. A, B

For Vo = –Vsat AOL = 104

Vx > 2 V

Af = 10 ⇒ R2/R1 = ?

2 + 2Vin 6−2

2 VUTP = Vin = 2V Vo = AOL Vd

3 2

So, option A is correct. 4 V0 R1

Vo = 104(V+ – V–) = 10 Vs −

When vin > 2 V R1 + R 2

VUTP = 2 V

Vo 104 (R1 + R 2 )

For Vx < –2 V = = 10 ( A f = 10)

Vs (1 + 104 ).(R1 + R 2 )

Vo = +Vsat

2 + 2Vin (1 + 104)R1 + R2 = 103(R1 + R2)

−2

3 (1 + 104 – 103)R1 = (103 – 1)R2

6−2 R 2 1 + 104 − 103

VLTP = Vin − = −4 V

2 = = 9.01

R1 103 − 1

So, option B is incorrect.

VH = VUTP – VLTP = 2 – (–4) = 6 V So if R1 = 1 kΩ

40. A, D So options A and B are correct only.

Peak gain 20 dB

42. A & B

at ω =10, 000 rad/sec

We know for the given wein Bridge

Gain is 3 dB down

oscillator

R f /R1

A(dB) = 20log10 R2

14(R f Cf )2 3

R1

R

20 = 20log10 f R2

2 R2 2R1

R1 R1

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43. A & C 1

Vo = − V dt

Circuit 1 is differentiator for this RC A

L dvi 1 (−0.75 sin50t)

V01 = VA = − Vo = −

R dt 5 5 10 −3

50

VA = −0.75 cos 50t Vo = 15 sin50t

Slew Rate unit is V/μsec

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Chapter

13 Oscillators

1. Assertion (A): All practical RC phase shift 3. Which of the following is/are used for

oscillators generate sinusoidal oscillation generation for radio frequency.

with some amount of amplitude distortion, I. wein–Bridge oscillator

which cannot be avoided. II. LC oscillator

Reason (R): The amplitude distortion of a III. RC oscillator

sinusoidal oscillator is controlled by the IV. crystal oscillator

onset of non-linearity of the amplifying A. I and III only

device. B. II, III and IV only

A. Both A and R are true and R is the C. II and IV only

correct explanation of A D. I, II, III and IV

B. Both A and R are true but R is NOT the 4. Consider the given phase – shift oscillator

correct explanation of A circuit operating at frequency, f = 80 KHz.

C. A is true but R is false The value of resistance RF is _____ kΩ

D. A is false but R is true.

2. The oscillator circuit shown in the figure is:

type of oscillator, its frequency and

A. Hartley oscillator with foscillation = 79.6 condition for sustained oscillations?

MHz

B. Colpitts oscillator with foscillation = 50.3

MHz

C. Hartley oscillator with foscillation = 159.2

MHz

D. Colpitts oscillator with foscillation = 159.2

MHz

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weinbridge , = 3 + 3

A. 2 R1R2C3C4 R1 C4 R2

Find the value of resistor Rx (in kΩ) for

oscillation

sustained oscillations.(Let consider the

1 R C R

Weinbridge , 2 = 3 + 4 circuit is at resonance)

B. 2 R3R 4C3C4 R1 C4 R 3

oscillation

1 R2 C3 R 4

phaseshift , = +

C. 2 R3R 4C3C4 R1 C4 R3

oscillation

wein - bridge

D. 1 R2 C R

oscillation , = 3 + 3

2 R3R 4C3C4 R1 C4 R 4

1 μH, C1 = 1 nF, C2 = 1 nF, R = 4 kΩ. 9. Find the relation between R1 and R2 for

below: C. R2 = 6R1 D. R2 = 7R1

10. Design the RC elements of a Wein bridge

oscillator as in below figure for operation at

f0 = 10 kHz

R2

For sustained oscillations, the value of

R1

A. 1 B. 2

A. 50 kΩ, 159 pF B. 100 kΩ, 159 pF

C. 3 D. 4

C. 150 kΩ, 200 pF D. 20 kΩ, 200 pF

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11. Consider the following Colpitts’s Oscillator 12. Consider the oscillator as shown in figure

generating 40 kHz frequency. below

1

A. Output frequency is

2 CeqL eq 1

A. Frequency of oscillation is

LC

1

B. Output frequency is B. To sustain oscillations Aβ should be 1.

L eqCeq

C. Rx = 9 kΩ to sustain oscillation.

C. If output Frequency is 40 kHz and C1 =

D. Rx cannot be computed for given

10C2, then C2 = 74 pF

conditions.

D. If output Frequency is 40 kHz and C1 =

10C2 then C2 = 174 pF

ANSWER

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SOLUTION

1. A. 5. B.

Both A and R are correct and R is the It’s a wein – bridge oscillator

correct explanation of A Now,

2. B.

The tank circuit is having two capacitors

and one inductor. So, it is Colpitts

oscillator and frequency is:

1

f =

2 LCeq

C1C2 22

Ceq = = = 1pF = 1pF

C1 + C2 2 + 2

It’s a non – investing configuration, so

1 1 109

f = =

2 10 R

2 10 10−6 10−12 A = 1 + 2 ( forward gain )

R1

f = 50.3 MHz

z3

3. C. = ( feedback gain )

z4 + z3

Wein–Bridge oscillator and RC oscillator

are used for generation of audio frequency 1

where z3 = R 3

sc3

while LC – oscillator and crystal oscillator

are used for generation of radio frequency 1

R3

sc3

4. =

1

Since it is a phase shift oscillator we know R3 +

sc3

that frequency of oscillation

R3

1 z3 =

f = 1 + sc3R 3

2 6RC

1

R z4 = R 4 +

and F = 29 sc4

R

1 + sc4R 4

It is given that =

sc4

f = 80 KHz

R3

& c = 100 pF

1 + sc3R 3

1 =

so, 80 KHz = R3 1 + sc4R 4

2 6 R 100 pF +

1 + sc3R3 sc4

R = 8.12 kΩ

sc4R 3

R =

Now, f = 29 sc4R 3 + (1 + sc3R 3 ) (1 + sc4R 4 )

R

sc4R3

So, Rf = 29 × (8.12k) =

1 + sc4R3sc3R3 + sc4R 4 + s2c3R3C4R 4

= 236 kΩ

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Now, for oscillation Aβ = 1 7. B.

The given circuit is

R2 sc4R3 =1

1 +

R

( 2

1 1 + s c4R3 + c3R3 + C4R 4 + s c3R3c4R 4 )

image part equals to ‘0’

R2 jwc4R 3

1 + =1

R1 1 − w2 ( C3R 3C4R 4 ) + jw (C4R 3 + C3R 3 ) + C4R 4

R2 −wR3c4

1 +

=1 Using KCL at the non inverting terminal,

( 3 3 4 4 4)

R1 i 1 − w2C R c R − ( c R + C R + C R )

3 3 3 4 4

V0 − Vi V V − V+

(1) = i + i

1 R R

Imaginary sC

1 – w 2 R 3 C 3 R 4 C4 = 0

2 V

Or V0 (sC) = Vi sC + − + -------(1)

1 R R

w=

R3C3R 4C4

Applying KCL at non inverting terminal, we

1 get

f =

2 R 3C3R 4C4

V+ ( V+ − Vi )

+ =0

Now, put this value of w 1 R

sC

in eqn (1) then

1 V

R2 wR3C4 or V+ sC + = i

1 + =1 R R

R1 w (C4R3 + C3 + C4R 4 )

so, Vi = V+(1 + sRC) …. (1)

R C R + C3R3 + C4R 4

1+ 2 = 4 3 V0(sRC) = V+(1 + sRC) (2 + sRC) - V+

R1 C4R3

= V+[(1 + sRC) (2 + sRC) - 1] … (2)

R C R

1+ 2 =1+ 3 + 4 Therefore, from equations (1) and (2), we

R1 C4 R 3

get the transfer function of the first

R2 C3 R 4

= + network as:

R1 C4 R 3

R sRC

6. T(s) = 1 + 2

R1 (1 + sRC)(2 + sRC) − 1

For Colpitts oscillator, the oscillation

frequency is defined as: R sRC

= 1 + 2

R1 2 + 3sRC + s R C − 1

2 2 2

1

f0 =

2 LCeq R sRC

= 1 + 2 2 2 2

R1 s R C + 3sRC + 1

Where Ceq = C1 ll C2

C1C2 1nF 1nF R jRC

= = = 0.5 nF. or T(j) = 1 + 2

C1 + C2 1nF + 1nF

2 2 2

R1 1 − R C + 3jRC

So, we get Hence, the condition for oscillation is:

1

f0 = R jRC

2 1 0.5n 1 = 1 + 2

R1 3jRC

f0 = 7.12 MHz

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R2 11. A, D

The value of is:

R1 L = 100 mH

R2 C1 = 10C2

=2

R1 The output frequency of Colpitts’s

8. B. Oscillator is given by

1

V0 5k f0 =

Gain = A = =1+ 2 L eqCeq

Vf Rx

Given f0 = 40 kHz

β = Vf/V0 = (2k)/(3k+2k) = 2k/5k

So, 40 103 = 1

[LC = short circuit at resonance]

2 (100 10−3 )(Ceq )

For sustained oscillations:

Ceq = 0.0174 × 10–10 F

1

A=

C1C2

Ceq =

C1 + C2

5k 5k 5k 5 10

∴ 1+ = → = − 1 Rx = k as C1 = 10C2

R x 2k Rx 2 3

So, C2 = 0.1C1

R x = 3.33 k

So, 0.0174 10−16 = C1C2 =

(10C2 )(C2 )

C1 + C2 (10C2 ) + C2

9. D.

C2 = 174 pF

−R2 V

A= = 0

R1 Vf So, option D is correct.

12. B, C

Vf 1

= = 180

V0 7 Redrawing the oscillator circuit

Aβ = 1 < 360°

R2 1

180 180 = 1 360

R1 7 For frequency of oscillations the

admittance of circuit should be only real.

R2 = 7R1

So Img part = 0

10. B.

1 1

Y= + + jC

Using equal values of R and C, we can (2k||2k ) jL

select R = 100kΩ and calculate the 1

Img part : j C − =0

required value of C using: L

1 1

f0 = C =

2RC L

1

C=

1

=

1 =

( )(

2f0R 6.28 10 103 100 103 ) LC

1

10 −9

f =

= 2 LC

6.28

= 159pF

Therefore, option A is incorrect.

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For amplifier to sustain oscillators Vf 2k || 2k

= =

Aβ =1 Vout (2k || 2k) + R x + 100

Given A = 10 For Aβ = 1

For β, redrawing circuit at oscillation

1k

frequency 10 =1

1k + R x + 100

10k = 1k + Rx + 100

Rx = 8.9 = 9 kΩ

So options B and C are correct

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Chapter

555 Timer

14

43.2

So, 43.2kW = = 12.28 Ton

& Waveform Generators3.5167

from irregular shaped pulses: circuit shown below. If the monostable

A. When it is given as input to a multivibrator with a 100μs output pulse

monostable multivibrator. then the value of R (in KΩ).

B. When it is given as triggering signal to

a bistable multivibrator.

C. When it is used as input to a schmitt

trigger.

D. When it is used as input to a pulse

transformer.

2. A 555 timer is configured to run in astable

mode. Determine the duty cycle of the

output.

555 if RA = 2kΩ, RB = 4 kΩ and C = 0.1 μf

calculate the frequency of output waveform

is ______ KHz

6. The output voltage Vo(t) for the circuit

below is

A . 55.12% B. 72.8%

C. 48.4% D. 32.4%

3. For 555 astable multivibrators, if C = 0.01

μF, RA = 10 kΩ, RB = 50 kΩ, the frequency A. e–t/10 u(t) V

and the duty cycle will be nearly B. –e–t/10 u(t) V

A. 1.6 kHz and 54.5% C. e–t/1.6 u(t) V

B. 1.3 kHz and 54.5% D. – e–t/1.6 u(t) V

C. 1.6 KHz and 46.5%

D. 1.3 kHz and 46.5%

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B. 4V to 6V

C. 2.6V to 4.3V

D. 2.4V to 6V

MSQs:

9. For the given figure, having RA = 6 kΩ, RB

C. +5 V D. -5 V correct option(s)?

the astable multivibrator given

B. tlow = 0.48 m seec.

C. Free running frequency = 5570.69 kHz

D. Duty cycle = 73.20%

ANSWER

1. C 2. A 3. B 4. 6.06 5. D 6. A 7. D 8. D 9. B,D

SOLUTION

1. C. 3. B.

Pulses of definite width can be obtained 1

f =

from irregular shaped pulses when it is 0.69 (R A + 2RB ) C

used as input to a schmitt trigger.

1

2. A. =

0.69 (10 + 2 50) 103 0.01 10−6

TON R + R2

Duty cycle = = 1

T R1 + 2 R 2 f = 1.3 KHz

1.3 + 5.7 R A + RB

= & % duty cycle = 100

1.3 + 2 5.7 R A + 2 RB

= 55.12%

146

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60 V0(∞) = 0 (∵capacitor would act as open

= 100 = 60%

100 circuit)

% duty cycle 54.5% Now, time constant of the circuit would be

∴ Option B

= CR = 8 10−3(1000 + 250) = 10s

4.

So, the expansion for V(t)

Since it is a monostable then time period is

equal to ( )

V(t) = V0 () + V0 O+ − V0 () e−t /

T = RC ln3

⇒ V(t) = 0 + (1 – 0) e–t/10

T = 1.1 × R × C

⇒ V(t) = e–t/10 u(t) V

Here, it is given that

7. D.

T = 100 μsec

C = 15 nF

So, 100 T = 1.1 RC

T

R=

1.1 C

100 sec

=

1.1 15 nF

Vp = Vn (due to virtual short)

= 6.06 kΩ

Also Vn – Vo = (0.3mA)*(10K) …………..(1)

5. D.

1 Vo x 20K 2Vo

f0 = Vp = = = Vn

0.69 (R A + 2RB ) C 30K + 20K 5

f0 =

0.69(2 + 2 9) 103 0.1 10−6 2Vo

– Vo = 3

5

∴ fo = 1.45 KHz

6. A. -3Vo = 15

follower circuit. 8. D.

Here, Vo = V– = V+ 2

Vthreshold = 2/3 Vcc = 12 = 8V

So, the simplified circuit becomes 3

1 1

VTrigger = VCC = 12 = 4V

3 3

12 − 4

Vc = Vtrigger – (I. 1K) = 4 − 1k

5k

= 2.4 V

=8− 2k = 6V

250 1000 4k

= 5 10−3 = 1V

250 + 1000 Hence, Vc range is 2.4V to 6V.

147

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9. B&D 1.45 103

f=

For the given 555 timer 2.6

tHigh = 0.69 (RA + RB)C f = 557.69 Hz

= 0.69(6 + 3.5)(0.2) ms ton tHigh

D= =

tHigh = 1.31 m sec. ton + t off tHiigh + tlow

tlow = 0.69 RBC = 0.69 × 3.5 × 0.2 ms

1.31

= 0.483 m sec.

D= 73.18%

1.31 + 0.48

1.45 1.45

f =

(R A + 2R B )C (6 + 2 3.5) 0.2 10−3

148

www.gradeup.co

149

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