Service Manual: Internal Use Only

Internal Use Only
Service Manual
LG-A395
Date: April, 2013 / Issue 1.0

Table Of Contents
1. INTRODUCTION�� 3 4.11 Receiver Trouble�� 81
1.1 Purpose��3 4.12 Microphone Trouble�� 83
1.2 Regulatory Information��3 4.13 SIM Card Interface Trouble�� 85
1.3 Abbreviations��5 4.14 KEY backlight Trouble�� 97
4.15 Micro SD Trouble�� 99
2. PERFORMANCE�� 7
4.16 Bluetooth Trouble��102
2.1 H/W Features��7
4.17 FM Radio Trouble��106
2.2 Technical Specification��9
5. DOWNLOAD�� 109
3. TECHNICAL BRIEF�� 14
3.1 Digital Main Processor�� 14 6. BLOCK DIAGRAM�� 129
3.2 Power Management�� 23
7. CIRCUIT DIAGRAM�� 135
3.3 FEM with integrated Power Amplifier Module (RF7182)�� 27
3.4 Clocks�� 29 8. BGA PIN MAP�� 139
3.5 RFSYS of MT6253 (U101)�� 31
9. PCB LAYOUT�� 141
3.6 MEMORY(H9DA1GH25HBMMMR, U100 )�� 33
3.7 SIM Card Interface�� 37 10. ENGINEERING MODE�� 143
3.8 Micro-SD Card Interface�� 41
11. CALIBRATION�� 145
3.9 LCD Interface�� 42
3.10 Battery Charger Interface�� 44 12. HIDDEN MENU�� 165
3.11 Keypad Interface�� 45
13. EXPLODED VIEW & REPLACEMENT PART LIST �� 170
3.12 Audio Front-End�� 47
13.1 EXPLODED VIEW��170
3.13 Camera Interface�� 49
13.2 Replacement Parts��171
3.14 KEY BACLKLIGHT LED Interfac�� 51
13.3 Accessory��185
3.15 Vibrator Interface�� 52
4. TROUBLE SHOOTING�� 53
4.1 RF Component�� 53
4.2 RX Trouble�� 54
4.3 TX Trouble�� 58
4.4 Power On Trouble�� 62
4.5 Charging Trouble�� 64
4.6 Vibrator Trouble�� 67
4.7 LCD Trouble�� 69
4.8 Camera Trouble�� 73
4.9 Speaker Trouble�� 76
4.10 Earphone Trouble�� 78
LGE Internal Use Only -2- Copyright © 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
1. INTRODUCTION
1. INTRODUCTION
1. INTRODUCTION
1.1 Purpose
This manual provides the information necessary to repair, calibration, description and download the
features of this model.
1.2 Regulatory Information

A. Security
Toll fraud, the unauthorized use of telecommunications system by an unauthorized part (for example,
persons other than your company’s employees, agents, subcontractors, or person working on your
company’s behalf) can result in substantial additional charges for your telecommunications services.
System users are responsible for the security of own system. There are may be risks of toll fraud
associated with your telecommunications system. System users are responsible for programming and
configuring the equipment to prevent unauthorized use. The manufacturer does not warrant that this
product is immune from the above case but will prevent unauthorized use of common-carrier
telecommunication service of facilities accessed through or connected to it.
The manufacturer will not be responsible for any charges that result from such unauthorized use.
B. Incidence of Harm
If a telephone company determines that the equipment provided to customer is faulty and possibly
causing harm or interruption in service to the telephone network, it should disconnect telephone service
until repair can be done. A telephone company may temporarily disconnect service as long as repair is
not done.
C. Changes in Service
A local telephone company may make changes in its communications facilities or procedure. If these
changes could reasonably be expected to affect the use of the this phone or compatibility with the
network, the telephone company is required to give advanced written notice to the user, allowing the
user to take appropriate steps to maintain telephone service.
D. Maintenance Limitations
Maintenance limitations on this model must be performed only by the manufacturer or its authorized
agent. The user may not make any changes and/or repairs expect as specifically noted in this manual.
Therefore, note that unauthorized alternations or repair may affect the regulatory status of the system
and may void any remaining warranty.
LGE Internal Use Only Copyright © 2007 LG Electronics. Inc. All right reserved.
4 / 131
1. INTRODUCTION
1. INTRODUCTION
E. Notice of Radiated Emissions
This model complies with rules regarding radiation and radio frequency emission as defined by local
regulatory agencies. In accordance with these agencies, you may be required to provide information
such as the following to the end user.
F. Pictures
The pictures in this manual are for illustrative purposes only; your actual hardware may look slightly
different.
G. Interference and Attenuation
Phone may interfere with sensitive laboratory equipment, medical equipment, etc.Interference from
unsuppressed engines or electric motors may cause problems.
H. Electrostatic Sensitive Devices
ATTENTION
Boards, which contain Electrostatic Sensitive Device (ESD), are indicated
by the sign. Following information is ESD handling:
• Service personnel should ground themselves by using a wrist strap when exchange system boards.
• When repairs are made to a system board, they should spread the floor with anti-static mat
which is also grounded.
• Use a suitable, grounded soldering iron.
• Keep sensitive parts in these protective packages until these are used.
• When returning system boards or parts like EEPROM to the factory, use the protective
package as described.
5 / 131
1. INTRODUCTION
1. INTRODUCTION
1.3 Abbreviations
For the purposes of this manual, following abbreviations apply:
APC Automatic Power Control
BB Baseband
BER Bit Error Ratio
CC-CV Constant Current – Constant Voltage
DAC Digital to Analog Converter
DCS Digital Communication System
dBm dB relative to 1 milli watt
DSP Digital Signal Processing
EEPROM Electrical Erasable Programmable Read-Only Memory
ESD Electrostatic Discharge
FPCB Flexible Printed Circuit Board
GMSK Gaussian Minimum Shift Keying
GPIB General Purpose Interface Bus
GSM Global System for Mobile Communications
IPUI International Portable User Identity
IF Intermediate Frequency
LCD Liquid Crystal Display
LDO Low Drop Output
LED Light Emitting Diode
OPLL Offset Phase Locked Loop
6 / 131
1. INTRODUCTION
1. INTRODUCTION
PAM Power Amplifier Module
PCB Printed Circuit Board
PGA Programmable Gain Amplifier
PLL Phase Locked Loop
PSTN Public Switched Telephone Network
RF Radio Frequency
RLR Receiving Loudness Rating
RMS Root Mean Square
RTC Real Time Clock
SAW Surface Acoustic Wave
SIM Subscriber Identity Module
SLR Sending Loudness Rating
SRAM Static Random Access Memory
PSRAM Pseudo SRAM
STMR Side Tone Masking Rating
TA Travel Adapter
TDD Time Division Duplex
TDMA Time Division Multiple Access
UART Universal Asynchronous Receiver/Transmitter
VCO Voltage Controlled Oscillator
VCTCXO Voltage Control Temperature Compensated Crystal Oscillator
WAP Wireless Application Protocol
7 / 131
2. PERFORMANCE
2. PERFORMANCE
2. SYSTEM SPECIFICATION
2.1 H/W
H/W Features
Features
Item Feature Comment
Standard Battery Lithium Ion, 3.7V 1500mAh
Stand by TIME >993 hr., Min.@PP9
Stand by time >1145 hr., Min.@PP5
>8.0hr., Min.@GSM900, PL=5

>22.0 hr., Min.@GSM900, PL=13
Talk time
>11 hr., Min.@PCS, PL=0
>27 hr., Min.@PCS, PL=9
Charging time Approx. 3 hours 30 min.
RX Sensitivity GSM, EGSM: -109dBm, DCS: -109dBm
GSM, EGSM: 32.3dBm(Level 5),

TX output power
DCS , PCS: 29.5dBm(Level 0)
GPRS compatibility Class 10
SIM card type 3V Small
Display MAIN : TFT 320 × 240(QVGA) pixel 262K Color
KEY TOTAL 22EA

Hard icons. Key Pad
Status Indicator Numeric(12EA : 0 ~ 9, #, *) Navigation Key OK Key(5EA)
Menu Key, Clear Key, Send Key, End Key,
SIM Switch Key(5EA)
ANT Internal
EAR Phone Jack Yes(3.5Ø)
PC Synchronization Yes
Speech coding EFR/FR/HR
Data and Fax Yes
Vibrator Yes
Loud Speaker Yes
Voice Recoding Yes
Microphone Yes
8 / 131
2. PERFORMANCE
Item Feature Comment
Speaker/Receiver 18 x 10 (Speaker & Receiver Dual Mode Assembly)
Travel Adapter Yes
MIDI SW MIDI (Mono SPK)

Camera 1.3M FF
Bluetooth / FM Radio Bluetooth version 2.1 / 76~108MHz supported
9 / 131
2. PERFORMANCE
2.2
2.2 Technical
TechnicalSpecification
Specification
Item Description Specification
GSM850 EGSM
TX: 824 ~ 849 MHz TX: 880 ~ 915MHz
RX: 869 ~ 894 MHz RX: 925 ~ 960 MHz
DCS
1 Frequency Band TX: 1710 ~ 1785 MHz
RX: 1805 ~ 1880 MHz
PCS
TX: 1850 ~ 1910 MHz
RX: 1930 ~ 1990 MHz
RMS < 5 degrees
2 Phase Error
Peak < 20 degrees
3 Frequency Error < 0.1 ppm
GSM850/EGSM
Level Power Toler. Level Power Toler.
5 33dBm ±2dB 13 17dBm ±3dB

6 31dBm ±3dB 14 15dBm ± 3dB
7 29dBm ±3dB 15 13dBm ± 3dB
8 27dBm ±3dB 16 11dBm ± 5dB
9 25dBm ±3dB 17 9dBm ± 5dB
10 23dBm ±3dB 18 7dBm ± 5dB
11 21dBm ±3dB 19 5dBm ± 5dB
12 19dBm ±3dB
4 Power Level
DCS/PCS
Level Power Toler. Level Power Toler.

0 30dBm ±2dB 8 14dBm ± 3dB
1 28dBm ±3dB 9 12dBm ± 4dB
2 26dBm ±3dB 10 10dBm ± 4dB
3 24dBm ±3dB 11 8dBm ± 4dB
4 22dBm ±3dB 12 6dBm ± 4dB
5 20dBm ±3dB 13 4dBm ± 4dB
6 18dBm ±3dB 14 2dBm ± 5dB
7 16dBm ±3dB 15 0dBm ± 5dB
10 / 131
2. PERFORMANCE
GSM850/ EGSM
Offset from Carrier (kHz). Max. dBc

100 +0.5
200 -30
250 -33
400 -60
600~ <1,200 -60
1,200~ <1,800 -60
1,800~ <3,000 -63
3,000~ <6,000 -65
Output RF Spectrum 6,000 -71

5
(due to modulation)
DCS/PCS
Offset from Carrier (kHz). Max. dBc

100 +0.5
200 -30
250 -33
400 -60
600~ <1,200 -60
1,200~ <1,800 -60
1,800~ <3,000 -65
3,000~ <6,000 -65

6,000 -73
GSM850/ EGSM
Offset from Carrier (kHz). Max. dBm

Output RF Spectrum
6 (due to switching 400 -19
transient) 600 -21
1,200 -21
1,800 -24
11 / 131
LGE Internal Use Only - 10 - Copyright © 2013 LG Electronics. Inc. All right reserved.
2. PERFORMANCE
DCS/PCS
Offset from Carrier (kHz). Max. dBm

Output RF Spectrum
400 -22
6 (due to switching
transient) 600 -24
1,200 -24
1,800 -27
7 Spurious Emissions Conduction, Emission Status
GSM850, EGSM
BER (Class II) < 2.439% @-102 dBm
8 Bit Error Ratio
DCS,PCS
BER (Class II) < 2.439% @-100 dBm
9 RX Level Report Accuracy ±3 dB
10 SLR 15±3 dB
Frequency (Hz) Max.(dB) Min.(dB)
100 -12 -
200 0 -
300 0 -12
11 Sending Response 1,000 0 -6
2,000 4 -6
3,000 4 -6
3,400 4 -9
4,000 0 -
12 RLR 2±3 dB
12 / 131
2. PERFORMANCE
Frequency (Hz) Max.(dB) Min.(dB)

100 - -
200 0 -
300 0 -11
500 0 -10
13 Receiving Response 1,000 0 -9
3,000 0 -13
3,400 0 -
4,000 0
* Mean that Adopt a straight line in between 300 Hz

and 1,000 Hz to be Max. level in the range.
14 STMR > 8 dB
15 Stability Margin > 6 dB
dB to ARL (dB) Level Ratio (dB)

-35 17.5
-30 22.5
-20 30.7
16 Distortion
-10 33.3
0 33.7
7 31.7
10 25.5
17 Side Tone Distortion Three stage distortion < 10%
System frequency
18 ≤ 2.5 ppm
(13 MHz) tolerance
19 32.768KHz tolerance ≤ 30 ppm
At least 67 dBspl under below conditions:

20 Ringer Volume 1. Ringer set as ringer.
2. Test distance set as 100 cm
13 / 131
2. PERFORMANCE
Fast Charge : Typ. 700 mA

21 Charge Current Slow Charge : Typ. 400mA
Total Charging Time : < Approx. 3 hours 30min.
Bar Number Power
4 over -91dBm±2dBm
4 -> 3 -91dBm±2dBm
3 -> 2 -99dBm±2dBm
22 Antenna Display
2 -> 1 -103dBm±2dBm
1 -> 0 -105dBm±2dBm
Battery Bar Number Voltage

3 ≥ 3.75± 0.05 V
23 Battery Indicator 3 -> 2 3.75 ± 0.05 V
2 -> 1 3.65 ± 0.05 V
1 -> 0 3.5 ± 0.05 V
≤ 3.5 ± 0.05V (Call), every 1 minute.

Low Voltage Warning
24
( Blinking Bar)
≤ 3.5 ± 0.05V (Standby), every 3 minute.
Forced shut down

25 3.35 ± 0.05V
Voltage
Sustain RTC
26 Over 1 min
without battery
Li-Ion Battery
Standard Voltage = 3.7 V
27 Battery Type
Battery full charge voltage = 4.2 V
Capacity: 1500mAh
Switching-mode charger
28 Travel Charger Input: 1000 ~ 240 V, 50/60 Hz
Output: 5.1 V, 700 mA
14 / 131
3. TECHNICAL BRIEF
3. TECHNICAL BRIEF
3.1 Digital Main Processor
Figure. 3.1.1 MT6255 Hardware Block Diagram
3. TECHNICAL BRIEF
3. TECHNICAL BRIEF
3.1.1 General
• Integrated power management unit, analog baseband and radio circuitry.
• Package:
– 12.1x11.6mm
– 0.5 mm pitch
– TFBGA 354balls, 0.5mm pitch package
3.1.2 MCU Subsystem

• ARM926EJ-STM 32-bit RISC processor
• Java hardware acceleration for fast Java-based games and applets
• High performance multi-layer AHB bus
• Operating frequency : Max. 416MHz with dynamic clock gating
• Dedicated DMA bus with 18 DMA channels
• On-chip boot ROM for Factory Flash Programming
• Watchdog timer for system crash recovery
• 4 sets of General Purpose Timer
• Circuit Switch Data coprocessor
• Division coprocessor
3.1.3 External Memory Interface

• Supports up to 2 external devices
• Supports 16-bit memory components with maximum size of up to 256M Bytes for each bank
• Supports mobile DDR SDRAM and cellular RAM
• Support Flash and SRAM/PSRAM with burst mode
• Support multi-media companion chips with 8/16 bits data width
• Configurable driving strength for memory interface
3.1.4 User Interface

• 8-row x 8-column keypad control with hardware scanner
• Support multiple key press for gaming
• Dual SIM/USIM Controller with hardware T=0/T=1 protocol control
• Real Time Clock(RTC) operating with a low quiescent current power supply
• General Purpose I/Os (GPIOs) available for auxiliary application
• 2 sets of Pulse Width Modulation(PWM) Output
• 15 external interrupt lines
• 2 external channel auxiliary 12 bit A/D converter
3.1.5 Security
• Support security key and 128bit chip random ID
16 / 131
3. TECHNICAL BRIEF
3. TECHNICAL BRIEF
3.1.6 Connectivity
• 3 UARTs with hardware flow control and supports of baud rate up to 921600 bps
• USB 2.0 high speed capability
• Multi Media Card, Secure Digital Memory Card host controller with
flexible I/O voltage power
• Supports SDIO interface for SDIO peripherals as well as WIFI connectivity
• I2S interface for Audio application
• I2C master interface for peripheral management including image sensor.
• SPI master interface for peripheral management including digital TV chip.
3.1.7 Power Management

• Li-ion battery charger
• High efficiency bulk converter for core power and memory power supply with programmable voltage scaling
• 14 LDOs for the power supply of memory card, camera, Bluetooth, RF, SIM card, and other diversified
usage
• Six Open-Drain Output Switches to Supply / control the LED
• LDO type Vibrator
• One NMOS switch to control Keypad LED
• Thermal Overload Protection
• Under voltage Lock out Protection
• Over voltage Protection
• Different levels of power down modes with sophisticated software control enables excellent power saving
performance
3.1.8 Radio Interface and Baseband Front End

• Digital PM data path with baseband front-end
• 96dB dynamic range delta-sigma ADC converts the downlink IF baseband I and Q signals to
digital baseband.
• 10-bit D/A Converter for Automatic Power Control.
• Programmable Radio RX filter with adaptive bandwidth control
• Dedicated Rx filter for FB acquisition
• 6-Pin Baseband Parallel Interface(BRI) with programmable driving strength
• support Multi-band
17 / 131
3. TECHNICAL BRIEF
3. TECHNICAL BRIEF
3.1.9 Voice and Modem CODEC
• Digital tone generation
• Voice Memo
• Noise Reduction
• Echo Suppression
• Advanced Sidetone Oscillation Reduction
• Digital sidetone generator with programmable gain
• Two programmable acoustic compensation filters
• GSM quad vocoders for adaptive multirate(AMR), enhanced full rate(EFR), full
rate(FR), and half rate(HR)
• GSM channel coding, equalization and A5/1, A5/2 and A5/3 ciphering
• GPRS GEA1, GEA2 and GEA3 ciphering
• support GSM/GPRS/EDGE-Rx modem
• Packet Switched Data With CS1/CS2/CS3/CS4 coding schemes
• GSM circuit switch Data
• GPRS/EDGE-Rx Class 12
3.1.10 Voice Interface and Voice Front End

• Two microphone inputs shares one low noise amplifier with programmable gain and automatic gain
control(AGC) mechanism
• Voice power amplifier with programmable gain
• 2nd order Sigma-delta A/D Converter for voice uplink path
• shares D/A Converter for audio playback path
• Supports half-duplex hands-free operation
• Compliant with GSM 03.05
3.1.11 LCD/NAND Flash Interface

• Dedicated Parallel Interface supports 3 external devices with 8_/16-bit NAND flash interface,
8_/9_/16_/18-bit parallel interface, and serial interface for LCM
• supports simultaneous connection to 2 NAND devices
• Built-in NAND Flash Controller with 8-bit ECC for mass storage
3.1.12 LCD Controller

• Supports simultaneous connection to 3 parallel LCD modules, 2 parallel LCD and 1 serial LCD
modules or 1 parallel LCD and 2 serial LCD modules
• Supports LCM format: RGB332, RGB444, RGB565, RGB666, RGB888
• Supports LCD module with maximum resolution up to 800x480 at 18bpp @ 200MHz, 16bit LPDDR1.
480x320 at 18bpp @ 133MHz, 16bit LPDDR1.
• Per pixel alpha channel
• True color engine
• Capable of combining display memories with up to 4 blending layers
18 / 131
3. TECHNICAL BRIEF
3. TECHNICAL BRIEF
3.1.13 Audio CODEC
• Wavetable including GM full set of 128 instruments and 47 sets of percussions
• Advanced wavetable synthesizer capable of generating simulated stereo
• PCM Playback and Record
• Digital Audio Playback
• Supports HE-AAC codec decode
• Supports ASC codec decode
3.1.14 Audio Interface and Audio Front End

• Supports I2S interface
• High resolution D/A Converters for Stereo Audio playback
• Voice band A/D converter with digital MIC input support
• Stereo to Mono Conversion
3.1.15 Camera interface

• YUV422 format image input
• Capable of processing image of size up to 1.3M pixels(Mediatek serial Interface), 3M pixels(w/o
compression) and 5M pixels (with JPEG compression)
• Support panorama
• Support zero shutter delay
3.1.16 JPEG Decoder

• Hardware-accelerated baseline JPEG decoding
• SW based progressive JPEG decoding
• Supports various YUV format, DC/AC Huffman tables, and quatization Tables
3.1.17 JPEG Encoder

• ISO/IEC 10918-1 JPEG baseline mode
• ISO/IEC 10918-2 compliance
• Supports YUV420 formats
• Supports EXIF/JFIF
• Standard DC and AC Huffman tables
• Provides 5 levels of encode quality
19 / 131
3. TECHNICAL BRIEF
3. TECHNICAL BRIEF
3.1.18 Image Data Processing
• Supports Digital Zoom

• Supports RGB and YCbCr image processing
• High throughput hardware scaler. Capable of tailoring an image to an arbitrary size
• Horizontal scaling with bicubic interpolation
• vertical scaling with bicubic interpolation
• Simultaneous scaling for video buffer and display buffer
• YUV and RGB color space conversion
• Boundary padding
• Pixel processing: hue/saturation/intensity/color adjustment, Gamma correction and grayscale/
invert/sepia-tone effects
• Hardware accelerated image editing
• RGB/YCbCr format thumbnail output
3.1.19 MPEG-4/H.263 CODEC

• ISO/IEC 14496-2 simple profile
decode @ level 0/1/2/3
encode @ level 0
• ISO/IEC 14496- 2 advanced simple profile : Decode @ level 0/1/2/3
• ITU-T H.263 profile 0 @ level 40
• Encoder resync maker and HEC
• Supported visual tools for decoder: I-VOP, P-VOP, AC/DC Prediction, 4-MV, Unrestricted MV,
Error Resilience, Short Header
• Error Resilience for decoder : Slice Resynchronization, Data Partitioning, Reversible VLC
• Supported visual tools for encoder : I-VOP, P-VOP, Half-Pel, DC Prediction, Unrestricted MV,
Reversible VLC, Short Header
• Supports encoding motion vector of range up to -64/+63.5 pixels
• HE-AAC decode support
• AAC/AMR/WB-AMR audio decode support
• AMR/WB-AMR audio encode support
• Software Video CODEC
3.1.20 H.264 Decode

• Software Decoder
• ISO/IEC 14496-10 baseline profile :
decode @ level 2. 1
encode @ level 1
• ISO/IEC 14496-10 main/high profile :
decode @ level 2. 1
20 / 131
3. TECHNICAL BRIEF
3. TECHNICAL BRIEF
3.1.21 2D Accelerator
• Supports 32-bpp ARGB8888, 24-bpp RGB888, 16-bpp RGB565, and 8-bpp index color modes
• Rectangle fill with constant or gradient color
• BitBlt : capable with 7 rotation types, ROP4, Mask
• Alpha blending with 7 rotation types, per-pixel alpha and pre-multiplied alpha
• Font caching : normal and italic font
• Linear transform : Support perspective transform, truncate/nearest/bi-linear sample filter
• Command queue with max depth of 1024
21 / 131
3. TECHNICAL BRIEF
3. TECHNICAL BRIEF
3.1.22 Bluetooth Radio Features
• Fully compliant with Bluetooth specification 3.0

• Low out-of-band spurious emissions supports simultaneous operation with GPS and GSM/GPRS/
EDGE-Rx worldwide radio systems
• Low-IF architecture with high degree of linearity and high order channel filter
• Integrated T/R switch and Balun
• Fully integrated PA provides 10dBm output power
• -94dBm sensitivity with excellent interference rejection performance
• Hardware AGC dynamically adjusts receiver performance in changing environments
3.1.23 Bluetooth Baseband Feature

• Up to 4 simultaneous active ACL links
• Up to 1 simultaneous SCO or eSCO link with CVSD coding
• Supports eSCO
• Scatternet support : Up to 4 piconets simultaneously with background inquiry/page scan
• Supports sniff mode
• AFH and PTA collaborative support for WLAN/BT coexistence
• Idle mode and sleep mode enables ultra-low power consumption
• Supports PCM interface and built-in transcoders for A-law, u-law and linear voice with re-transmission
• Built-in hardware modem engine for access code correlation, header error correction, forward error
correction, CRC, whitening and encryption
• Channel quality driven data rate adaptation
• Channel assessment for AFH
3.1.24 Bluetooth Platform features

• Embedded processor for Bluetooth protocol stack with built-in memory system
• Fully verified ROM based system with code patch for feature enhancement
22 / 131
3. TECHNICAL BRIEF
3. TECHNICAL BRIEF
3.1.25 FM Features
• 76-108 MHz worldwide FM bands with 50kHz tuning step

• Supports RDS/RBDS radio data system
• Supports long/short antenna
• 30ms seek time per channel, and 6sec search time for all channels
• Superior stereo noise reduction
• Soft mute volume control
• Supports short antenna, auto calibration for different FM channels
• 60dB SINAD with 22.5 kHz FM deviation
• 3dBuVemf FM RX sensitivity with superior interference rejection
• 20dBuVemf(for SANT) or 19dBuVemf(for LANT) RDS sensitivity (dev: 2kHz)
• More than 55dBc rejection capability against -200 kHz ACL
23 / 131
3. TECHNICAL BRIEF
3. TECHNICAL BRIEF
3.2Power
3.2 PowerManagement
Management
The power management unit(PMU) manages the power supply of the entire chip, such as baseband,
processor, memory, SIM cards, camera, vibrator, etc. The digital part of PMU is integrated into the analog
part. PMU includes the following functions for signal processing:
3.2.1 Low Dropout Regulators(LDOs), Buck converter and Reference

The PMU Integrates 14 LDOs and 1 buck converter(BUCK) that are optimized for their given functions by
balancing quiescent current, dropout voltage, line/load regulation, ripple rejection, and output noise
▪ RF LDO (VRF)
The RF LDO is a linear regulator that could source 200mA (max) with 2.8V output voltage. It
supplies the RF circuitry of the handset. The LDO is optimized for high performance and adequate
quiescent current.
▪ Digital Core Buck Converter (VCORE)

The digital core regulator is a DC-DC step-down converter (Buck converter) that could source
350mA (max) with 1.3V to 0.9V programmable output voltage based on software register setting.
It supplies the power for baseband circuitry of the SoC. The buck converter is optimized for high
efficiency and low quiescent current.
Digital IO LDO (VIO18)
The digital IO LDO is a linear regulator that could source 100mA (max) with 1.8V output voltage. It
supplies the power for baseband circuitry of the SoC. The LDO is optimized for very low quiescent
current and turns on automatically together with Vm/Va LDOs.
 Analog LDO (VA)
The analog LDO is a linear regulator that could source 40mA (max) with 2.8V output voltage. It
supplies the analog sections of the SoC. The LDO is optimized for low frequency ripple rejection in
order to reject the ripple coming from the burst at 217Hz of RF power amplifier.
TCXO LDO (VTCXO)
The TCXO LDO is a linear regulator that could source 40mA (max) with 2.8V output voltage. It
supplies the temperature compensated crystal oscillator, which needs ultra low noise supply with
very good ripple rejection.
24 / 131
3. TECHNICAL BRIEF
3. TECHNICAL BRIEF
 Single-Step RTC LDO (VRTC)
The single-step RTC LDO is a linear regulator that can charge up a capacitor-type backup coin cell to 2.8
V, which also supplies the RTC module even at the absence of the main battery. The single-step LDO
features the reverse current protection and is optimized for ultra low quiescent current while sustaining
the RTC function as long as possible.
SIM LDO (VSIM)

The SIM LDO is a linear regulator that could source 60mA (max) with 1.8V or 3.0V output voltage
selection based on the supply specs of subscriber identity modules (SIM) card. It supplies the SIM card
and SIM level shifter circuitry in the handset. The Vsim LDO is controlled independently by the register
named VSIM_EN.
 SIM2 LDO (VSIM2)
The SIM2 LDO is a linear regulator that could source 60mA (max) with 1.3V, 1.5V, 1.8V, 2.5V, 2.8V, 3.0V or
3.3V output voltage selection based on the supply specs of the 2nd subscriber identity modules (SIM)
card. It supplies the 2nd SIM card and SIM level shifter circuitry in the handset. The Vsim2 LDO is
controlled independently by the register named VSIM2_EN.
 USB LDO (VUSB)
The USB LDO is a linear regulator that could source 60mA (max) with 3.3V output dedicated for USB
circuitry. It is controlled independently by the register named RG_VUSB_EN.
 Bluetooth LDO (VBT)
The VBT LDO is a linear regulator that could source 100mA (max) with 1.3V, 1.5V, 1.8V, 2.5V, 2.8V, 3.0V,
3.1V or 3.3V output for Bluetooth module. It is controlled independently by the register named
RG_VBT_EN.
 Camera Analog LDO (VCAMA)
The Vcama LDO is a linear regulator that could source 250mA (max) with 1.5V, 1.8V, 2.5V or 2.8V output
which is selected by the register named VCAMA_SEL[1:0]. It supplies the analog power of the camera
module. Vcama is controlled independently by the register named RG_VCAMA_EN.
 Camera Digital LDO (VCAMD)
The Vcamd LDO is a linear regulator that could source 100mA (max) with 1.3V, 1.5V, 1.8V, 2.5V, 2.8V,
3.0V or 3.3V output which is selected by the register named VCAMD_SEL[2:0]. It supplies the digital
power of the camera module. Vcamd is controlled independently by the register named
RG_VCAMD_EN.
25 / 131
3. TECHNICAL BRIEF
Output Output
Device Input pin Power Device Output Voltage(V) Power Net
pin Current (mA)
MT6255 AVDD43_ DC-DC
VCORE 1.2 350 VCORE_1V2
VCORE
AVDD43_VA Essential LDOs VA 2.8 40 AVDD_2V8
AVDD43_VD1 VIO18 1.8 400 VIO_1V8
AVDD43_VD2
VIO28 2.8 60 VIO_2V8
VMC 1.3/1.5/1.8/2.5/2.8/3.0/3.3 200 VMC_3V3
VSIM 1.8/3.0 60 VSIM1
VSIM2 1.3/1.5/1.8/2.5/2.8/3.0/3.3 60 VSIM2
VRTC 2.8 2 VRTC_2V8
Basic Feature VUSB 3.3 60 VUSB_3V3
LDOs VBT 1.5/1.8/2.5/2.8/3.0/3.1/3.3 100 VBT_3V1
VCAMA 1.5/1.8/2.5/2.8 150 VCMA_1V8
VCAMD 1.3/1.5/1.8/2.5/2.8/3.0/3.3 200 VCMAIO_1V8
Extra LDOs VIBR 1.3/1.5/1.8/2.5/2.8/3.0/3.3 200 VIBR_3V0
2G Transceiver
VTCXO 2.8 40 VTCXO_2V8
LDOs
AVDD43_VRF VRF 2.84 200 VRF_2V8
LED_KP KPLED 150mA (8 steps) KEY_BL0
Current Sink 6 x(24 mA,0.25V),Sharing(Individual Current BLED_EN
ISINK0~5 / Enable control) GLED_EN
4/8/12/16/20/24 mA RLED_EN
Table3.2.1. Power Supply Domains
3. TECHNICAL BRIEF
3. TECHNICAL BRIEF
3.2.2
3.2.2Power
PowerOn
OnSequence
Sequence
The PMU handles the powering ON and OFF of the handset. There are three ways to power-on the
handset system :
1. Push PWRKEY (Pull the PWRKEY pin to the low level)
Pulling PWRKEY low is the typical way to turn on the handset. The VCORE buck converter will be turned-
on first, and then VA/VIO LDOs turn-on at the same time. After VA/VIO turn-on, VUSB LDOs, and finally
VRF/VTCXO LDOs will be turn on. The supplies for the baseband are ready and then the system reset
ends at the moment when the VCORE/VA/VIO/VUSB/VRF/VTCXO are fully turned-on to ensure the
correct timing and function. After that, baseband would send the PWRBB signal back to PMU for
acknowledgement. To successfully power-on the handset, PWRKEY should be kept low until PMU
receives the PWRBB from baseband.
2. RTC module generate PWRBB to wakeup the system
If the RTC module is scheduled to wakeup the handset at some time, the PWRBB signal will directly send
to the PMU. In this case, PWRBB becomes high at the specific moment and let PMU power-on just like
the sequence described above. This is the case named RTC alarm.
3. Valid charger plug-in (CHRIN voltage is within the valid range)
Charger plugging-in will also turn on the handset if the charger is valid (no OVP take place). However, if
the battery voltage is too low to power-on the handset (UVLO state), the system won‘t be turned-on by
any of these three ways. In this case, charger will charge the battery first and the handset will be
powered-on automatically as long as the battery voltage is high enough.
Under-voltage Lockout (UVLO)
The UVLO state in the PMU prevents startup if the initial voltage of the main battery is below the 3.2V
threshold. It ensures that the handset is powered-on with the battery in good condition. The UVLO
function is performed by a hysteretic comparator which can ensure the smooth power-on sequence. In
addition, when the battery voltage is getting lower and lower, it will enter UVLO state and the PMU will
be turned-off by itself, except for Vrtc LDO, to prevent further discharging. Once the PMU enters UVLO
state, it draws low quiescent current. The RTC LDO is still working until the DDLO disables it.
Deep Discharge Lockout (DDLO)
PMU will enter to the deep discharge lockout (DDLO) state when the battery voltage drops below 2.5V.
In this state, the Vrtc LDO will be shutdown. Otherwise, it draws very low quiescent current to prevent
further discharging or even damage to the cells.
Reset
The PMU contains a reset control circuit which takes effect at both power-up and power-down. The
RESETB pin is held at low in the beginning of power-up and returns to high after the pre-determined
delay time. The delay time is controlled by a large counter, which use clock from internal ring-oscillator.
At power-off, RESETB pin will return to low immediately without any delay.
27 / 131
3. TECHNICAL BRIEF
3. TECHNICAL BRIEF
3.3 FEM with integrated Power Amplifier Module (RF7182)
3.3 FEM with integrated Power Amplifier Module (RF7182)
3.3.1 Internal Block Diagram
3.3.1 Internal Block Diagram
GND
GND
GND
NC
RX0
RX1
GND 1 22 21 20 19 18 17
RFIN HB 2
ESD 16 NC
Protection
GND 3 Amplifier Switch 15 ANTENNA
14 GND
RFIN LB 4
13 GND
GND 5 CMOS Controller
GND 6 7 8 9 10 11 12
GPCTRL1
VRAMP
TX ENABLE
GPCTRL0
VBATT
NC
Figure. 3.3.1 RF7182 FUNCTIONAL BLOCK DIAGRAM
Figure. 3.3.1 RF7182 FUNCTIONAL BLOCK DIAGRAM
3.3.2 General Description
The RF7182 is a quad-band GSM/GPRS Class 12 compliant transmit module (GSM850 / EGSM900 /
DCS1800 / PCS1900) with two symmetrical receive ports. This transmit module builds upon RFMD’s leading
power amplifier with PowerStar® integrated power control technology, pHEMT switch technology, and
integrated transmit filtering for best-in-class harmonic performance. The results are high performance, a
reduced solution size, and ease of implementation. The device is designed for use as the final
portion of the transmitter section in aGSM850 / EGSM900 / DCS1800 / PCS1900 handset and eliminates
the need for PA-to-antenna switch module matching network.
The RF7182 features RFMD’s latest integrated power-flattening circuit, which significantly reduces current and
power variation into load mismatch. The RF7182 also integrates an ESD filter to provide excellent ESD
protection at the antenna port. TheRF7182 is designed to provide maximum efficiency at rated POUT.
/ 131
3. TECHNICAL BRIEF
TX Module Mode Tx ENABLE GpCtrl1 GpCtrl0

Off 0 0 0
RX 0 0 1 0
RX 1 0 1 1
GSM850/900 TX Mode 1 1 0
DCS1800/PCS1900 TX Mode 1 1 1
VBAT
Changed (9/10)
C410 22u
Changed (7/27)
C408 0.1u
RF_ANT_SW2
(10V, X5R)
RF_ANT_SW1
C409 22p
RF_PA_EN
(50V) R407 10K
RF_TX_RAMP
C463 C464 C465

C407
(7/16) U400 : RF7180 -> RF7182 DNI DNI DNI

220p
R409
24K
11
10
9
8
7
VBATT
GPCTRL1
GPCTRL0
TX_ENABLE
VRAMP
Changed (11/6)
close to TXM
Shielding by GND
NC1 GND4
12 6
GND5 GND3
13 5 (50ohm)
C461 100p
14
GND6 RFIN_LB
4
LowBand_Tx
ANTENNA GND2
15 U400 3 (50ohm)
C462 100p
16
NC2 RFIN_HB
2
HighBand_Tx
GND1
1 (7/3) DC Blocking
GND_SLUG
GND7
GND8
GND9
NC3
RX1
RX0
C451 C452
17
18
19
20
21
22
23
DNI DNI
Figure 3.3.2 RF-module CIRCUIT DIAGRAM
3. TECHNICAL BRIEF
3. TECHNICAL BRIEF
3.4Clocks
3.4 Clocks
There are two major time bases in the MT6255. For the faster one is the 26 MHz clock originated from the
digital control oscillator(DCXO) of RF block. This is then converted to the square-wave signal through
CLKSQ.
The other time base is the 32768 Hz clock generated by an on-chip oscillator connected to an external
crystal.
26MHz EN
DCXO MPLL_SEL 104MHz EMI clock
(Cx8300_0204[1:0]) CG 104MHz AHB clock
CLKSQ_DIV2_MCU_SEL0
(Cx8300_0100[0]) 0 52MHz AHB clock
2
3 FMCU_CK 52MHz APB clock
CLKSQ CLKSQ_26M_CK 1/2 0 MCV_DCM
1
CLKSQ_DIV2_MCU_SEL0
1/2 (Cx8300_0100[1]) DPLL_SEL
EN
CLKSQ_CON (Cx8300_0100) (Cx8300_0204[3:2])
0 CG 10MHz GDSP1_CK
10MHz GDSP2_CK
1 0
2 FDSP_CK
MPLL MPLL_113M_CK 3
DSP_DCM
PLL_CON0(Cx8300_0200)
PLL_CON1(Cx8300_0204) CLKSQ_DIV2_GSM_SEL0 GPLL_SEL
(Cx8300_0100[2]) (Cx8300_0204[4])
MPLL_CON0(Cx8300_0210) EN
MPLL_CON1(Cx8300_0214)
0 CG
52MHz GGSM_CK
1 0 52MHz BFE_clock
UPLL UPLL_CON0(Cx8300_0208) 1 FGSM_CK
UPLL_CON1(Cx8300_020C)
GSM_DCM
UPLL_104M_CK
CLKSQ_DIV2_USB_SEL0 UPLL_SEL
(Cx8300_0100[3]) (Cx8300_0204[5])
EN
0 CG
GUSB_CK
1 0 FUSB_CK
1
USB_DCM
UPLL_48M_USB_CK USB PHY USB_PHY_CLK MSDC_DCM

EN
MSDC_clock
UPLL_48M_IRDA_CK F48M_CK
CG IrDA_clock
32KHz EN
XOSC_ANA XOSOOUT F32k_CK

CG SLOW_CK
XOSQ_CON (Cx8300_0000)
Figure. 3.4.1 Clock distributions inside the MT6255.

SLOW_DCM
MT6255
MT6255
B15
XOUT
A15
XIN
C15 X102
TESTMODE
VCO_MONITOR_BT
DVDD28_IO 1 2
SALNA_IN_N_FM
SALNA_IN_P_FM
(VIO_2V8) 32.768KHz
LNA_IN_N_FM
LNA_IN_P_FM
FC-135
TRXIQ_N_BT
TRXIQ_P_BT
RF2G_N_BT
RF2G_P_BT
2 C144 2 C145
RBIAS_BT
BPI_BUS0
BPI_BUS1
BPI_BUS2
BPI_BUS3
BPI_BUS4
BPI_BUS5
22p 22p
1 1
AC10
AC11
G10
AA13
AB12
AB14
AB10
AB11
C11
U14
A12
B12
B11
Y13
V14
F11
Figure. 3.4.2 Crystal Oscillator External Connection
LGE Internal Use Only

30 / 131 ExternalCopyright
Figure. 3.4.2 Crystal Oscillator © 2007 LG Electronics. Inc. All right reserved.
Connection
3. TECHNICAL BRIEF
3. TECHNICAL BRIEF
3.4.1 32.768KHz Time Base
The 32768 Hz clock is always running. It’s mainly used as the time base of the Real Time Clock(RTC) module,
which maintains time and date with counters. Therefore, both the 32768Hz oscillator and the RTC module is
powered by separate voltage supplies that shall not be powered down when the other supplies do.
In low power mode, the 13Mhz time base is turned off, so the 32768Hz clock shall be employed to update the
critical TDMA timer and Watchdog Timer. This time base is also used to clocks the keypad scanner logic
3.4.2 26MHz Time Base

Since PLL are based on 13MHz reference clock. There is an ½-dividers for PLL existing to allow using 26MHz
DCXO.
There are 2 phase-locked loops(PLL) in MT6255. The UPLL generates 624Mhz clock output, then a frequency
divider further divide 6, and 13 to generate fixed 103Mhz, and 48Mhz for GSM_CLOCK and USB_CLOCK and
DSP_CLOCK. These four primary clocks then feed into GSM, USB, MCU and DSP Clock Domain, respectively.
These 2 PLLs require no off-chip components for operations and can be turn off in order to save power. After
power-on, the PLLs are off by default and the source clock signal is selected through multiplexers. The software
shall take cares of the PLL lock time while changing the clock selections. The PLL and usages are listed below.
- PLL supply four clock source : MCU_CLOCK(104~113Mhz), DSP_CLOCK(104~113Mhz),
GSM_CLOCK(104Mhz) and USB_CLOCK(48Mhz)
- For DSP/MCU system clock, MCU_CLOCK and DSP_CLOCK. The outputted 104~113Mhz clock is controlled by
MCU for 500Khz per step and settled time is under 100uS. The clock is also connected to DSP/MCU DCM
(dynamic clock manager) for dynamically adjusting clock rate by digital clock divider.
MCU_CLOCK paces the operations of the MCU cores, MCU memory system, and MCU peripherals as well
- Modem system clock, GSM_CLOCK, which paces the operations of the GSM/GPRS hardware, coprocessors as
well. The outputted 104Mhz clock is connecter to GSM_DCM for dynamically adjusting clock rate by digital
clock divider. Typically the GSM_DCM output clock no more than 52Mhz.
Note that PLL need some time to become stable after being powered up. The software shall take cares of the
PLL lock time before switching them to the proper frequency. Usually, a software loop longer than the PLL lock
time is employed to deal with the problem.
For power management, the MCU software program may stop MCU Clock by setting the Sleep Control Register.
Any interrupt requests to MCU can pause the sleep mode, and thus MCU return to the running mode.
AHB also can be stop by setting the Sleep Control Register. However the behavior of AHB in sleep mode is a
little different from that of MCU. After entering Sleep Mode, it can be temporarily waken up by any “hreq”(bus
request), and then goes back to sloop automatically after all “hreqs” de-assert. Any transactions can take place
as usual in sleep mode, and it can save power while there is no transaction on it. However the penalty is losing a
little system efficiency for switching on and off bus clock, but the impact is small
31 / 131
3. TECHNICAL BRIEF
3. TECHNICAL BRIEF
3.5 RFSYS of MT6253 (U101)
3.5 RFSYS of MT6253 (U101)
Figure.3.5.1
Figure. 3.5.1 Block
Block DIAGRAM
DIAGRAM of
ofRFSYS
RFSYS
3.5.1 GENERAL DESCRIPTION

RFSYS built in MT6255 SOC is a highly integrated RF transceiver for multi-band GMS and GPRS and EDGE-Rx
cellular systems. The features are listed as following.
 Receiver
- Quad band differential input LNAs
- Quadrature RF mixers
- Fully integrated channel filter with f3dB=700kHz
- 96 dB dynamic range ADC
- 24 dB PGA gain with 6 dB gain Step
32 / 131
3. TECHNICAL BRIEF
3. TECHNICAL BRIEF
 Transmitter
- DFM for GSM/GPRS application
 Frequency Synthesizer
- Programmable fractional-N synthesizer
- Integrated wide range RFVCO
- Integrated loop filter
- Fast settling time suitable for multi-slot GPRS/EDGE applications
 Digitally-Controlled Crystal Oscillator (DCXO)

- Two-pin 26 MHz crystal oscillator
-On-chip programmable capacitor array for coarse - tuning
- On-chip programmable capacitor array for fine – tuning
- Low power mode support for 32K crystal removal
 3-wire serial interface

 CMOS process technology
 41 balls(incl.24 GND balls) of RFSYS in TFBGA package
33 / 131
3. TECHNICAL BRIEF
3. TECHNICAL BRIEF
3.6MEMORY(H9DA1GH25HBMMMR,
3.6 MEMORY(H9DA1GH25HBMMMR, U100
U100 ) )
3.6.1
3.6.1Functional
FunctionalDescription
Description
SK hynix NAND Flash is offered in 1.8 Vcc and VccQ Power Supply, and with x16 I/O interface. Its NAND cell
provides the most cost-effective solution for the solid state mass storage market. The memory is divided
into blocks that can be erased independently so it is possible to preserve valid data while old data is
erased. The Depending on whether the devices have a x8 or x16 bus width, the page size is (1024+32
spare) words.
Each block can be programmed and erased up to 50,000 cycles with ECC (error correction code) on. To
extend the lifetime of Nand Flash devices, the implementation of an ECC is mandatory.
The chip supports CE# don't care function. This function allows the direct download of the code from the
NAND Flash memory device by a microcontroller, since the CE# transitions do not stop the read operation.
In addition, device supports ONFI 1.0 specification. The copy back function allows the optimization of
defective blocks management: when a page program operation fails the data can be directly
programmed in another page inside the same array section without the time consuming serial data
insertion phase. We don’t have EDC function in this device.
A write protect pin is available to provide hardware protection against program and erase operations. The
devices feature an open-drain ready/busy output that identifies if the program/erase/read controller is
currently active. The use of an open-drain output allows the ready/busy pins from several memories to
connect to a single pullup resistor.
The devices have a cache read feature that improves the read throughput for large files. During cache
reading, the devices loads the data in a cache register while the previous data is transferred to the I/O
buffers to be read. This feature is implemented according to ONFI 1.0 specification.
34 / 131
3. TECHNICAL BRIEF
3. TECHNICAL BRIEF
VCC
CE# IQ0~IQ15
WE#
RE# R/B#
ALE
CLE
WP#
VSS
Figure.
Figure. 3.6.1
3.6.1 LOGICDIAGRAM
LOGIC DIAGRAM
Table 3_6_1 Signal Names
Table 3_6_1 Signal Names

35 / 131
3. TECHNICAL BRIEF
3. TECHNICAL BRIEF
A27~A0
ADDRESS
REGISTER/
COUNTER
PROGRAM
ERASE X
CONTROLLER
HV GENERATION D
NAND Flash E
C
ALE MEMORY ARRAY O
D
CLE
E
WE R
CE COMMAND
WP INTERFACE
LOGIC
RE PAGE BUFFER
Y DECODER
COMMAND
REGISTER
I/O BUFFER
DATA
REGISTER
IO0~IO15
Figure. 3.6.2 BLOCK DIAGRAM

Figure. 3.6.2 BLOCK DIAGRAM
36 / 131
3. TECHNICAL BRIEF
3. TECHNICAL BRIEF
3.6.2 Features
[ MCP ] [ DDR SDRAM ]
• Operation Temperature
- -30oC ~ 85oC •Standard SDRAM Protocol
• Package •Clock Synchronization Operation
- 130-ball FBGA - 8.0x9.0mm2, 1.0t, 0.65mm pitch
- Lead & Halogen Free •Multibank Operation : Internal 4 Bank Operation
•VDD / VDDQ = 1.7V to 1.95V
[ NAND Flash ]
• OPEN NAND FLASH INTERFACE(ONFI) 1.0 •Memory Cell Array
COMPLIANT - 4Mb x 4Bank x 16 I/O

• POWER SUPPLY VOLTAGE •LVCMOS Compatible I/O Interface
-VCC/VCCQ = 1.7V ~ 1.95V •Programmable Burst Length
-MEMORY CELL ARRAY (with SPARE) - 1, 2, 4, 8 or full page
- Page size : (1K+32spare) words
•Programmable Burst Type
- Block size : (64K+2K) words
- sequential or interleaved
- Plane size : 1024blocks
•Programmable CAS Latency
- Device size : 1024blocks
• PAGE READ / PROGRAM TIME •Programmable Drive Strength
- Random Read Time(tR) : 25us(Max)

- Sequential access time : 45ns(Min)
- Page program : 300us(Typ)
• BLOCK ERASE
- Block Erase Time : 3ms(Typ.)
• COMMAND SET
- ONFI1.0 Compliant command set
- Read Unique Ids
• ELECTRONIC SIGNATURE
- 1st cycle: Manufacturer Code
- 2nd cycle: Device Code
- 3rd cycle: Internal chip number, Cell Type,
Number of Simultaneously
Programmed Pages
- 4th cycle: Page size, Block size, Organization,
Spare size
• RELIABILITY
- 50,000 Program / Erase cycles
(with 4bit/512+16 Byte ECC)
• DATA RETENTION
- 10 years
37 / 131
3. TECHNICAL BRIEF
3.7 SIM Card Interface

VSIM_1
SIM2 (SW must be careful)
J201
R267
1 4 DNI
C1 C5
2 5
SIM_1_RST C2 C6
3 6
SIM_1_CLK C3 C7 SIM_1_DATA
7 10
GND1 GND4
8 9
VA228 GND2 GND3
VA229 C280 VA233
C279 C276 2 C277
DNI DNI 1u DNI
1
VSIM_2
J202
R268
1 4 DNI
C1 C5
2 5
SIM_2_RST C2 C6
3 6
SIM_2_CLK
7
C3 C7
10
SIM_2_DATA
GND1 GND4
8 9
VA234 GND2 GND3
VA235 C283 VA236
C281 C282 C284
DNI DNI 1u DNI
VSIM_3
J203 R269
1 4 DNI
C1 C5
2 5 1 2
SIM_3_RST C2 C6
3 6
SIM_3_CLK
7
C3 C7
10
SIM_3_DATA
GND1 GND4
8 9
VA237 GND2 GND3
2 C285
VA238
2 C286 2 C287 2 C288 VA239
DNI DNI 1u DNI

1 1 1 1
VSIM_4
J204 R240
1 4 DNI
C1 C5
2 5 1 2
SIM_4_RST C2 C6
3 6
SIM_4_CLK
7
C3 C7
10
SIM_4_DATA
GND1 GND4
8 9
VA208 GND2 GND3
2 C241
VA209
2 C242 2 C243 2 C244 VA210
DNI DNI 1u DNI

1 1 1 1
3. TECHNICAL BRIEF
Added for Dual SIM (10/12) Changed for Dual SIM (11/9)
VIO_1V8 VBAT VSIM_1VSIM1 VSIM_2 VSIM_3 VSIM_4 VSIM2
R284
R285
0
0
C239 C2372 2 C238
2.2u 2.2u 1u
1 1
1u
1u
2 2
C259
C260
RST_N
1u
1u
C257
C258
1 1
SIM2 (SW)
23
19
Close to IC (10/12)
4
SYSRSTB
VIO
VBAT
R278 0
SIM_1_CLK
R279 0
SIM_1_RST VSIM1
R280 0 5
SIM_1_DATA SCLK1/GPIO1 SIM_1_CLK
SIM2 (SW)
6
SIM_CLK SIMCLK1/GPI13 SRST1/GPIO2 SIM_1_RST
15 7
SIO1/GPIO3
8
SIM_1_DATA
SIM_RST SIMRST1/GPI14
14
VSIM2
3
SIM_DATA SIMIO1/GPI15 SCLK2/GPIO4 SIM_2_CLK
SIM3 (SW)
13 2
SRST2/GPIO5
1
SIM_2_RST
SIO2/GPIO6
28
SIM_2_DATA
SIM2_CLK SIMCLK2/GPI16
16
U202 VSIM3
27
SIM2_RST SIMRST2/GPI17 SCLK3/GPIO7 SIM_3_CLK
SIM1 (SW) SIM4 (SW)
17 24
Close to IC (10/12) SRST3/GPIO8
25
SIM_3_RST
SIM2_DATA SIMIO2/GPI18 SIO3/GPIO9 SIM_3_DATA
R281 0 18 26
SIM_4_CLK
R282 0 Added for Quad SIM (10/12)
SIM_4_RST 20
CE0 VSIM4
9
R283 0
SIM_4_DATA SCLK4/GPIO10 SIM_4_CLK
SIM1 (SW)
10
I2C_SCL2 21
SCL SRST4/GPIO11
11
SIM_4_RST
SIO4/GPIO12
12
SIM_4_DATA
I2C_SDA2 SDA
GND
22
29
In case of dual SIM

R278, R279, R280, R281, R282, R283, R284, R285 : Install
U202, C237, C238, C239, C257, C258, C259, C260 : DNI
In case of quad SIM

Figure 3.7.2 SIM controller Circuit Diagram
R278, R279, R280, R281, R282, R283, R284, R285 : DNI
U202, C237, C238, C239, C257, C258, C259, C260 : Install
3. TECHNICAL BRIEF
3. TECHNICAL BRIEF
The Main Base Band Processor(MT6255) contains two dedicated smart card interfaces to allow the
MCU to access the two SIM cards. Each interface can operator via 5 terminals. As shown is the Figure
3.8.2, SIMVCC, SIMSEL, SIMRST, SIMCLK and SIMDATA are for one SIM interface, while SIM2VEE, SIM2SEL,
SIM2RST, SIM2CLK and SIM2DATA are for the other one.
The functions of the two SIM interfaces are identical; therefore, only first SIM interface will be described
in this document.
The VSIM is used to control the external voltage supply to the SIM card and SIM SEL determines the
regulated smart card supply voltage. SIMRST is used as the SIM card reset signal. Besides, SIMDATA and
SIMCLK are used for data exchange purpose.
A395 is using U202 as SIM controller to be able to use Quad SIM.
Figure 3.7.3 SIM Interface block diagram
40 / 131
3. TECHNICAL BRIEF
3. TECHNICAL BRIEF
• General Description
The MT6306 is a SIM card / GPIO control chip optimized for GSM handsets, especially those based on
the MediaTek MT62xx system solution. It supports up to four SIM interfaces or 12 GPIOs plus six GPIs.
Each SIM interface can be individually programmed as GPIOs. The SIM interface supports both 1.8V and
3V SIM cards. An I2C interface is used to control SIM channel individually.
The MT6306 is available in 28-pin 4mm x 4mm QFN package. The operating temperature range is from
-25°C to +85°C.
• Features
Control and communication through an I2C interface with baseband processor.
Independent 1.8V/3V VCC control for each SIM card
Power management and control for quad SIM cards
Independent clock stop mode (at high or low level) for each SIM card
Programmable SIM interface pins (can be SIM interface pins or GPIO pins)
Compatible with MediaTek baseband processor chips, MT6252, MT6253, MT6235, MT6236, etc.
28-Pin 4mm x 4mm QFN Package
Figure 3.7.4 MT6306 Block diagram
LGE Internal Use Only Figure 3.7.4 MT6306 Block diagram

Copyright © 2007 LG Electronics. Inc. All right reserved.
41 / 131
3. TECHNICAL BRIEF
3. TECHNICAL BRIEF
3.8 Micro-SD Card Interface
3.8 Micro-SD Card Interface
VIO_2V8
J301
1 8
MSD_D[2] DAT2 DAT1 MSD_D[1]
2 7
MSD_D[3] CD/DAT3 DAT0 MSD_D[0] R221
3 6
MSD_CMD CMD VSS (7/3) R221 : 1Mohm
4 5 1M
9
VDD CLK
11
MSD_CLK
Changed (10/30) GND1 POL
10 12
VMMC_3V3 GND2 DET MSD_DET_N
C265
1u
VA324 VA325 VA326 VA321 VA322 VA323

Changed (12/29)
1u
1u
C270
C235
Figure 3.8.1 Micro-SD Card Interface

Figure 3.8.1 Micro-SD Card Interface
The controller fully supports the Memory Stick bus protocol as defined in Format Specification version 2.0 of
Memory Stick Standard (Memory Stick PRO) and the SD Memory Card bus protocol as defined in SD Memory
Card Specification Part 1 Physical Layer Specification version 2.0 as well as the Multi Media Card(MMC) bus
protocol as defined in MMC system specification version 4.1. Since SD memory Card bus protocol is backward
compatible to MMC bus protocol, the controller is capable of working well as the host on MMC bus under
control of proper firmware. Furthermore, the controller also support SDIO card specification version 1.0 partially.
However, the controller can only be configured as either the host controller.
42 / 131
3. TECHNICAL BRIEF
3.9 LCD Interface 3. TECHNICAL BRIEF

VIO_1V8
3.9 LCD Interface VBAT
R307 2
DNI 1
C305
35
2.2u
LCD_LED_CA1
FL300 LCD_LED_CA2 34 Added (10/31)
33
LCD_LED_CA3
LCD_WR_N 1 INOUT_A1 INOUT_B1 9 32
LCD_RS 2 INOUT_A2 INOUT_B2 8 IF_MODE[1:0] = 01 --> 00 R308 100K 31 VIO_1V8

D[15:0] 16 bit --> D[7:0] 8 bit mode
LCD_CS_N 3 INOUT_A3 INOUT_B3 7 Changed (9/10)
30 1 2
4 INOUT_A4 INOUT_B4 6 IM0 29 R312
IM1
LCD_VSYNC 28 100K
G1
G2
R367
27
LCD_RD_N
10K
5 10 26
7.5pF
25
24
LCD_RST_N
23
22
VA327 VA328 Added (9/10)
FL301 21
C322
20
1u
LNAND_D_[07] 1 INOUT_A1 INOUT_B1 9 19
Changed from D[15:8] to D[7:0] 15
G1
G2
Changed (9/10) 14
5 10
7.5pF 13
12
11
FL302 10
VIO_1V8 VIO_2V8
9
LNAND_D_[06] 1 INOUT_A1 INOUT_B1 9
8
7
6
5
G1
G2
R311 100K 4
LCD_ID 3
5 10
7.5pF VA329
2
VA332 VA331
Added (9/10) 1 C308 C309
CN301
1u 1u
TIANMA LCD ID : HIGH
Added (10/30)
Figure3.9.1
Figure 3.9.1LCD
LCDInterface
Interface
MT6255 contains a versatile LCD controller which is optimized for multimedia applications. This controller
supports many types of LCD modules and contains a rich feature set to enhance the functionality. These
features are:
• Up to 800x480 at 18 bpp @ 200 MHz, 480x320 at 18 bpp @ 133 MHz
• Supports LCD format : RGB332, RGB444, RGB565, RGB666, RGB888 LCD modules.
• 4 Layers Overlay with individual color depth, window size, vertical and horizontal offset, source key,
alpha value and display rotation control(90°,180°, 270°, mirror and mirror then 90°, 180° and 270°)cc
• One Color Look-Up Table
• Three Gamma Correction Tables
For parallel LCD modules, the LCD controller can reuse external memory interface or use dedicated 16/18-bit
parallel interface to access them and 8080 type interface is supported. It can transfer the display data from the
internal SRAM or external SRAM/Flash Memory to the off-chip LCD modules.
For serial LCD modules, this interface performs parallel to serial conversion and both 8- and 9- bit serial interface
is supported. The 8-bit serial interface uses four pins – LSCE#, LSDA, LSCK and LSA0 – to enter commands and
data.
Meanwhile, the 9-bit serial interface uses three pins – LSCE#, LSDA and LSCK – for the same purpose. Data read
is not available with the serial interface and data entered must be 8 bit.
LGE Internal
UseUse
OnlyOnly
LGE Internal - 42
43 -
/ 131 Copyright
Copyright©©2007
2013 LG Electronics.
LG Electronics. Inc.Inc. All reserved.
All right right reserved.
Only for training and
Onlyservice purposes
for training and service purposes
3. TECHNICAL BRIEF
LCD Charge Pump

3. TECHNICAL BRIEF
Changed (8/8)
VMMC_3V3
VFM_2V8
VIO_1V8
Changed (10/30)
Added for NC pin (8/21)
VBAT
VBAT
2.2u
C360
2
2.2u
R351
C351
1 1K
21
11
14
12
3
SLUG_G
AGND
PGND
LDO2
LDO1
NC2
15
NC1 ENA
10 9
AVIN
U302 13
VOUT
20
LCD_LED_CA1 LED1 PVIN
19 6
LCD_LED_CA2 LED2
18
LCD_LED_CA3 LED3 SDA I2C_SDA2
17 8
16
LED4 SCL
7
I2C_SCL2
C2N
C1N
C2P
C1P
NP0 --> X7R (8/27)

2
2.2u
2.2u
C352 C353 2
2
33p
C354 C355
C356
C357
1u
1
1 (10V)
1u 1u
Figure 3.9.2 Charge Pump CIRCUIT DIAGRAM

Figure 3.9.2 Charge Pump CIRCUIT DIAGRAM
The RT9367C is an integrated solution for backlighting and phone camera input supply. The part contains a
charge pump white LED driver and dual low dropout linear regulators. This IC can be shut down by pulling EN
low.
In the section of charge pump, The RT9367C can power up 4 white LEDs with regulated constant current for
uniform intensity. Each channel (LED1-LED4) can support up to 25mA. The part maintains highest efficiency by
utilizing a x1/x1.5/x2 fractional charge pump and low dropout current regulators. An internal 5-bit DAC is used
for brightness control. Users can easily configure up to 32-step of LED current by I2C interface.
In the section of linear regulator, The RT9367C comprises a dual channel, low noise, and low dropout regulator
sourcing up to 300mA at each channel. The range of output voltage can be configured from 1.1V to 3.3V by I2C
interface. The outputs of LDO offer 3% accuracy and low dropout voltage of 250mV @ 300mA. The LDO also
provides current limiting and output short circuit thermal folded back protection.
44 / 131
3. TECHNICAL BRIEF
3. TECHNICAL BRIEF
3.10 Battery Charger Interface
3.10 Battery Charger Interface
VUSB_LDO_4V9 VBUS_USB VBAT VIO_1V8
R271
100K
11
PGND
1 10
VIN BATT
2 9
ISET U204 PGB
3 8
4
GND1 CHGSB
7
EOC
LDO GND2
5 6
IEOC EN_SET CHG_EN
C289
R276
R277
R274
C275
DNI
820
3K
0.1u 0.1u
50V internal voltage (10/31)
Figure 3.10.1 BATTERY CHARGER BLOCK

Figure 3.10.1 BATTERY CHARGER BLOCK
The RT9536 is a fully integrated single cell Li-ion battery charger IC ideal for portable applications.
The RT9536 optimizes the charging task by using a control algorithm including pre-charge mode, fast
charge mode and constant voltage mode. the input voltage range of the VIN pin can be as high as 28V.
When the input voltage exceeds the OVP threshold, it will turn off the charging MOSFET to avoid
overheating of the chip.
In RT9536, the maximum charging current can be programmed with an external resistor. For USB application,
the user can set the current to 100mA/500mA through the EN/SET pin. For the factory mode, the RT9536 can
allow 4.2V or 4.35V/2.3A power pass through to support system operation. It also provides a 50mA LDO to
support the power of peripheral circuit. The internal thermal feedback circuit regulates the die temperature
to optimize the charge rate for all ambient temperatures. The RT9536 provides protection functions such as
under voltage protection, over voltage protection for VIN supply and thermal protection for battery
temperature.
The RT9536 is available in a WDFN-10L 3x2 package to achieve optimized solution for PCB space and
thermal considerations.
45 / 131
3. TECHNICAL BRIEF
3.11 Keypad Interface

SW1 SW2
KB300
KB301
1 2
R301
1 2
KEY_ROW0
680
VA301
NUM 1 NUM 2 NUM 3 UP DOWN

KB302 KB303 KB304 KB305 KB306
R302
KEY_ROW2
680
VA302
NUM 4 NUM 5 NUM 6 LEFT RIGHT

KB308 KB309 KB310 KB311 KB312
R303
KEY_ROW3
680
VA304
Changed (12/29)
NUM 7 NUM 8 NUM 9 OK
KB313 KB314 KB315 KB316
R316 1 2
KEY_ROW4
680
VA305
STAR NUM 0 SHARP SEND

KB317 KB318 KB319 KB320
R304
KEY_ROW1
680
VA306
Changed (12/29)
VA307 VA309 VA310 VA308

VA311
R309
680
R305
R306
R317
680
680
680
R318
680
KEY_COL0
KEY_COL1
KEY_COL2
KEY_COL3
KEY_COL4
SIM Selection KEY

END
SW300
R365
S1
KEY_ROW4 3
680
4
VA314
5
(10/12) Changed
KB307
6
S2 END_KEY
R366 VA303
KEY_COL4
680
Added for ESD (8/21) 1 VA315
Figure 3.11.1 MAIN KEY STRUCTURE
3. TECHNICAL BRIEF
3. TECHNICAL BRIEF
The keypad can be divided into two parts: one is the keypad interface including 7 columns and 6
rows(A395 is using 5columns and 5rows) with one dedicated power-key, as shown in Figure 3.11.2; the
other is the key detection block which provides key pressed, key released and de-bounce mechanisms.
Each time the key is pressed or released, i.e. something different in the 6 x 7 matrix or power-key, the key
detection block senses the change and recognizes if a key has been pressed or released. Whenever the key
status changes and is stable, a KEYPAD IRQ is issued. The MCU can then read the key(s) pressed directly in
KP_MEM1, KP_MEM2, KP_MEM3, and KP_MEM4 registers. To ensure that the key pressed information is
not missed, the status register in keypad is not read-cleared by APB read command. The status register can
only be changed by the key-pressed detection FSM.
Figure 3.11.2 8x8 matrix with one power-key

Figure 3.11.2 8x8 matrix with one power-key
47 / 131
3. TECHNICAL BRIEF
3. TECHNICAL BRIEF
3.12 Audio
3.12 Audio Front-End
Front-End
3.12.1General
3.12.1 GeneralDescription
Description
Audio mixed-signal blocks (AMB) integrate complete voice uplink/downlink and audio playback function. As
shown in the figure below, it includes three parts. The first consists of stereo audio DACs and audio amplifiers
for audio playback. The second part is the voice downlink path, including voice-band DACs (left channel
audio DAC) and voice amplifier, which produces voice signal to earphone or other auxiliary output device.
Amplifiers in the two blocks are equipped with multiplexers to accept signals from internal audio/voice. The
last part is the voice path, which is the interface between the microphone (or other auxiliary input device)
input and MT6255 DSP. A set of bias voltage is provided for the external electric microphone.
HS_AMP AU_HSP
AU_HSM
HPR_AMP
Voice or Audio Audio AU_HPR
Digital Signal RCH-DAC
HPL_AMP
Voice or Audio Audio AU_HPL
Digital Signal LCH-DAC
LSB
Class_AB SPK_P
SPK_N
Digital MIC
I/O Signal
AU_V1N0_P
MUX
Voice PGA
Voice Signal
ADC AU_V1N0_N
MUX
MICBIAS0(1.9V)
1.2V
MICBIAS1(1.9V)
AU_V1N1_N
AU_V1N1_P
Figure
Figure 3.12.1.
3.12.1. Block
Block diagram
diagram of of audio
audio mixed-signalblocks.
mixed-signal blocks.
3.13.2
3.13.2Functional
FunctionalSpecifications
Specifications
See
Seethe
thetable
tablebelow
belowfor
forthe
thefunctional specifications
functional of voice-band
specifications uplink/downlink
of voice-band blocks
uplink/downlink blocks.
48 / 131
3. TECHNICAL BRIEF
Figure 3.12.2 Functional specifications of analog voice blocks
See the table below for the functional specifications of audio blocks.
Figure 3.13.2 Functional specifications of analog voice blocks
3. TECHNICAL BRIEF
3.13 Camera Interface
VCAMD_IO_1V8
VCAM_2V8
3. TECHNICAL BRIEF
3.13 Camera Interface Beads are deleted (12/3)
VCAM_IOVDD
VCAM_DVDD
VCAM_AVDD
CN302 VCAMD & VIO are merged to VCAMD_IO_1V8 (10/31)
1 24
CAM_DATA07 2 23 I2C_SCL1
CAM_DATA06 3 22 I2C_SDA1
CAM_DATA05 4 21
CAM_DATA04 5 20 CAM_VSYNC
CAM_DATA03 6 19 CAM_HSYNC
CAM_DATA02 7 18 CAM_F_MCLK
CAM_DATA01 8 17
CAM_DATA00 9 16
R358
10 15 CAM_MCLK 1 2 CAM_F_MCLK
CAM_F_PCLK 10
CAM_RESET 11 14 2 C361 2 C362

DNI 7.5p
0.1u
0.1u
0.1u
CAM_PD 12 13
1u
1u
1u
2 2 2 2
(DIF_D8) 1 VA312 VA313
1 1
C315
C325
C316
C324
C317
C326
1 1 1 1
2
R359
CAM_PCLK 1 2 CAM_F_PCLK
10
C364 C363
7.5p DNI
Figure 3.13.1 Camera Interface

Figure 3.13.1 Camera Interface
The YACC6A1SBDBS is a high quality 1.3mega-pixel single chip cmos image sensor for mobile phone camera
applications and digital still camera products. The YACC6A1SBDBS incorporates a 1324 X 1084 pixel array, on-
chip 10-bit ADC, and an image signal processor. Unique sensor technology enhances image quality by reducing
FPN(Fixed Pattern Noise), horizontal/vertical line noise, and random noise. The Image Signal Processor (ISP)
performs sophisticated image processing functions including color correction, lens shading correction, edge
enhancement, gamma correction, image scaling, noise reduction, auto exposure (AE), auto white balance
(AWB), anti-flicker (50Hz/60Hz, manual/Auto). The AE and AWB functions are performed by an embedded 8-bit
processor which uses to run built-in these sophisticated algorithms. The programmable functions are
controlled by host processor via 2-wire I2C bus interface. The YACC6A1SBDBS, which needs a single master
clock(48Mhz(Max)), is suitable for low power camera module with 2.8V/1.8V power supply.
3. TECHNICAL BRIEF
3. TECHNICAL BRIEF
3.13.1 FEATURES
3.13.1 FEATURES
• Optical size : 1/6 inch

• Unit pixel size : 1.75 um x 1.75 um
• Resolution : 1,280H X 1,024V
• Active image Size : 2.296mm(H) X 1.848mm(V)
• Output format : Yuv4:2:2, RGB5:6:5, ITU656-like
• Frame rate : 15fps@SXGA, 30fps@VGA, 20 fps@720P
• ADC resolution : 10-Bit
• Lens shading correction
• Color correction
• Noise reduction
• Edge enhancement
• Windowing : Programmable
• Sub-Sample : 1/2. 1/4 (VGA, QVGA)
• Gamma correction
• Image effect: Mono, Sepia, Solarization, Negative, Sketch, Embossing
• Image scaling: 1x ~ 1/64x
• Anti-flicker (50Hz/ 60Hz) : Auto/Manual
• Image Flip : X/Y Flip
• Auto exposure (AE)
• Auto white balance (AWB)
• Black Level Calibration
• Strobe Control : Support Xenon / LED Type
• On-Chip Dead Pixel Correction
• Host interface: two-wire serial bus interface
• Internal PLL
• Operating temperature: -20°C to +60°C
• Supply voltage: 2.8V / 1.8V
51 / 131
3. TECHNICAL BRIEF
3. TECHNICAL BRIEF
3.14 KEY
3.14 KEYBACLKLIGHT
BACLKLIGHTLED
LEDInterface
Interface
Key Backlight LED is controlled by KEYPAD_LED signal of MT6255.

The built-in open drain output switch drives the Keypad LED in the handset. This switch is controlled by
baseband with the enable register. The keypad LED can sink 150mA and will become high impedance as
disabled.
KEY BACKLIGHT
VBAT
WHITE Top View LED (8/13)
2 C300
2 C301 1u
1u
1
1 LD300 LD301 LD302 LD303 LD304 LD305
R357
R360
R361
R362
R363
R364
47
47
47
47
47
47
Changed (8/8)
KEY_BL0
C319
1u
Figure 3.14.1 Key Backlight Block
Figure 3.14.1 Key Backlight Block
52 / 131
3. TECHNICAL BRIEF
3. TECHNICAL BRIEF
3.15Vibrator
3.15 VibratorInterface
Interface
Vibrator is driven by MT6255.

VIBR_3V0 is connected with + terminal of vibrator and – terminal is connected with
GND. It is controlled by VIBRATOR signal of MT6255 .
VIBRATOR
VIBR_3V0
Location is changed for RSE (11/9)
VB300
L301 22n
1
(10/12) Changed
2
VA330 D301 L302

C307
1u 270n
Figure 3.15.1 Vibrator Driver Block
Changed (9/10) Added (9/10)
Figure 3.15.1 Vibrator Driver Block
53 / 131
4. TROUBLE SHOOTING
4. TROUBLE SHOOTING
4.1 RF Component
U101
U101 X102
X101
U401
SW400
Figure 4.1
U101 Main Chip (MT6255)
U400 TX Module (RF7182)
Memory(2G/1G DDR)
U100
H9DA2GH1GHMMMR-46M
X101 Crystal, 26MHz Clock
X102 Crystal, 32.768MHz Clock
4. TROUBLE SHOOTING
4.2 RX Trouble
START
HP8960 : Test mode

62 CH, 7 level setting (TCH)
62CH, -60dBm setting (BCCH)
Spectrum analyzer setting
Oscilloscope setting
(1) Check Crystal Circuit
(2) Check Mobile SW &TX module
(3) Check PLL Control
Re-download SW or
Do calibration again
4. TROUBLE SHOOTING
(1) Checking Crystal Circuit
TP1
Figure 4.2.1
W23
TXO_LB LowBand_Tx
W24
TXO_HB HighBand_Tx TP1
AA16
CLK_SEL X101
1 2
AC16 EARMIC_BIAS
XTAL1 4 3
AB16
XTAL2 VMIC_BIAS_P
TSX-3225 26MHZ_7_4PF
W15 26MHz
FREF
U23
MICBIAS1
P23
MICBIAS0
C132
1u
26 MHz No
Replace TP1
O.K?
Yes
Crystal is OK.
See next page to check PLL Circuit
4. TROUBLE SHOOTING
(2) Checking Mobile SW &Tx module
TP6
TP1
TP7
TP5
SW400
TP4 TP2
TP3
Figure 4.2.1
VBAT
TP2
Changed (9/10) TP5
C410 22u
TP4 Changed (7/27)
C408 0.1u
TP3
RF_ANT_SW2
(10V, X5R)
RF_ANT_SW1
C409 22p
RF_PA_EN
(50V) R407 10K
RF_TX_RAMP
C463 C464 C465

C407
(7/16) U400 : RF7180 -> RF7182 DNI DNI DNI

220p
R409
24K
TP1
11
10
9
8
7
VBATT
GPCTRL1
GPCTRL0
TX_ENABLE
VRAMP
Changed (11/6)
close to TXM
Shielding by GND
(7/17) 12
NC1 GND4
6
GND5 GND3
13 5 (50ohm)
C461 100p
SW400 C466 1.5n C467 2.7n
2 14
GND6 RFIN_LB
4
LowBand_Tx
ANT COMMON ANTENNA GND2
1 15 U400 3 (50ohm)
C462 100p
G3 G4 16
NC2 RFIN_HB
2
HighBand_Tx
L411 GND1
3 4
C415 L456
1 (7/3) DC Blocking
GND_SLUG
DNI 1.2p 47n

GND7
GND8
GND9
NC3
RX1
RX0
C451 C452
17
18
19
20
21
22
23
DNI DNI
component changed (12/5)
TP7
GSM1800,1900
(50ohm) GSM850,900
L451 12n
1 2 LB_RxN
10
(50ohm)
(12/28) Changed
GND4
L401
L402 2.2n Changed (9/10)
Changed (8/9) 1
GSM850/900_UnB GSM850/900_Bal2
9 33n
L452 12n
C457 2 8
GND1 GSM850/900_Bal1 1 2 LB_RxP
1p
FL400 L454 3.9n
3 7
GND2 GSM1800/1900_Bal2 HB_RxP
L405
4 6
GSM1800/1900_UnB GSM1800/1900_Bal1
2.7n L403
GND3
2 C460 6.8n Changed (9/25)

1p L455 3.9n
TP6
5
1 HB_RxN
Changed (9/26)
(7/27) (7/18) coil -> non_coil

(7/27) 0603 -> 1005
(12/28) Changed
4. TROUBLE SHOOTING
Check TP1 of SW400
No
TP1 Signal is OK? Replace Mobile SW (SW400)
Yes
Check TP2 of U400
Control Signal No
Is (TP3, 4, 5) Check MT6255(U101)
OK ?
Yes
No
TP6(High Band),
TP7(Low Band) Signal is OK ? Replace TX module (U400)
Yes
Mobile SW & TX Module is OK.

Off 0 0 0
RX 0 0 1 0
RX 1 0 1 1
GSM850/900 TX Mode 1 1 0
4. TROUBLE SHOOTING
4.3 TX Trouble
START
HP8960 : Test mode

62 CH, 7 level setting (TCH)
62CH, -60dBm setting (BCCH)
Spectrum analyzer setting
Oscilloscope setting
(1)Check
Crystal Circuit
(2) Check
Mobile SW &Tx module
(3) Check PLL Control
Redownload SW or
Do calibration again
4. TROUBLE SHOOTING
(1) Checking Crystal Circuit
TP1
Figure 4.2.1
W23
TXO_LB LowBand_Tx
W24
TXO_HB HighBand_Tx TP1
AA16
CLK_SEL X101
1 2
AC16 EARMIC_BIAS
XTAL1 4 3
AB16
XTAL2 VMIC_BIAS_P
TSX-3225 26MHZ_7_4PF
W15 26MHz
FREF
U23
MICBIAS1
P23
MICBIAS0
C132
1u
26 MHz No
Replace TP1
O.K?
Yes
Crystal is OK.
See next page to check PLL Circuit
4. TROUBLE SHOOTING
(2) Checking Mobile SW &Tx module
TP6
TP1
TP7
TP5
SW400
TP4 TP2
TP3
Figure 4.2.1
VBAT
TP2
Changed (9/10) TP5
C410 22u
TP4 Changed (7/27)
C408 0.1u
TP3
RF_ANT_SW2
(10V, X5R)
RF_ANT_SW1
C409 22p
RF_PA_EN
(50V) R407 10K
RF_TX_RAMP
C463 C464 C465

C407
(7/16) U400 : RF7180 -> RF7182 DNI DNI DNI

220p
R409
24K
TP1
11
10
9
8
7
VBATT
GPCTRL1
GPCTRL0
TX_ENABLE
VRAMP
Changed (11/6)
close to TXM
Shielding by GND
(7/17) 12
NC1 GND4
6
GND5 GND3
13 5 (50ohm)
C461 100p
SW400 C466 1.5n C467 2.7n
2 14
GND6 RFIN_LB
4
LowBand_Tx
ANT COMMON ANTENNA GND2
1 15 U400 3 (50ohm)
C462 100p
G3 G4 16
NC2 RFIN_HB
2
HighBand_Tx
L411 GND1
3 4
C415 L456
1 (7/3) DC Blocking
GND_SLUG
DNI 1.2p 47n

GND7
GND8
GND9
NC3
RX1
RX0
C451 C452
17
18
19
20
21
22
23
DNI DNI
component changed (12/5)
TP7
GSM1800,1900
(50ohm) GSM850,900
L451 12n
1 2 LB_RxN
10
(50ohm)
(12/28) Changed
GND4
L401
L402 2.2n Changed (9/10)
Changed (8/9) 1
GSM850/900_UnB GSM850/900_Bal2
9 33n
L452 12n
C457 2 8
GND1 GSM850/900_Bal1 1 2 LB_RxP
1p
FL400 L454 3.9n
3 7
GND2 GSM1800/1900_Bal2 HB_RxP
L405
4 6
GSM1800/1900_UnB GSM1800/1900_Bal1
2.7n L403
GND3
2 C460 6.8n Changed (9/25)

1p L455 3.9n
TP6
5
1 HB_RxN
Changed (9/26)
(7/27) (7/18) coil -> non_coil

(7/27) 0603 -> 1005
(12/28) Changed
4. TROUBLE SHOOTING
Check TP6 & TP7
No
TP6, TP7 Signal is OK ? Replace MT6255 (U101)
Yes
No
Control Signal is Check MT6255 (U101)
(TP3,4,5) OK ?
Yes
Check TP1 of U400 ?
No
TP1 Signal is OK? Replace TX module (U400)
Yes
No
TP8 signal same as TP1? Replace SW400
Yes
Mobile SW & TX module is OK.

Off 0 0 0
RX 0 0 1 0
RX 1 0 1 1
GSM850/900 TX Mode 1 1 0
4. TROUBLE SHOOTING
4.4 Power On Trouble
TP1 (U101)
TP2 1K Ω
Figure 4.4.1
U9
GND_20
U2
GND_21
E18
SIM2_CLK SCLK2
D20
SIM2_DATA SIO2
C20
SIM2_RST SRST2
D19
SIM_CLK SCLK
E19
SIM_DATA SIO
D18
SIM_RST SRST
TP2 1K Ω
Close to IC TP1 (U101)
H20
RST_N RESETB
R108 1K G21
END_KEY PWRKEY
1 C126 1u 2 F20
C125 VREF
F21
AVSS43_VRF
330p
J22
PMU_TESTMODE
G20
VCDT
H22
CHRLDO
G22
Figure 4.4.2
4. TROUBLE SHOOTING
START
No
Check Battery Voltage Charge or Change Battery
> 3.30V
Yes
Push power-on key No

Check the contact of power key
And check the level change
Or dome-switch
into high of PWRKEY
Yes
Check the voltage of No

resistors at R107 when pushing power Replace TP1 (U100)
key
Yes
No
Logic level at PWRON of TP2 Re-download software
= HIGH(above 1.2V)?
Yes
No
Is the phone power on? Replace TP1 (U100) and
Re-download software
Yes
Does it work properly?
Yes
No
The phone will Properly operate. Replace the main board
4. TROUBLE SHOOTING
4.5 Charging Trouble
TP2
TP1
RT9536 CN201
USB Connector
Figure 4.5.1
VUSB_LDO_4V9 VBUS_USB VBAT VIO_1V8

R271
100K
11
PGND
1 10
VIN BATT
2 9
TP2 3
ISET U204 PGB
8
4
GND1 CHGSB
7
EOC
LDO GND2
5 6
IEOC EN_SET CHG_EN
C289
R276
R277
R274
C275
DNI
820
3K
0.1u 0.1u
50V internal voltage (10/31)
4. TROUBLE SHOOTING
VBUS_USB
AVDD_2V8
Line Width: 2mm
Added for low voltage surge (12/3)

CN201(TP1)
R275
Changed (8/28) 240K C269 C268 Changed (10/12)
D202
1u 22pF CN201
6
7
8
Changed (8/27) 25V --> 50V (9/10) Line Width: 2mm 1
2
USB_DM
3
USB_DP
4
ACC_ID 5
D201 9
4
C295 C272 10
ID
DP
DM
VBUS
11
MTK recommend (9/10) 0.1u 22p
GND1
GND2
5
Changed for Low voltage surge (12/3)
LGE Internal Use Only

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Service Manual: Internal Use Only

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Service Manual: Internal Use Only

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Internal Use Only

Date: April, 2013 / Issue 1.0

1.2 Regulatory Information

G. Interference and Attenuation

H. Electrostatic Sensitive Devices

which is also grounded.

• Use a suitable, grounded soldering iron.

APC Automatic Power Control

BER Bit Error Ratio

CC-CV Constant Current – Constant Voltage

DAC Digital to Analog Converter

DCS Digital Communication System

dBm dB relative to 1 milli watt

DSP Digital Signal Processing

EEPROM Electrical Erasable Programmable Read-Only Memory

ESD Electrostatic Discharge

FPCB Flexible Printed Circuit Board

GMSK Gaussian Minimum Shift Keying

GPIB General Purpose Interface Bus

GSM Global System for Mobile Communications

IPUI International Portable User Identity

LCD Liquid Crystal Display

LDO Low Drop Output

LED Light Emitting Diode

OPLL Offset Phase Locked Loop

PAM Power Amplifier Module

PCB Printed Circuit Board

PGA Programmable Gain Amplifier

PLL Phase Locked Loop

PSTN Public Switched Telephone Network

RLR Receiving Loudness Rating

RMS Root Mean Square

RTC Real Time Clock

SAW Surface Acoustic Wave

SIM Subscriber Identity Module

SLR Sending Loudness Rating

SRAM Static Random Access Memory

PSRAM Pseudo SRAM

STMR Side Tone Masking Rating

TDD Time Division Duplex

TDMA Time Division Multiple Access

UART Universal Asynchronous Receiver/Transmitter

VCO Voltage Controlled Oscillator

VCTCXO Voltage Control Temperature Compensated Crystal Oscillator

WAP Wireless Application Protocol

Item Feature Comment

Standard Battery Lithium Ion, 3.7V 1500mAh

Stand by TIME >993 hr., Min.@PP9

Stand by time >1145 hr., Min.@PP5

>8.0hr., Min.@GSM900, PL=5

Charging time Approx. 3 hours 30 min.

RX Sensitivity GSM, EGSM: -109dBm, DCS: -109dBm

GSM, EGSM: 32.3dBm(Level 5),

GPRS compatibility Class 10

SIM card type 3V Small

Display MAIN : TFT 320 × 240(QVGA) pixel 262K Color

KEY TOTAL 22EA

EAR Phone Jack Yes(3.5Ø)

Speech coding EFR/FR/HR

Data and Fax Yes

Loud Speaker Yes

Voice Recoding Yes

Item Feature Comment

Speaker/Receiver 18 x 10 (Speaker & Receiver Dual Mode Assembly)

Travel Adapter Yes