Вы находитесь на странице: 1из 448

32-

19861, 19861, 19861, 19861QI, 198614


99

67

100

66

19861
XXYY

132

34
1

* 144 ;
62 ;
32 32
, 3 ;
,
;

CAN;
8- 12- ;
2 12- ;
14
;

3,03,6 ;

33

XX
YY

:
19861

60 125

19861
19861
19861QI

60 125
0 70
40 85

* 3 (140 1 2)

:
132- 4229.132-3;
144- LQFP144;
198614 .

.431296.008C

2.8.1 19.02.2015

19861, 19861, 19861, 19861QI, 198614


:
32- RISC , 144 ( 3),
0.8 DMIPS/MHz ;
32 x 32 .
:

FLASH- 128 ;
48 ;
,
, NAND Flash.

3,03,6 ;
1,8 ;
;
;
RC 8 ;
RC 40 ;
2 16 ;
20 30 ( 2 );
32 ;
PLL ;
PLL USB.

12- ( 8 ) 03,6 ;
12- ;
32- ( 16 );
.

-,
-;
CAN ;
18977-79;
52070-2003;
Ethernet 10/100 PHY Transceiver;
USB Device Host;
2UART, 3SPI;
96 /.

SWD JTAG.

19861, 19861, 19861, 19861QI, 198614

.............................................................................................................2
1
................................................................................................................................7
2
- ...................................................................................8
3
.................................................................................................................9
4
Stand Alone .............................................................................12
5
...................................................................15
6
...........................................................................................................16
7
.....................................18
8
............................................................................................................20
8.1
Code .................................................................................................................. 22
8.2
Internal SRAM .................................................................................................... 22
8.3
Peripheral........................................................................................................... 22
8.4
External SRAM External device ....................................................................... 22
8.5
Private Peripheral Bus ........................................................................................ 22
8.6
BUS MATRIX ......................................................................................................... 22
8.7
EEPROM ........................................................................................................... 23
8.8
SRAM ................................................................................................................ 23
8.9
, ................................................................................ 23
8.10 .................................................................. 24
8.11 ................................................................................... 25
8.12 .......................... 25
8.13 ......................................................................................... 27
9
....................................................28
10 FLASH .................................................................................34
10.1 Flash .................................................... 34
10.2 Flash .................................... 35
10.3 Flash ..................... 40
11 .............................................................................................................43
11.1 .................................................................................................... 46
11.2 ................................................................................................................................ 46
11.3 ............................................................................................................... 46
11.4 .................................................................................................................. 51
12 ...................................................................................................................52
12.1 ..................................................................................................... 54
12.2 .................................................................................................... 55
12.3 ........................................................................................... 61
12.4 ..................................................................................... 68
12.5 ................................................................................................. 75
12.6 .......................................................................... 76
12.7 ................................................................................ 77
12.8 ........................................................................................................ 79
13 ..................................................................................................83
13.1 RC HSI..................................................................................... 83
13.2 RC LSI ...................................................................................... 84
13.3 HSE ............................................................................................ 84
13.4 LSE ............................................................................................. 84
13.5 ........................................ 84
13.6 USB ..................... 84
13.7 ........................................ 85
14 ..................................................................98
14.1 .............................................................................................. 98
14.2 ................................................................................ 99
14.3 ......................................................... 99
15 /.......................................................................................................... 106

19861, 19861, 19861, 19861QI, 198614


15.1 / ................................................................ 109
16 .......................................................................................... 113
17 ................................................................................................. 115
17.1 , ...... 115
17.2 NAND Flash .................................................................... 117
17.3 ........................ 121
18 Stand Alone ............................................................................................................. 126
19 USB ........................................................................................... 128
19.1 ............................................................ 128
19.2 USB / .................... 128
19.3 ................................................. 129
19.4 IN (Usb Device) ......................................................................................... 129
19.5 SETUP/OUT (Usb Device) ........................................................................ 130
19.6 SETUP/OUT (Usb Host) ............................................................................ 131
19.7 IN (Usb Host) ............................................................................................ 132
19.8 SOF (Usb Host) ................................................ 133
19.9 USB .......................... 134
20 CAN ........................................................................................... 153
20.1 ........................................................................................................... 154
20.2 ............................................................................................ 155
20.3 (Data Frame) ...................................................................... 156
20.4 ............................................................................................................ 161
20.5 .................................................................................................. 161
20.6 Remote Transmit Request (RTR) ........................................ 161
20.7 ....................................................................................................... 161
20.8 .......................................... 162
20.9 .............................................................................. 162
20.10 ........................................... 162
20.11 ............................................................................................................ 163
20.12 ....................................................................................................... 164
20.13 ................................................................................................................. 167
20.14 CAN ...................................................................... 168
21 52070-2003 ............................................................. 177
21.1 ........................................................................................................... 178
21.2 ................................................................................................... 179
21.3 ................................................................................................................ 180
21.4 ............................................................................................................ 185
21.5 ................................................................................. 185
21.6 ................................................................................. 186
21.7 ................................................................................................................. 187
21.8 52070-2003 ............................................. 187
22 ............................................................................................ 196
22.1 ...................................................................................................... 196
22.2 .............................................................................................................. 199
22.3 ....................................................................................... 201
22.4 ............................................................................................................. 207
22.5 ................................................................................................................. 209
22.6 ...................................................................................................................... 211
22.7 ........................................................................... 214
23 ( 1)............................................................................................. 226
23.1 ............................................................................. 227
23.2 ......................................... 227
23.3 ......................................................................... 228
23.4 ...................................................................................... 228
23.5 .................................................................................................... 228
23.6 ............................................................................ 229
23.7 ........................................................... 230

19861, 19861, 19861, 19861QI, 198614


24 ( 2)............................................................................................. 235
24.1 ............................................................................. 236
24.2 ......................................... 236
24.3 ......................................................................... 237
24.4 ...................................................................................... 237
24.5 .................................................................................................... 237
24.6 ............................................................................ 238
24.7 ........................................................... 239
25 ................................................................................................................ 244
25.1 ........................................................... 245
26 18977-79 .................................................................... 247
26.1 .............................................................................................................. 248
26.2 ......................................................................... 251
26.3 18977-79 .................................................... 252
27 SSP................................................................................................................. 268
27.1 SSP ..................................................................... 268
27.2 ................................................................................... 270
27.3 SPI ................................................................................ 270
27.4 Microwire ...................................................................... 270
27.5 SSI ................................................................................ 270
27.6 SSP .......................................................................................... 270
27.7 ....................................................................... 286
27.8 ........................................................................... 288
27.9 ................................................................................................................. 294
28 UART .............................................................................................................. 296
28.1 UART ................................................................... 296
28.2 ................................................................................... 297
28.3 UART 16C650 ..................................................................... 297
28.4 ................................................................................... 297
28.5 UART ................................................................ 299
28.6 IrDA SIR .................................................... 301
28.7 UART .............................................................................................. 303
28.8 ....................................................................................... 308
28.9 ....................................................................... 310
28.10 ................................................................................................................. 312
28.11 ........................................................................... 315
28.12 ........................................................... 316
29 DMA .................................................................... 332
29.1 DMA ..................................................................... 332
29.2 ............................................................................................. 332
29.3 .......................................................................................... 334
29.4 DMA ......................................................................................................... 338
29.5 .................................................................... 357
29.6 DMA ..................................................................... 367
30 Ethernet ..................................................................................... 383
30.1 .......................................................................................................... 384
30.2 ..................................................................................... 384
30.3 ............................................................................................................... 385
30.4 ........................................................................................ 385
30.5 ............................................................................. 385
30.6 ................................................................... 386
30.7 FIFO ..................................................................................... 386
30.8 ............................................................................ 386
30.9 ................................................................................................................. 386
30.10 ........................................................ 387
30.11 ..................................................................................................................... 387
30.12 .......................................................................................................... 387

19861, 19861, 19861, 19861QI, 198614


30.13 ...................................................................................................................... 388
30.14 PHY...................................................................................................................... 397
31 ................................................................................................ 407
31.1 ........................................................................................................ 408
31.2 ............................................................................................... 409
31.3 ...................................................................................................... 409
31.4 .............................................................................................................................. 410
31.5 ................................................................. 411
31.6 .................................................................................................. 412
31.7 (late-arriving) ........................................................................................ 413
31.8 ............................................................................ 413
31.9 ........................................................................................................ 414
31.10 Lock-up ......................................................................................................................... 415
32 NVIC .......................................................................................... 417
32.1 NVIC ......................................................................................... 417
32.2 ............................................................................... 418
32.3 ...................................................................................... 418
32.4 ..................... 419
32.5 ................................................. 419
32.6 ................................................................................ 420
32.7 .......................................................................... 420
32.8 ................................................................... 421
32.9 ............................................................... 421
33 ....................................................................................... 422
33.1 (ACTLR) .................................................... 422
33.2 SysTick (CTRL) .......................................................... 423
33.3 SysTick (LOAD) ................................................... 424
33.4 SysTick (VAL) ................................................................. 424
33.5 SysTick (CALIB)................................................... 425
33.6 CPUID ............................................................................................................. 425
33.7 (ICSR) ............................................... 426
33.8 (AIRCR) ................... 428
33.9 (CCR) .............................................................. 429
33.10 ........................................................ 429
33.11 2 (SHP2) ............................................ 429
33.12 3 (SHP3) ............................................ 430
33.13 (SHCSR) ....................... 430
34 ........................................................................................................ 431
34.1 .................................................... 431
35 - ..................................................... 435
36 ........................................................................... 437
37 .......................................................................................................... 439
38 ........................................................................................................ 441
39 ...................................................................................... 444
40 .................................................................................................... 446
.................................................................................................... 447

19861, 19861, 19861, 19861QI, 198614

,
-
RISC . 144
128 - 48 .
USB
12 / (Full Speed) 1,5 / (Low Speed), UART
SPI, 18977-79 52070-2003,
Ethernet 10/100 , MII
, ,
, NAND Flash

32- 4
. 24 .

12- ( 512 /)
8 , .
12- .
RC HSI (8 ) LSI (40 ), HSE
(216 ) LSE (32 ) PLL USB
.


. DMA
.
,
, 1,8
. ,
3,0 3,6 .
, ,

.

.
.

19861, 19861, 19861, 19861QI, 198614

1 -

19861, 19861, 19861, 19861QI, 198614


.
- -

4229.132-3 LQFP144

PA0 /
MODE[0]
PA1 /
MODE[1]
PA2 /
MODE[2]
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15

127

137

143

A
-

D0

EXTINT1

ETR1

126

136

142

D1

EXTINT2

ETR2

125

135

141

D2

EXTINT3

ETR3

124
123
122
121
120
119
118
115
114
113
112
111
110

134
133
132
131
130
129
128
124
123
122
121
120
119

140
139
138
137
136
135
134
129
128
127
126
125
124

D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15

EXTINT4
BRK2
BRK3
TMR4_CH1
TMR4_CH1N
TMR4_CH2
TMR4_CH2N
TMR4_CH3
TMR4_CH3N
TMR4_CH4
TMR4_CH4N
BRK4
ETR4

BRK1
FRX
FSD
FXEN
FTX
PRMC+
PRMCPRMD+
PRMDPRDC+
PRDCPRDD+
PRDD-

PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15

109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94

118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103

123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108

D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31

IN1+
IN1IN2+
IN2IN3+
IN3IN4+
IN4IN5+
IN5IN6+
IN6IN7+
IN7IN8+
IN8-

TMR3_CH1
TMR3_CH1N
TMR3_CH2
TMR3_CH2N
TMR3_CH3
TMR3_CH3N
TMR3_CH4
TMR3_CH4N
TMR1_CH1N
TMR2_CH1N
TMR1_CH2N
TMR2_CH2N
TMR1_CH3N
TMR2_CH3N
TMR1_CH4N
TMR2_CH4N

PC0
PC1
PC2
PC3

89
90
91
92

98
99
100
101

103
104
105
106

B
C
-

ETR1
ETR2
CLKO
CLE

BRK1
BRK2
BRK3
SIR_OUT1

PC4

93

102

107

BUSY

SIR_IN1

PC5
PC6
PC7
PC8
PC9

56
57
58
59
60

61
62
63
64
65

65
66
67
68
69

nWR
nRD
ALE
UART_TXD
1
UART_RXD
1
EXTINT1
EXTINT2
EXTINT3
EXTINT4
SSP2_TXD

SSP1_TXD
SSP1_RXD
SSP1_SCK
SSP1_FSS
BE0

SSP1_RXD
SSP1_TXD
FXEN
FTX
CAN_RX1

19861, 19861, 19861, 19861QI, 198614


PC10
PC11
PC12
PC13
PC14
PC15

61
62
63
67
68
69

66
67
68
72
73
74

70
71
72
76
77
78

PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7

72
73
74
75
76
77
78
41

81
82
83
84
85
86
87
46

86
87
88
89
90
91
92
50

PD8

42

47

51

PD9
PD10
PD11
PD12
PD13

43
44
45
46
47

48
49
50
51
52

52
53
54
55
56

D
ADC0_RE
F+
ADC1_RE
FADC2
ADC3
ADC4
ADC5
ADC6

PD14

48

53

57

ADC7

PD15

49

54

58

PE0
PE1
PE2
PE3
PE4
PE5
PE6

50
51
52
16
17
18
34

55
56
57
18
19
20
37

59
60
61
20
21
22
39

PE7

35

38

40

PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15

19
20
21
22
23
24
25
26

21
22
23
24
25
26
27
28

23
24
25
26
27
28
29
30

REFD0
E
REFD1
DAC0
DAC1
OSC_IN3
2
OSC_OU
T32
F

PF0

27

29

31

PF1

28

30

32

PF2

29

31

33

PF3
PF4
PF5
PF6
PF7

79
80
81
82
83

88
89
90
91
92

93
94
95
96
97

SSP2_RXD
SSP2_SCK
SSP2_FSS
PRMA+
PRMAPRMB+

BE1
BE2
BE3
A30
A31
BUSY

CAN_TX1
CAN_RX2
CAN_TX2
UART_TXD2
UART_RXD2
TMR2_CH1

PRMBPRDA+
PRDAPRDB+
PRDBPRD_PRMA
PRD_PRMB
SSP2_TXD

ALE
CLE
SSP1_TXD
SSP1_RXD
SSP1_SCK
SSP1_FSS
nUART2RI
nUART2DCD

A16
A15
A14
A13
A7
A6
A5
A4

SSP2_RXD

nUART2DTR

A3

SSP2_SCK
SSP2_FSS
A0
SSP3_TXD
UART_TXD
2
UART_RXD
2
OUT3+

nUART2DSR
nUART2RTS
nUART2CTS
ETR3
OUT1+

A2
A1
FRX
SSP3_RXD
SIR_OUT2

OUT1-

SIR_IN2

A13

FSD

OUT4+
OUT3OUT4TMR1_CH1
TMR1_CH2
TMR1_CH3
TMR1_CH4

A14
A15
A16
A17
A18
A19
A20

MDC
nUART2RI
MDIO
TXD[0]
TXD[1]
TXD[2]
TXD[3]

TMR2_CH1

A21

RXD[0]

TMR2_CH2
TMR2_CH3
TMR2_CH4
CAN_RX1
CAN_TX1
CAN_RX2
CAN_TX2
PRD_PRMD

A22
A23
A24
A25
A26
A27
A28
A29

RXD[1]
RXD[2]
RXD[3]
TXEN
TXER
TXCLK
RXCLK
RXDV

OSC_IN2 PRD_PRMA READY


5
OSC_OU PRD_PRMB A30
T25
READY
A31
/PRD_PRM
C
PRMC+
A0
PRMCA1
PRMD+
A2
PRMDA3
PRDC+
A4

RXER
CRS
COL

TMR1_CH1
TMR1_CH2
TMR1_CH3
TMR1_CH4
OUT4+

10

19861, 19861, 19861, 19861QI, 198614


PF8
PF9
PF10
PF11
PF12
PF13
PF14
PF15

84
85
86
87
88
64
65
66

nRESET 55
OSC_IN 53
OSC_OUT54
WAKEUP 36
ITCMLAE 15
N

DP
DN

37
38

TXP
TXN
RXP
RXN
EXRES1

3
2
7
6
10

CM

Ucc
AUcc

31, 71, 117


40

VDD1AVDD4A
BUcc
GND
AGND
VSS1AVSS4A

5, 8, 12, 14

TMS
TDI
TDO
TCK
TRST
JTAGEN

128
129
130
131
132
33

32
30, 70, 116
39
1, 4, 9, 11,
13

SHDN
EXT_POR RST_BYP VPP
TM0
TM1
TM2
VDD
TSTBUSA -

93
94
95
96
97
69
70
71

98
99
100
101
102
73
74
75

PRDCA5
OUT4PRDD+
A6
OUT3+
PRDDA7
OUT3PRD_PRMC A8
OUT2+
PRD_PRMD A9
OUT2OUT2+
A10
SSP3_FSS
OUT2A11
SSP3_SCK
SSP3_RXD A12
SSP3_TXD

60
64

58
62
HSE
59
63
HSE
39
41
Standby
17
19
:
1- ;
0- .
USB
42
44
USB D+
43
47
USB DPHY Ethernet
3
3

2
2
8
8

7
7
12
13
12,4
1% VSS2A
6
6

33,76,127
35, 80, 133 3,03,6
45
49
, A, PLL 3,03,6
( Ucc)
5,10,14,16
5, 10, 16,
PHY 3,03,6
18
34
36
1,83,6
32,75,125
34, 79, 131
44
48
, , PLL
1,4,11,13,15 1, 4, 12, 15, PHY
17
JTAG
138
144
139
145
140
146
141
147
142
148
35
37
TAP
JTAG.
.

40
42

41
43

126
132

77
82

79
84

78
83

80
85

36
38

9
9

A, B, C, D, E, F /
RESET, OSC_IN, WAKEUP, ITCMLAEN, JTAGEN
OSC_OUT

11

19861, 19861, 19861, 19861QI, 198614

Stand Alone
2 Stand Alone

- -

4229.132-3 LQFP144

DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15

127
126
125
124
123
122
121
120
119
118
115
114
113
112
111
110

137
136
135
134
133
132
131
130
129
128
124
123
122
121
120
119

143
142
141
140
139
138
137
136
135
134
129
128
127
126
125
124

ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
nBE_ET
H0
nBE_ET
H1
nCE1

109
108
107
106
105
104
103
102
101
100
99
98
97

118
117
116
115
114
113
112
111
110
109
108
107
106

123
122
121
120
119
118
117
116
115
114
113
112
111

96

105

110

byte enable1 Ethernet

95

104

109

nCE2

94

103

108

chip enable 1
Ethernet
52070-2003
chip enable 2
Ethernet
52070-2003

nWE
nOE
RDY_ET
H
ADDR12
DATA16
DATA17

89
90
91

98
99
100

103
104
105

92
93
56

101
102
61

106
107
65

byte enable0 Ethernet

C


/
Ethernet


52070-2033

12

19861, 19861, 19861, 19861QI, 198614



- -

4229.132-3 LQFP144
DATA18 57
62
FXEN /
58
63
INT1
FTX
/INT2

59

64

PRMA+
PRMAPRMB+

60
61
62
63
67
68
69

65
66
67
68
72
73
74

PRMB-

72

81

PRDA+
PRDAPRDB+
PRDBPRD_PR
MA
PRD_PR
MB

73
74
75
76
77

82
83
84
85
86

78

87

41
42
43
44
45
46

46
47
48
49
50
51

FSD

47
48
49

52
53
54

MDC

50

55

ETH_INT
MDIO
TXD[0]
TXD[1]
TXD[2]
TXD[3]
RXD[0]
RXD[1]
RXD[2]
RXD[3]
TXEN
TXER
TXCLK
RXCLK
RXDV

51
52
16
17
18
34
35
19
20
21
22
23
24
25
26

56
57
18
19
20
37
38
21
22
23
24
25
26
27
28

FRX
FXEN
FTX

66
67
PHY

52070-2003
68
PHY
520702003
69
70
71
72
76

52070-2003
77
78

52070-2003
D
86

52070-2003
87

52070-2003
88
89

52070-2003
90
91

52070-2003
92

52070-2003
50
51
52
53
54
PHY
55
PHY (
3)
56
PHY ( 3)
57
58

PHY
E
59
MII Ethernet ,
PHY
60
Ethernet
61
MII Ethernet ,
PHY.
20
PHY
21

22
39
40
23
24
25
26
27
28
29
30

13

19861, 19861, 19861, 19861QI, 198614


- -

4229.132-3 LQFP144

F
MII Ethernet ,
PHY

RXER
CRS
COL
PRMC+
PRMCPRMD+
PRMDPRDC+
PRDCPRDD+
PRDDPRD_PR
MC
PRD_PR
MD
-

27
28
29
79
80
81
82
83
84
85
86
87

29
30
31
88
89
90
91
92
93
94
95
96

31
32
33
93
94
95
96
97
98
99
100
101

88

97

102

64
65
66

69
70
71

73
74
75

nRESET
OSC_IN
OSC_OU
T
WAKEUP
ITCMLAE
N

55
53
54

60
58
59

64
62
63

36
15

39
17

41
19

TXP
TXN
RXP
RXN
EXRES1

3
2
7
6
10

CM

Ucc
AUcc

31,71,117
40

VDD1AVDD4A
BUcc
GND
AGND
VSS1AVSS4A

5,8,12,14

34
32,75,125
44
1,4,11,13,1
5

36
34, 79, 131
48
1, 4, 12, 15,
17

32
30,70,116
39
1,4,9,11,13


52070-2003

52070-2003

52070-2003

52070-2003

52070-2003

52070-2003



HSE
HSE

Standby
Eternet,
52070-2003
PHY Ethernet
3
3

2
2
8
8

7
7
12
13
12,4
1% VSS2A
6
6

33,76,127 35, 80, 133


3,03,6
45
49
, A, PLL 3,03,6
( Ucc)
5,10,14,16 5, 10, 16, 18 PHY 3,03,6
1,83,6

SRAM 50 .

14

19861, 19861, 19861, 19861QI, 198614

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

68

33

67
66

69

32
65

70

31

64

71

30

63

72

29

62

73

28

61

74

27

60

75

26

59

76

25

58

77

24

57

78

23

56

79

22

55

80

21

54

81

20

53

82

19

52

83

18

51

84

17

50

85

16

49

86

15

48

87

14

47

88

13

46

89

12

45

90

11

44

91

10

43

92

42

93

41

94

40

95

39

96

38

97

37

36

98

35

99

34

PB10
PB11
PB12
PB13
PB14
PB15
PC4
PC3
PC2
PC1
PC0
PF12
PF11
PF10
PF9
PF8
PF7
PF6
PF5
PF4
PF3
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Ucc
GND
PC15
PC14
PC13

PE6
PE7
WAKE
DP
DN
AGND
AUcc
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PE0
PE1
PE2
OSC_IN
OSC_OUT
nRESET
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PF13
PF14
PF15

VSS1A
TXN
TXP
VSS1A
VDD1A
RXN
RXP
VDD2A
VSS2A
EXRES1
VSS3A
VDD3A
VSS4A
VDD4A
ITCMLAEN
PE3
PE4
PE5
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PF0
PF1
PF2
GND
Ucc
BUcc
JTAGEN

131

132

TRST
TCK
TDO
TDI
TMS
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
Ucc
GND
PA10
PA11
PA12
PA13
PA14
PA15
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9

2 132-x 4229.132-3

15

19861, 19861, 19861, 19861QI, 198614

.
Ucc :
, , USB PHY .
3,0 3,6 .
Bucc :
Ucc LSE .
Ucc 2,0 .

4 Ucc 2,0 .
1,8 3,6 . ,
Bucc Ucc.
Aucc : , , PLL
, .
, Ucc,
.
2,4 3,6 .
2,2 2,4 , .
GND : .
AGND : .
GND,
.

16

19861, 19861, 19861, 19861QI, 198614


DUcc

2,0...3,6

Ucc

3,3 -> 1,8

2*

/,
USB PHY,

HSI, LSI HSE,

BUcc

1,8...3,6

PVD

LSE

SW

BDUcc

GND

AUcc
4

AGND

AUcc
5*
AGND


PLL

3 -
:
* -
1. 1 = 22 , 2 = 3 = 4 = 5 = 0,1 ;
2. , Bucc
Ucc;
3. USB, Ucc
3,0 3,6 ;
4. , Ucc (Aucc)
2,4 3,6 ;
,
.

17

19861, 19861, 19861, 19861QI, 198614

POR
, Ucc , 2,0 ,
POR ; POR
~ 4 , ,
POR , .

2,0

~4

Ucc

POR
4

Ucc 2,0 POR
.
POR Bucc
Ucc.
Ucc
Ducc
. .

nRESET,
. nRESET ,
.

nRESET

IWDG
WWDG

&

5 -

18

19861, 19861, 19861, 19861QI, 198614

nRESET 10
.
200 , .
20 .
>200
nRESET

<10
>20

19

19861, 19861, 19861, 19861QI, 198614


Bus Matrix
S
M

2-1

Ethernet 10/100

2-1

SRAM
(Data)

2-1

External System Bus


(Program & Data)

2-1

AHB 2 APB
Bridge
(Data)

S
ITCM

DTCM
AHB-Lite (S)

EEPROM
(Program)

SRAM
(Data)

S
M
S

DMA Bus (M)


M

7
:
ITCM Bus ,
;
DTCM Bus , ;
AHB-Lite
.
(DMA),
DMA Bus.

4 .
.

20

19861, 19861, 19861, 19861QI, 198614


0xFFFFFFFF

0xE00FFFFF
0xE00FF000
0xE0042000
0xE0041000
0xE0040000
0xE000F000
0xE000ED00
0xE000E000
0xE0003000
0xE0002000
0xE0001000
0xE0000000

ROM Table

Reserved

Reserved
Reserved

private peripheral bus

Reserved

0xE0100000
0xE0000000
0xDFFFFFFF

Reserved
Debug control


AHB-Lite

NVIC
Reserved
BP

External device
1 GB

DW
Reserved

0xA0000000
0x9FFFFFFF


AHB-Lite
External SRAM
1 GB

0x60000000
0x5FFFFFFF
0x5FFFFFFF
0x50000000
0x40000000
0x30000000

External Peripheral
Peripheral registers
Ethernet SRAM & registers

0x40000000
0x3FFFFFFF

0x20200000
0x20100000
0x20000000


AHB-Lite

Peripheral
0.5 GB

AHB-Lite SRAM 16KB


DTCM SRAM 32KB

Internal SRAM
0.5 GB

:
AHB-Lite
DTCM
0x20000000
0x1FFFFFFF

Code
0.5 GB

0x1FFFFFFF

:
AHB-Lite
ITCM

External code
0x10100000
0x1000FFFF

0x00000000
ITCM (Upper Alias)

0x10000000
0x0FFFFFFF
External code
0x00100000
0x00000000

ITCM EEPROM 128KB

21

19861, 19861, 19861, 19861QI, 198614

8.1

Code

ITCM EEPROM:
,
.
.
External code:
AHB-Lite .
,
.

8.2

Internal SRAM

DTCM SRAM:
, .
(stack) (heap) .
.
AHB-Lite SRAM:
AHB-Lite .
, AHBLite.
Ethernet SRAM & registers:
AHB-Lite
Ethernet. ,
AHB-Lite.

8.3

Peripheral
Peripheral registers:
.

External Peripheral:

.
, .

8.4

External SRAM External device

AHB-Lite
.
,
.

8.5

Private Peripheral Bus


.

8.6

BUS MATRIX

BUS MATRIX AHB-Lite DMA Bus


.
. ,

22

19861, 19861, 19861, 19861QI, 198614


. ,
. .
AHB-Lite,
DMA Bus. ,
,
.
.
, .

8.7

EEPROM

EEPROM

. EEPROM 40 .
100
5 .
1 .
EEPROM
EERPOM.

8.8

SRAM

SRAM .
SRAM 1 .

8.9

.
,
.
.

:
Normal
Device
Strongly-ordered ( )
Normal

.
Device

Device Strongly-ordered.
Strongly-ordered

.
Device Strongly-ordered
, Device ,
Strongly-ordered.
:
Shareable ( )
Execute Never XN ( )

23

19861, 19861, 19861, 19861QI, 198614

Shareable
Shareable

, , DMA.

Strongly-ordered Shareable.

, Shareable,
.
Execute Never (XN)
().
XN Hard fault.

8.10
,
, ,
, , ,
, .
, ,
, ,
(memory
barrier instruction), .
.

Device Strongly-ordered. 1 2,
1 2 , ,
, , 3 .
3
2
1
Normal
Device, non-shareable
Device, shareable
Strongly-ordered

Normal
-

Device
non-shareable shareable
<
<
<
<

Strongly-ordered
<
<
<

- ,
, < ,
1 2.

24

19861, 19861, 19861, 19861QI, 198614

8.11
4.
4

0000000000000FFFFF


Code, ITCM,
Lower Alias

Normal

XN

00010000000FFFFFFF
0x100000000x1000FFFF

Code, external

Normal

Code, ITCM,
Upper Alias

Normal

0x100100000x1FFFFFFF
0200000000200FFFFF

Code, external

Normal

SRAM, DTCM

Normal

XN

0x201000000x3FFFFFFF
04000000005FFFFFFF

SRAM

Normal

Peripheral

Device

XN

06000000009FFFFFFF
000000000DFFFFFFF

External SRAM

Normal

External
Device

Device

XN

0E00000000E00FFFFF

Private Peripheral
Bus

Stronglyordered

XN

0E01000000FFFFFFFF

XN

ITCM
, ITCMLAEN
. ITCMLAEN
,
.

.
ITCM
, ITCMUAEN
. ITCMUAEN
,
.

.
DTCM
.
.

.

.


.

.


NVIC,
system timer

8.12


, :

, ;
;
;

.
,
. ,

25

19861, 19861, 19861, 19861QI, 198614


,
.
:
DMB
Data Memory Barrier (DMB) ,
.
DMB.
DSB
Data Synchronization Barrier (DSB) ,

. DSB.
ISB
Instruction Synchronization Barrier (ISB) ,
.
ISB.
, , :
.
, ISB .
,
.
.
, DSB
. ,
.
.
,
DSB . ,
DSB .

.
, ,
DMB .
,
, .
Strongly-ordered,
(NVIC, System Timer ) DMB .

26

19861, 19861, 19861, 19861QI, 198614

8.13
5

0x0000_0000
0x0010_0000
0x2000_0000
0x2010_0000
0x3000_0000

0x4000_0000
0x4000_8000
0x4001_0000
0x4001_8000
0x4002_0000
0x4002_8000
0x4003_0000
0x4003_8000
0x4004_0000
0x4004_8000
0x4005_0000
0x4005_8000
0x4006_0000
0x4006_8000
0x4007_0000
0x4007_8000
0x4008_0000
0x4008_8000
0x4009_0000
0x4009_8000
0x400A_0000
0x400A_8000
0x400B_0000
0x400B_8000
0x400C_0000
0x400C_8000
0x400D_0000
0x400D_8000
0x400E_0000
0x400E_8000
0x400F_0000
0x400F_8000
0x5000_0000
0x6000_0000
0xA000_0000
0xE000_0000


EEPROM
Flash
BOOT ROM

External code


DTCM SRAM

AHB-Lite SRAM

Ethernet

Ethernet

CAN1
CAN1
CAN2
CAN2
USB
USB
EEPROM_CNTRL Flash
RST_CLK

DMA

UART1
UART1
UART2
UART2
SPI1
SSP1
MIL-STD-1553B1

MIL-STD-1553B 1
MIL-STD-1553B2

MIL-STD-1553B 2
POWER

WWDT

WWDT
IWDT
IWDT
TIMER1
1
TIMER2
2
TIMER3
3
ADC

DAC

TIMER4
4
SPI2
SSP2
PORTA

PORTB
B
PORTC
C
PORTD
D
PORTE
E
ARINC429R

ARINC429
BKP

ARINC429T

ARINC429
PORTF
F
EXT_BUS_CNTRL
SPI3
SSP3
External peripheral

External SRAM

External device

Private Peripheral Bus

27

19861, 19861, 19861, 19861QI, 198614

(POR) (RESET)
, BOOT
ROM. ,
, .
MODE[2:0] (PA[2:0]). FPOR
BKP_REG_0E, Ucc.
.
MODE[2:0] ,
FPOR. PA[2:0]
.
6
MODE[2:0]

000

001

Stand alone1

00000_0000

010

Stand alone2

00000_0000

011

Stand alone3

00000_0000

00000_0000

FLASH
.
JTAG
:
ITCMLAEN=1- .
ITCMLAEN=0- .

Ethernet

.
HSE,
11 PLL.
{PC[3],PB[11:0]}
PA[15:0]
Byte enable PB[13:12]
Chip enable PB[15:14]
Write enable PC[0]
Output enable PC[1]
ITCMLAEN=1.


52070-2003

.

HSE, 11 PLL.
{PC[3],PB[11:0]}
{PC[6:4],PA[15:0]}
Chip enable PB[15:14]
Write enable PC[0]
Output enable PC[1]
ITCMLAEN=0.

Ethernet

52070-2003

.
HSE,
11 PLL.

ITCMLAEN=1

28

19861, 19861, 19861, 19861QI, 198614

100-110

UART

111

00000_0000

Ethernet.

ITCMLAEN=0

520702003.

UART1 PC[4:3]

-

JTAG/SW.
JTAG/SW ,

.

10

10

10

10

10

10

Ucc

RESET
TRST
TCK

TMS
TDI

JTAG/SW

TDO

9
:
, , FLASH ;
, ;
;
;
;
;
.
JTAG/SW
, 5.
7 JTAG/SW
JTAG/SW
TRST
TCK
TMS
TDI
TDO
JTAG_EN


JTAG
TRST
TCK
TMS
TDI
TDO
JTAG_EN

SWCLKTCK
SWDITMS

TCK
TMS

SW

29

19861, 19861, 19861, 19861QI, 198614


UART
UART UART1,
( 6).
8 / UART

100b
101b
110b

RX
P4
P4
P4

TX
P3
P3
P3

,
- ( Flash-),
. ,
. ,
(EERPOM, ROM, ).
UART1 RC-
HSI 8 . HSI,
UART1 .
UART
UART :
9600 ;
8;
;
Stop- 1;
FIFO UART1;
Slave, ,
Master;
.
UART
, (Master),
.
, :
9 UART

CMD_SYNC

0x00

CMD_CR
CMD_BAUD
CMD_LOAD
CMD_VFY
CMD_RUN

0x0D
0x42
0x4C
0x59
0x52

ASCII

'B'
'L'
'Y'
'R'

. ,

Master




.
(Master) Rx
. Master 000.
, .

30

19861, 19861, 19861, 19861QI, 198614


, (3 0x0D
( ), 0x0A ( ), 0x3E ('>'),) Master.
Master
.
CMD_SYNC
.
(Slave) , .
.
CMD_SYNC
10 CMD_SYNC

ASCII ,

:
Master: CMD_SYNC.

CMD_SYNC = 0x00

0
Slave: ,
ERR_CHN ERR_CMD

CMD_CR
Master-.
11 CMD_CR

ASCII
,


:
Master: CMD_CR.

CMD_CR = 0x0D

0
Slave: ,
ERR_CHN ERR_CMD
.
CMD_CR.
0x0A.
0x3E (ASCII '>').

CMD_BAUD
.
12 CMD_BAUD

ASCII
,

:
Master: CMD_BAUD
Master:

CMD_BAUD = 0x42
'B'
1
[].
Slave: ,
ERR_CHN ERR_CMD
.
Slave: ,
ERR_CHN ERR_BAUD
.
CMD_BAUD.
.

31

19861, 19861, 19861, 19861QI, 198614


CMD_LOAD
.
13 CMD_LOAD

ASCII
,


1.
2.
:
Master: CMD_LOAD
Master: 1.
Master: 2.

Master:
.

CMD_LOAD = 0x4C
'L'
2
.

Slave: ,
ERR_CHN ERR_CMD
.
Slave:
, ERR_CHN
.
Slave:
, ERR_CHN
.
CMD_LOAD.
Slave: .
,
ERR_CHN
,
.
REPLY_OK = 0x4B ('K').

CMD_VFY
.
14 CMD_VFY

ASCII
,


1
2
:
Master: CMD_VFY
Master: 1
Master: 2

CMD_VFY = 0x59
'Y'
2


Slave: ,
ERR_CHN ERR_CMD

Slave:
, ERR_CHN

Slave:
, ERR_CHN
.
CMD_VFY.
.
REPLY_OK = 0x4B ('K')

32

19861, 19861, 19861, 19861QI, 198614


CMD_RUN
.
15 CMD_RUN

ASCII ,


.
:
Master: CMD_RUN.
Master: .

CMD_RUN = 0x52
'R'
1

Slave: ,
ERR_CHN ERR_CMD

Slave: ,
ERR_CHN
. CMD_RUN.
MSP PC
(NVIC ) ,
, Slave


4- .
.
0xFFFFFFFF.
(UART '1'
- ), .
, ,
.

2- .
0x45 ('E'). .

, Master
, .
Master CMD_CR
, , .
: ERR_CHN, ERR_CMD, ERR_BAUD.

ERR_CHN
UART.
0x69 ('i').
, UART '1'
;
ERR_CMD
.
0x63 ('c').
, ;
ERR_BAUD
.
0x62 ('b').
, Master

UART.

33

19861, 19861, 19861, 19861QI, 198614

10

FLASH

Flash 128
4 .
( CON = 0, EEPROM_CMD)
ITCM .
( CON=1, EEPROM_CMD)
.
AHBLite . Flash
.

10.1 Flash
Flash 40 ,
Flash
25 .
, Flash 8
128 . , 40 Flash 16 ,
4 8 .
, . ,

. ,
, ,
, Flash.
, 25
, Flash ,
25 50 .
EEPROM_CMD Delay[2:0]. 16
Flash .
16 Flash-
Delay[2:0]
0x00
0x01
0x02
0x03
0x04
0x05
006
007

0
1
2
3
4
5
6
7

25
50
75
100
125
150
175
200


144

34

19861, 19861, 19861, 19861QI, 198614

10.2 Flash
Flash
, (
CON = 1) , .
EERPOM_KEY
0x8AAA5551.
(
IFREN = 0, EEPROM_CON), ( IFREN = 1) :

;
4 ;
32- ;
32- .

31
256 128
4K x 8
1
256 128
4K x 8
0
256 128
4K x 8

0x0001_FFFC

0x0001_F00C

0x0001_FFF8

0x0001_F008

0x0001_FFF4

0x0001_F004

0x0001_FFF0

0x0001_F000

0x0000_1FFC

0x0000_100C

0x0000_1FF8

0x0000_1008

0x0000_1FF4

0x0000_1004

0x0000_1FF0

0x0000_1000

0x0000_0FFC

0x0000_001C
0x0000_000C
Sector_D

0x0000_0FF8

0x0000_0018
0x0000_0008
Sector_C

0x0000_0FF4

0x0000_0014
0x0000_0004
Sector_B

0x0000_0FF0

0x0000_0010
0x0000_0000
Sector_A

256 x 32
1K x 8

256 x 32
1K x 8

256 x 32
1K x 8

256 x 32
1K x 8

(IFREN=0)
0
256 128
4K x 8

0x0000_0FFC

0x0000_001C
0x0000_000C
Sector_D

0x0000_0FF8

0x0000_0018
0x0000_0008
Sector_C

0x0000_0FF4

0x0000_0014
0x0000_0004
Sector_B

0x0000_0FF0

0x0000_0010
0x0000_0000
Sector_A

256 x 32
1K x 8

256 x 32
1 x 8

256 x 32
1 x 8

256 x 32
1K x 8

(IFREN=1)
10 Flash

35

19861, 19861, 19861, 19861QI, 198614

10.2.1
4 :
1 Sector_A ;
2 Sector_B ;
3 Sector_C ;
4 Sector_D .
.
IFREN (1
0 )
EEPROM_ADR[3:2] (00 Sector_A, 01 Sector_B, 10 Secotor_C 11 Sector_D),
XE, MAS1 ERASE , tnvs = 5
NVSTR . tme = 40 .
ERASE, tnvh1 = 100 XE, MAS1
NVSTR. trcv = 1 .
(. 11).
, .

IFREN

XADR

XE

MAS1
YE=SE=0
ERASE

tnvs
NVSTR

tme

tnvh1

trcv

11

36

19861, 19861, 19861, 19861QI, 198614

10.2.2 4
4 :
1 Sector_A ;
2 Sector_B ;
3 Sector_C ;
4 Sector_D .

.
IFREN (1 0
), EEPROM_ADR[16:12]
EEPROM_ADR[3:2] (00 Sector_A, 01 Sector_B, 10 Secotor_C 11
Sector_D). XE ERASE , tnvs = 5
NVSTR . terase = 40 .
ERASE, tnvh = 5
XE NVSTR. trcv =
1 . (.
12).
.

IFREN

XADR

XE

YE=SE=MAS1=0

ERASE

tnvs
NVSTR

terase

tnvh

trcv

12

37

19861, 19861, 19861, 19861QI, 198614

10.2.3 32-
.
IFREN (1 0
), ,
EEPROM_ADR, EEPROM_DI ,
XE PROG , tnvs = 5 NVSTR .
tpgs = 10 YE .
tprog = 40 . YE, tadh = 20
.
tads = 20 YE .
, tpgh = 20 YE
PROG tnvh = 5 XE NVSTR.
trcv = 1 .
( 13).

IFREN

XADR

XE

tadh

YADR

YE

DIN

tads
tprog

PROG

tpgh

tnvs
NVSTR

tpgs
thv

tnvh
trcv

13

38

19861, 19861, 19861, 19861QI, 198614

10.2.4 32-
.
.
, .
IFREN (1 0
), ,
EEPROM_ADR, XE, YE SE ,
txa, txy = 30 EEPROM_DO .
, EEPROM_ADR
txa, txy = 30 EEPROM_DO .
, .

( 14).

IFREN

XADR

XE

YADR

YE

SE

DOUT

txa

tya

tya

14
Flash 20 000 .

4 .

39

19861, 19861, 19861, 19861QI, 198614

10.3 Flash

15 Flash-
.
17 Flash-

0x4001_8000

EEPROM_CNTRL

Flash

0x00

EEPROM_CMD

004
0x08
0x0C
0x10

EEPROM_ADR
EEPROM_DI
EEPROM_DO
EEPROM_KEY

EEPROM

10.3.1 EEPROM_CMD
18 EERPOM_CMD

3114
U
0

9
R/W
0
IFREN

8
R/W
0
SE

7
R/W
0
YE

6
R/W
0
XE

13
R/W
0
NVSTR

12
R/W
0
PROG

11
R/W
0
MAS1

10
R/W
0
ERASE

53
R/W
100
Delay[2:0]

2
R/W
0
RD

1
R/W
0
WR

0
R/W
0
CON

:
R/W ;
RO ;
U .
19 EEPROM_CMD

31...1
4
13

,
.

NVSTR


0
1
ADR[16:2] EERPOM_DI
0
1
, ERASE =1
0
1
ADR[16:9], ADR[8:0]

0
1

0
1

12

PROG

11

MAS1

10

ERASE

IFREN

40

19861, 19861, 19861, 19861QI, 198614


8

SE

YE

XE

53

Delay[2:0]

RD

WR

CON


0
1
ADR[8:2]
0
1
ADR[16:9]
0
1
(
)
000 0
001 1

111 7
EERPOM ( )
0
1
EERPOM ( )
0
1
EEPROM
,
EERPOM
0 EERPOM ,
1 ,

10.3.2 EEPROM_ADR
20 EERPOM_ADR

310
R/W
0
ADR [31:0]

21 EEPROM_ADR
,


310
ADR[31:0]
:
ADR[1:0] ,
32

10.3.3 EEPROM_DI
22 EERPOM_DI

310
R/W
0
DATA [31:0]

23 EERPOM_DI

310


DATA[31:0]

,

EERPOM

41

19861, 19861, 19861, 19861QI, 198614

10.3.4 EEPROM_DO
24 EERPOM_DO

310
R/W
0
DATA [31:0]

25 EERPOM_DO

310


DATA[31:0]

,

, EERPOM

10.3.5 EEPROM_KEY
26 EEPROM_KEY

310
R/W
0
KEY [31:0]

27 EEPROM_KEY

310


KEY[31:0]

,

Flash-
.

EERPOM_KEY

0x8AAA5551

42

19861, 19861, 19861, 19861QI, 198614

11

, ,
:
3- ;
ARM v6-M,
32- Thumb-2 , BL, MRS, MSR, ISB, DSB DMB;

SVC ,
;
;
Handler Thread;
;
Thumb;
;
13x32 , link (LR),
(PC), xPSR,
(SP).
NVIC :

;
32 ;
,
;

,
.
ITCM, DTCM, AHB-Lite.
TCM ,
25 , Flash
.
:
;
DAP;
BPU;
DW.
32- .

43

19861, 19861, 19861, 19861QI, 198614

SW/JTAG
DAP
SWJ-DP
AHB-PPB

AHBAP

AHB matrix
AHB master

AHB Decoder
AHB Multiplexer

NVIC

Breakpoint unit
Data watchpoint
unit
Debug
control
ROM Table
Debug TCM
Interface

Dbg

Core

ITCM
88
Flash&ACC
128KB

DTCM
88
RAM
32KB

AHB-Lite

NVIC

15 -
:
NVIC
.

Bus master
. Private Peripheral
Bus (PPB) AHB PPB.
AHB .

AHB Private Peripheral Bus (AHB-PPB).


NVIC .

AHB decoder
AHB
.

AHB multiplexer
.

AHB matrix

PPB AHB-Lite.

DAP
AHB-Access Port (AHB-AP). AHB-AP
DP AHB-Lite. AHB-AP master
AHB matrix.
Serial-Wire JTAG Debug Port (SWJ-DP) JTAG Serial Wire
, , Serial Wire
JTAG.

44

19861, 19861, 19861, 19861QI, 198614

Debug TCM
ITCM DTCM.
TCM .

Breakpoint Unit
4- .

.

. , BPU
, .
.

Data Watchpoint unit


.
.
.
Watchpoint . ,
, ,
.

Debug control
PPB
.
, .

ROM table

, ,
.

45

19861, 19861, 19861, 19861QI, 198614

11.1
Thumb-2,
ARM v6-M. ARM
.
User Privileged.
Privileged.
:
Thread
,

Handler
.
Thread .

:
Thumb state
Thumb Thumb-2 16- 32 .

Debug state
, .

11.2
main . ,
SVCall, , Thread , main
process, EXC_RETURN .
main . R13, ,
main process . , process main, R13
.
main process Thread
Special-Purpose Control MSR.

11.3
32-x :
13 , R0-R12;
(SP, R13) , SP_process SP_main;
Link (LR, R14);
(PC, R15);
, xPSR.

46

19861, 19861, 19861, 19861QI, 198614

16

11.3.1 R0-R12
Low registers R0-R7 ,
.
High registers R8-R12 16 .

11.3.2 SP R13
R13 . [1:0]
, ( ).
SP[1:0] SBZP. Handler
SP_main, Thread SP_main, SP_process.

11.3.3 LR R14
R14 . LR
PC .
,
.
.

11.3.4 PC R15
Program Counter R15. . 0
0, .
, 0x00000004.

47

19861, 19861, 19861, 19861QI, 198614

11.3.5 PSR
Program Status Register (PSR) :
Application Program Status Register (APSR);
Interrupt Program Status Register (IPSR);
Execution Program Status Register (EPSR).
32- PSR.
. ,
,
MSR MRS. :
, PSR MRS ;
APSR APSR MSR .
28 PSR

XPSR
IEPSR
IAPSR
EAPSR

RW (1),(2)
RO
RW(1)
RW(2)

APSR, EPSR IPSR


EPSR IPSR
APSR IPSR
APSR EPSR

1.
IPSR .
2.
EPSR , .
MRS MSR.

11.3.6 APSR
APSR
.
29 APSR

31

30

29

28

270

30 APSR

31

30

29

28

270

,
.
Negative
0 , , ,
.
1
Zero:
0
1
Carry:
0 ,

1 ,
Overflow:
0
1

48

19861, 19861, 19861, 19861QI, 198614

11.3.7 IPSR
IPSR
.
31 IPSR

316

50

ISR_NUMBER

32 IPSR

316
50


ISR_NUMBER

,
.


0 Thread
2 NMI
3 Hard Fault
11 SVCall
14 PendSV
15 SysTick
16 IRQ0

47 IRQ31

11.3.8 EPSR
EPSR Thumb .
33 EPSR

31.25

24

230

34 EPSR

3125
24

23...0

,
.

,
reset.
- EPSR
Hard Fault.
, ARM ,
.

, EPSR, MSR
, , EPSR, MSR ,
.

49

19861, 19861, 19861, 19861QI, 198614

11.3.9 xPSR

. 9, , xPSR SP,
.

11.3.10 Priority Mask


PRIMASK .
35 PRIMASK

311

PRIMASK

36 PRIMASK

311
0

PRIMASK

,
.

0
1 0

MSR MRS,
CPS PRIMASK.

11.3.11 CONTROL
.
37 CONTROL

31.2

Active Stack
Pointer

38 CONTROL

312
1


Active Stack
Pointer
-

,
.

0 SP_main
1 Thread SP_process
)

a). Handler .

50

19861, 19861, 19861, 19861QI, 198614

11.4
:
32- (words);
16- (half words);
8- (bytes).
, code ,
. , ,
.
little-endian . Private Peripheral Bus
(PPB) little-endian .

51

19861, 19861, 19861, 19861QI, 198614

12

Thumb.
37.
:
<>
;
{} ;
;
Op2 , ;
.
.
39

ADC, ADCS
ADD, ADDS
ADR

{Rd,} Rn, Op2


{Rd,} Rn, Op2
Rd, label

AND, ANDS
ASR, ASRS
B
BIC, BICS
BKPT
BL
BLX
BX
CMN, CMNS

{Rd,} Rn, Op2


Rd, Rn, Op2
label
{Rd,} Rn, Op 2
#imm8
label
Rm
Rm
Rn, Op2

CMP, CMPS
CPSID

Rn, Op2
iflags

CPSIE

iflags

CPY
DMB

Rd, Op2
-

DSB

EOR, EORS
ISB

{Rd,} Rn, Op2


-

LDM

Rn!, reglist

LDMFD, LDMIA

Rn!, reglist

LDR
LDRB
LDRH
LDRSB
LDRSH

Rt, [Rn, #offset]


Rt, [Rn, #offset]
Rt, [Rn, #offset]
Rt, [Rn, #offset]
Rt, [Rn, #offset]

LSL, LSLS

Rd, Rm, <Rs|#n>

,

,

,

,





N,Z,C,V
N,Z,C,V
N,Z,C
N,Z,C
N,Z,C
N,Z,C,V
N,Z,C,V
N,Z,C
N,Z,C
N,Z,C

52

19861, 19861, 19861, 19861QI, 198614

LSR, LSRS
MOV, MOVS
MRS

Rd, Rm, <Rs|#n>


Rd, Op2
Rd, spec_reg

MSR

spec_reg, Rm

MUL, MULS

{Rd,} Rn, Rm

MVN, MVNS
NEG
NOP
ORR, ORRS
POP
PUSH
REV

Rd, Op2
{Rd,} Rm
{Rd,} Rn, Op2
reglist
reglist
Rd, Rn

REV16

Rd, Rn

REVSH

Rd, Rn

ROR, RORS
RSB, RSBS

Rd, Rm, <Rs|#n>


{Rd,} Rn, Op2

SBC, SBCS
SEV
STM

{Rd,} Rn, Op2


Rn!, reglist

STMEA

Rn!, reglist

STMIA

Rn!, reglist

STR
STRB
STRH
SUB, SUBS
SVC
SXTB

Rt, [Rn, #offset]


Rt, [Rn, #offset]
Rt, [Rn, #offset]
{Rd,} Rn, Op2
#imm
{Rd,}Rm{,ROR#n}

SXTH

{Rd,}Rm{,ROR#n}

TST
UXTB

Rn, Op2
{Rd,}Rm{,ROR#n}

UXTH

{Rd,}Rm{,ROR#n}

YIELD





, 32-










,







,

N,Z,C
N,Z,C
-

,

,


,
,

N,Z,C,V
N,Z
N,Z,C
N,Z,C,V
N,Z,C
-

N,Z,C
N,Z,C,V
N,Z,C,V
-

N,Z,C,V
N,Z,C
-


hint

53

19861, 19861, 19861, 19861QI, 198614

12.1
ANSI C
. (intrinsic) ,
.
,

.
CMSIS ,
ANSI C.
40 CMSIS,


CPSIE I
CPSID I
CPSIE F
CPSID F
ISB
DSB
DMB
REV
REV16
REVSH
SEV


void __enable_irq(void)
void __disable_irq(void)
void __enable_fault_irq(void)
void __disable_fault_irq(void)
void __ISB(void)
void __DSB(void)
void __DMB(void)
uint32_t __REV(uint32_t int value)
uint32_t __REV16(uint32_t int value)
uint32_t __REVSH(uint32_t int value)
void __SEV(void)

, CMSIS
, MRS MSR.
41 CMSIS

PRIMASK
CONTROL
MSP
PSP


uint32_t __get_PRIMASK (void)
void __set_PRIMASK (uint32_t value)
uint32_t __get_CONTROL (void)
void __set_CONTROL (uint32_t value)
uint32_t __get_MSP (void)
void __set_MSP (uint32_t TopOfMainStack)
uint32_t __get_PSP (void)
void __set_PSP (uint32_t TopOfProcStack)

54

19861, 19861, 19861, 19861QI, 198614

12.2
:
;
PC SP;
;
;
;
;
.

12.2.1
, ,
, .
, , -.
-, , ,
.
,
, . . .

12.2.2 PC SP
(PC)
(SP) -.
.
[0] , PC BX, BLX, LDM, LDR
POP 1, ,
Thumb.

12.2.3

.
Operand2. :
;
.

:
#constant
constant :
,

32- ;
0x00XY00XY;
0xXY00XY00;
0xXYXYXYXY.
X Y .
constant
.
.
Operand2 MOVS, MVNS,
ANDS, ORRS, EORS TST , 255

55

19861, 19861, 19861, 19861QI, 198614


[31]
. Operand2
.

,
, ,
.
, CMP Rd, #0xFFFFFFFE
CMN Rd, #0x2.

Operand2 :
Rm {, shift}
:
Rm , ;
shift , Rm.
:
ASR #n n , 1 <= n <= 32;
LSL #n n , 1 <= n <= 31;
LSR #n n , 1 <= n <= 32;
ROR #n n , 1 <= n <= 31.
, , LSL #0.
Rm -
.

32- Rm,
Rm .

.
.

12.2.4

. :
ASR, LSR, LSL ROR,
-;
Operand2 ,
.
,
. 0, .
, ,
0.
(Rm , n ).
ASR
n 32-n
Rm n , 32-n. [31]
n ( 17).
ASR # n Rm 2^n,
( ).
ASRS, , ASR #n MOVS, MVNS, ANDS, ORRS, EORS

56

19861, 19861, 19861, 19861QI, 198614


TST ,
, [n-1] Rm.
n >= 32, [31]
Rm. ,
[31] Rm.

17 ASR # 3
LSR
n 32-n Rm
n , 32-n. n
0 ( 18).
LSR # n Rm 2^n,
, .
LSRS, , LSR #n
MOVS, MVNS, ANDS, ORRS, EORS
TST ,
, [n-1] Rm.
n >= 32, 0. n >= 33
, 0.

18 LSR # 3
LSL
n 32-n Rm
n , 32-n. n
0 ( 19).
LSL # n Rm 2^n,
, ,
, .
.
LSLS, , LSL #n
MOVS, MVNS, ANDS, ORRS, EORS
TST ,
, [32-n] Rm. LSL #0
.
n >= 32, 0. n >= 33
, 0.

57

19861, 19861, 19861, 19861QI, 198614

19 LSL # 3
ROR
n 32-n Rm
n , 32-n. n
n ( 20).
RORS, , ROR #n
MOVS, MVNS, ANDS, ORRS, EORS
TST , [n-1]
Rm.
n = 32, . n =
32 ,
[31] Rm.
ROR , 32,
n-32.

20 ROR # 3

12.2.5
,
, ,
, ,
, .
.

:
LDR;
LDRH;
LDRSH;
STR;
STRH.

(Hard fault).
.
, , ,
. ,

58

19861, 19861, 19861, 19861QI, 198614


. ARM
. ,
, 1
UNALIGN_TRP CCR,
(.
).

12.2.6 PC

PC / .
.
, .
B, BL 4
.

4 , [1] 0
.

PC, / [PC, #number].

12.2.7

(APSR)
.
, .
, .
.
,
, ,
, .
40 , ,
.

. , :
;
-;
;
.
B<c>
(Branch), <c> .
:
;
.

APSR :
N=1 , , 0 ;
Z=1 , , 0 ;
C=1 , , 0
;
V=1 , , 0 .

59

19861, 19861, 19861, 19861QI, 198614


:
2^32;
;

.
, ,
2^31, -2^31.
,
S. . .

, , .
{cond}.
,
APSR.
( 40).
.

.
42

EQ
NE
CS HS
CC LO
MI
PL
VS
VC
HI
LS
GE
LT
GT
LE
AL

Z=1
Z=0
C=1
C=0
N=1
N=0
V=1
V=0
C = 1 and Z = 0
C = 0 or Z = 1
N=V
N != V
Z = 0 and N = V
Z = 1 and N != V
1

,
,


,
,
,
,
,
,
.

60

19861, 19861, 19861, 19861QI, 198614

12.3
43.
43

ADR
LDM{mode}
LDR{type}
LDR{type}
LDR
POP
PUSH
STM{mode}
STR{type}
STR{type}


,

,
,




,
,

12.3.1 ADR
, .

ADR Rd, label


:
Rd -.
Label , . .

ADR
PC ,
-.

.
ADR BX BLX
, [0] 1.
PC 01020.

Rd SP
PC.

ADR R1, TextMessage

; ,
; TextMessage, R1

12.3.2 LDR STR,


, -.

op{type} Rt, [Rn {, #offset}] ;


op{type} Rt, [Rn, #offset]!
; -
op{type} Rt, [Rn], #offset
; -
opD Rt, Rt2, [Rn {, #offset}]
; ,

61

19861, 19861, 19861, 19861QI, 198614


opD Rt, Rt2, [Rn, #offset]!
opD Rt, Rt2, [Rn], #offset

; -,
; -,

:
op :
LDR .
STR .
Type :
B , .
SB ,
( LDR).
H ,
.
SH ,
( LDR).
32- .
Rt ,
.
Rn , .
Offset Rn. ,
, .
Rt2 ,
.

LDR .
STR .

:

Rn.
. Rn
.
: [Rn, #offset].
-
Rn.
,
Rn.
: [Rn, #offset]! .
-
Rn .
Rn,
Rn.
: [Rn], #offset .
, ,
.
. . .
44
.

62

19861, 19861, 19861, 19861QI, 198614


44

, ,

-
-
0 124
0 124
0 124
, 4-, 0 1020

:
Rt PC SP
;
Rt Rt2 ;
- - Rn
Rt Rt2.
Rt
PC:
[0] 1;
,
[0] 0.
:
Rt SP ;
Rt Rn PC;
- - Rn
Rt Rt2.

LDR R5, [R7]


STR R2, [R7,#const-struc]
STRH R3, [R4], #4

; R5 ,
; R7.
; const-struc ,
; 0-124.
; R3,
; , , R4,
; R4 4

12.3.3 LDR STR,


,
.

op{type} Rt, [Rn, Rm {, LSL #n}]


:
op :
LDR .
STR .
Type :
B , .
SB ,
( LDR).
H ,
.

63

19861, 19861, 19861, 19861QI, 198614

SH ,
( LDR).
32- .

Rt ,
.
Rn , .
Rm , .
LSL #n , 0 3.

LDR .
STR .
, ,
Rn .
Rm .
,
.
, . . .

:
Rn PC;
Rm SP PC;
Rt SP
;
Rt PC ;
Rt
PC. [0] 1,
.

STR R0, [R5, R1]


LDRSB R0, [R5, R1, LSL #1]

STR R0, [R1, R2, LSL #2]

; R0 ,
;R5 R1
; , R5
;R1,

;
; , R0
; R0 ,
; R1+4*R2

64

19861, 19861, 19861, 19861QI, 198614

12.3.4 LDR, PC
.

LDR{type}Rt, label
:
type :
B , .
SB ,
( LDR).
H , .
SH ,
( LDR).
32- .
Rt , .
Rt2 , .
Label , . .

LDR , ,
PC.
, .

, . . .
.
45
.
45

, ,


0 124
0 1020

:
Rt PC SP
;
Rt2 PC SP;
Rt Rt2 .
Rt
PC. [0] 1,
;

LDR R0, LookUpTable


LDRSB R7, localdata

; R0
; LookUpTable
; localdata,
;
; , R7
65

19861, 19861, 19861, 19861QI, 198614

12.3.5 LDM STM


.

op{addr_mode} Rn!, reglist


:
op :
LDM .
STM .
Addr_mode :
IA .
.
EA ( STM).
FD ( LDM).
Rn , .
! .
, , ,
Rn.
Reglist ,
.
. -.
( ) . . .
LDMFD LDMIA LDM.
LDMFD ,
(Full Descending stack).
STMEA STMIA STM. STMEA
,
(Empty Ascending stack).

LDM reglist
, Rn.
STM ,
reglist, , Rn.
LDM, LDMIA, LDMFD, STM, STMIA STMEA
Rn Rn+4*(n-1), n reglist.
,
,
. Rn+4*(n-1) Rn.

:
Rn PC;
reglist SP;
STM reglist PC;
LDM reglist PC LR;
LDM reglist PC. [0]
1,
.

66

19861, 19861, 19861, 19861QI, 198614

LDMFD R6!,{R0,R2,R7}
; LDMFD LDM
STMEA R1!,{R3-R6,R0,R7} ; STMEA STM

STM R5!,{R5,R4,R3} ; R5
LDM R2!, {}
;

12.3.6 PUSH POP


, ,
(full-descending stack).

PUSH reglist
POP reglist
:
reglist ,
.
. -.
( ) .
PUSH POP STM LDM,
SP,
.
PUSH POP .

PUSH ,
.
POP
,
.

:
reglist SP;
PUSH PC;
POP
PC LR.
POP reglist PC, [0]
1,
.

PUSH {R0,R4-R7}

67

19861, 19861, 19861, 19861QI, 198614

12.4
46 .
46

ADC
ADD
AND
ASR
BIC
CMN
CMP
EOR
LSL
LSR
MOV
MVN
ORR
REV
REV16
REVSH

ROR
RSB
SBC
SUB
TST

12.4.1 ADD, ADC, SUB, SBC RSB


, , , ,
.

op{S} {Rd,} Rn, Operand2


op {Rd,} Rn, #imm8 ; ADD, SUB RSB
:
op :
ADD .
ADC .
SUB .
SBC .
RSB .
S . ,
, . .
Rd - . Rd ,
Rn.
Rn , .
Operand2 . . .
Imm8 0 1020 (Thumb) 0-508 (Thumb-2) ( RSB
0)

ADD Operand2 imm8 Rn.


68

19861, 19861, 19861, 19861QI, 198614


ADC Rn Operand2, .
SUB Operand2 imm8 Rn.
SBC Operand2 Rn.
, .
RSB Rn Operand2.
, Operand2.
ADC SBC
, . .
. ADR.

:
Operand2 SP PC;
SP Rd ADD
SUB, :
- Rn SP;
- Operand2 3 LSL;
SP Rn ADD
SUB;
PC Rd :
ADD PC, PC, Rm, :
- S;
- Rm PC SP;
- , IT-.
ADD PC, PC, Rm, Rn
PC ADD SUB
:
- S;
- 0 1020;
- PC [1:0]
0b00 ,
;
- , PC. ARM ADR,
;
- PC Rd ADD PC, PC, Rm
[0] , PC, ,
,
.

S, N, Z, C
V .

ADD R2, R1, R3


SUBS R7, R6, #240 ;
RSB R4, R4, #0
; R4 0

64-
, 64-
, R2 R3, 64- ,
R0 R1, R4 R5.

69

19861, 19861, 19861, 19861QI, 198614


ADDS R4, R0, R2
ADC R5, R1, R3

;
;

96-

. , , ,
96- , R5, R1 R7,
, R6, R2 R3. R6, R5 R2.
SUBS R6, R6, R5
SBCS R4, R2, R1
SBC R2, R3, R7

;
;
;

12.4.2 AND, ORR, EOR, BIC


, , , .

op{S}{Rd,} Rn, Operand2


:
op :
AND .
ORR .
EOR .
BIC .
S . ,
, . .
Rd - .
Rn , .
Operand2 . . .

AND, ORR EOR , , ,


, Rn
Operand2.
BIC ,
Rn Operand2.

SP PC.

S, :
N Z
;
C , .
;
V.

AND R4, R2,#0xFF00


ANDS R4, R3, #0x19
EORS R7, R5, #0x18181818
BIC R0, R1, #0xab

70

19861, 19861, 19861, 19861QI, 198614

12.4.3 ASR, LSL, LSR, ROR


, , ,
.

op{S} Rd, Rm, Rs


op{S} Rd, Rm, #n
:
op :
ASR .
LSL .
LSR .
ROR .
S . ,
, . .
Rd - .
Rm , .
Rs , .
, , 0
255.
N .
:
ASR 1 32;
LSL 0 31;
LSR 1 32;
ROR 1 31.

LSL{S} Rd, Rm, #0



MOV{S} Rd, Rm.

ASR, LSL, LSR ROR Rm


, n Rs.
Rd,
Rm .
.

SP PC.

S, :
N Z
;
C ,
, . . .

ASR R7, R1, #9


LSLS R1, R2, #3
LSR R4, R5, #6
ROR R4, R5, R6

; 9
; 3
; 6
; ,
; R6
71

19861, 19861, 19861, 19861QI, 198614

12.4.4 CMP CMN


.

CMP Rn, Operand2


CMN Rn, Operand2
:
Rm , .
Operand2 . . .

.
,
.
CMP Rn Operand2.
SUBS, , .
CMN Rn Operand2.
ADDS, ,
.

:
PC;
Operand2 SP.

N, Z, C V .

CMP R2, R7
CMN R0, #6400

12.4.5 MOV MVN


.

MOV{S} Rd, Operand2


MOV Rd, #imm8
MVN{S} Rd, Operand2
:
S . ,
, . .
Rd - .
Operand2 . . .
Imm8 0 255.
MVN Operand2,
, Rd.

SP PC
MOV, :
;
S .

72

19861, 19861, 19861, 19861QI, 198614


Rd PC:
[0] , PC, ;
,
[0], 0.

S, :
N Z
;
C , .
;
V.

MOVS R6, #0x000B ; 0x000B R6,


MOVS R5, R7
; R7 R5,
MOVS R3, #23
; 23 R3
MOVS R4, SP
; R4
MVNS R2, #0xF
; 0xFFFFFFF0 ( 0x0F)
; R2,

12.4.6 REV, REV16, REVSH


.

op Rd, Rn
:
op :
REV ;
REV16 ;
REVSH ,
.
Rd - .
Rn , .

(endianness)
:
REV 32- big-endian
little-endian .
REV16 32- big-endian
little-endian .
REVSH :
- 16- big-endian 32-
little-endian;
- 16- little-endian 32-bit 32-
big-endian.

SP PC.

73

19861, 19861, 19861, 19861QI, 198614

REV R3, R7
REV16 R0, R0
REVSH R0, R5
REVHS R3, R7

; R7, R3
; 16- R0
;
; (HS)

12.4.7 TST
, .

TST Rn, Operand2


:
Rn , .
Operand2 . . .


Operand2. ,
.
TST Rn
Operand2. ANDS, ,
.

SP PC.

S, :
N Z
;
C , .
;
V.

TST R0, R1

; R0 R1
; ,

74

19861, 19861, 19861, 19861QI, 198614

12.5
47 .
47

MUL


, 32-

12.5.1 MUL
(, )
32- 32- .

MUL{S} {Rd,} Rn, Rm ;


:
S . ,
, . .
Rd - . Rd ,
Rn.
Rn, Rm , .
Ra , ,
.

MUL , Rn
Rm, 32 Rd.
,
.

SP PC.
MUL S:
Rd, Rn Rm R0 R7;
Rd , Rm;
cond.

S, :
N Z
;
C V.

MUL R7, R2, R5


MULS R0, R2, R2

; R7 = R2 x R5
; R0 = R2 x R2,

75

19861, 19861, 19861, 19861QI, 198614

12.6
48 , :
48

SXTB
SXTH
UXTB
UXTH

12.6.1 SXT UXT



.

SXTextend Rd, Rm
UXTextend Rd, Rm
:
extend :
B 8- 32-.
H 16- 32-.
Rd - .
Rm - .

SXTB [7:0] Rm, 32-


[7] [31:8],
Rd.
UXTB [7:0] Rm, 32-
[31:8], Rd.
SXTH [15:0] Rm,
32- [15] [31:16],
Rd.
UXTH 16 [15:0] Rm, 32-
[31:16], Rd.

SP PC.

SXTH R4, R6

UXTB R3, R7

; R6,
; 32-
; , R4
; R7,
; 32- ,
; R3

76

19861, 19861, 19861, 19861QI, 198614

12.7
49 .
49

B
BL
BLX
BX

12.7.1 B, BL, BX BLX


.

B {cond} label
BL label
BX Rm
BLX Rm
:
B .
BL .
BX , .
BLX .
Cond , . .
Label , . .
Rm , , .
[0] 1,
, [0], 0.


, Rm. :
BL BLX LR
(R14).
BX BLX (Hard fault) , bit[0]
Rm 0.
50
.
50

B {cond} label
BL label
BX Rm
BLX Rm


-1 +1
-16 +16
,
,

77

19861, 19861, 19861, 19861QI, 198614

BLX PC;
BX BLX, [0] Rm 1,
, , , [0], 0;
B {cond}
BLX BX Thumb.
Hard Fault

B loopA
BLE ng
BEQ target
BL funC

; loopA
; ng
; target
; ( ) funC,
; LR
BX LR ;
BLX R0
; ( ) , R0

78

19861, 19861, 19861, 19861QI, 198614

12.8
51
:
51

BKPT
CPSID
CPSIE
CPY
DMB
DSB
ISB
MRS
MSR
NOP
SEV
SVC
YIELD


,
,
MOV






hint.

12.8.1 CPS
.

CPSeffect iflags
:
effect :
IE 0.
ID 1.
Iflags :
i PRIMASK.

CPS PRIMASK.

CPS ,
.

CPSID i
CPSIE i

;
;

79

19861, 19861, 19861, 19861QI, 198614

12.8.2 DMB
.

DMB

DMB
. , (explicit) ,
DMB, ,
.
DMB ,
.

DMB ;

12.8.3 DSB
.

DSB

DSB
. , , , DSB,
. DSB ,
(explicit) .

DSB ; Data Synchronisation Barrier

12.8.4 ISB
.

ISB

ISB .
, ,
, ISB,
.

ISB
;

80

19861, 19861, 19861, 19861QI, 198614

12.8.5 MRS
.

MRS Rd, spec_reg


:
Rd - .
Spec_reg : APSR, IPSR, EPSR, IEPSR, IAPSR,
EAPSR, PSR, MSP, PSP, PRIMASK CONTROL.

MRS MSR --
PSR, , Q.
, ,
,
.

() PSR.
MRS,
MSR.
. MSR.

- Rd SP PC.

MRS R0, PRIMASK ; PRIMASK R0

12.8.6 MSR
.

MSR spec_reg, Rn
:
Rn - .
Spec_reg : APSR, IPSR, EPSR, IEPSR, IAPSR,
EAPSR, PSR, MSP, PSP, PRIMASK CONTROL.

MSR
.
APSR. , EPSR
.
.
. MRS.

- Rn SP PC.

MSR CONTROL, R1 ; R1 CONTROL


81

19861, 19861, 19861, 19861QI, 198614

12.8.7 NOP
.

NOP

NOP . ,
, ,
. NOP , ,
, 64- .

NOP ;

12.8.8 SEV
.

SEV

SEV . ,
1.
. .

SEV ;

12.8.9 SVC
.

SVC #imm8
:
imm8 , 0 255 (8-
).

SVC SVC. imm8


.
.

SVC 0x32

; :
; SVC
; PC .

82

19861, 19861, 19861, 19861QI, 198614

13

,

.

SLEEPING

SLEEPDEEP

PLLCPUo

PLLCPUrdy

PLLCPUrld

PLLCPUmul[3:0]

PLLCPUi

PLLUSBo

PLLCPUon

CPU PLL

PLLUSBrdy

PLLUSBrld

PLLUSBmul[3:0]

PLLUSBi

PLLUSBon

USB PLL

CPU_C2
HSI
HSE
LSI
LSE
HSEON
HSEBYP
HSERDY
HSE2

HSI

CPU_C1

HSI
/1...256

MUX

/2
MUX

HSE

HCLK

CPU_C3
LSE

CPU_C2_SEL[1:0]

&

MU
X

F_CLK
CPU_CLK

LSI

/2

CPU_C3_SEL[3:0]
HSI

CPU_C1_SEL[1:0]

HSE

HSEON2
HSEBYP2
HSERDY2

PHY_CLK
/1...128

MUX

PLLCPUo
0 HSE2

PHY_CLK_EN

PHY_CLK_SEL[1:0]
HCLK

&

UART1_CLK_EN
UART2_CLK_EN
TIM1_CLK_EN
TIM2_CLK_EN
TIM3_CLK_EN
TIM4_CLK_EN
SSP1_CLK_EN
SSP2_CLK_EN
SSP3_CLK_EN
MAN_CLK_EN
ETH_CLK_EN
HSI

&

PHY_BRG[2:0]

/1...128
/1...128
/1...128
/1...128
/1...128
/1...128
/1...128
/1...128
/1...128
/1...128
/1...128

UART1_CLK
UART2_CLK
TIM1_CLK
TIM2_CLK
TIM3_CLK
TIM4_CLK
SSP1_CLK
SSP2_CLK
SSP3_CLK
MAN_CLK
ETH_CLK
USB_C2

USB_C1

USB_C3
/1...2

MUX

&

USB_CLK

/2
USB_CLK_EN

MUX

HSE

USB_C2_SEL[1:0]
ADC_CLK_EN

USB_C3_SEL

/2

ADC_C3

USB_C1_SEL[1:0]

LSE
CPU_C2

MUX

LSI

&

MUX

&

USB_C2
ADC_C3_SEL[1:0]

HCLK
ADC_C2_SEL[1:0]

/1...256

HSE

MCO

MCO_CLK_EN

ADC_C1_SEL[1:0]
HSI

ADC_CLK

/1...256

&

PCLK[31:0]

/1...256
PCLK_EN[31:0]

HSI_C1_SEL[3:0]

&

HSE_RTC_EN

RTCHSI

HSE_C1_SEL[3:0]

&

HSE_RTC_EN

RTCHSE

21

13.1 RC HSI
HSI 8 .
Ucc
HSIRDY BKP_REG_0F.
HSI.
HSI HSION
BKP_REG_0F. HSITRIM
BKP_REG_0F.

83

19861, 19861, 19861, 19861QI, 198614

13.2 RC LSI
LSI 40 .
Ucc
LSIRDY BKP_REG_0F.
LSI 4 .
LSI LSION
BKP_REG_0F.

13.3 HSE
HSE 216
. Ucc
HSEON HS_CONTROL.
HSERDY CLOCK_STATUS.
HSEBYP, OSC_IN
HSE, OSC_OUT
.

13.4 LSE
LSE 32
. BDUcc
LSEON BKP_REG_0F .
LSERDY BKP_REG_0F.
LSEBYP, OSC_IN32
LSE. OSC_OUT32 .
LSE BDUcc
BKP_REG_0F ,
Ucc. LSE
.

13.5

2 16, PLLCPUMUL[3:0] PLL_CONTROL.
216 144
.
PLLCPURDY CLOCK_STATUS.
PLLCPUON PLL_CONTROL.
.

13.6
USB

2 16, PLLUSBMUL[3:0] PLL_CONTROL.
216
48 .
PLLUSBRDY CLOCK_STATUS.
PLLUSBON PLL_CONTROL.
USB .
RST_CLK.
HSI .
RST_CLK

84

19861, 19861, 19861, 19861QI, 198614


.
PER_CLOCK. (UART,
CAN, USB, ) ,
(UART_CLOCK, CAN_CLOCK, USB_CLOCK,
TIM_CLOCK) .
/
.
,
, CPU_CLOCK USB_CLOCK.

13.7
52

0x4002_0000

0x00

RST_CLK
CLOCK_STATUS

004

PLL_CONTROL

0x08

HS_CONTROL

0x0C

CPU_CLOCK

0x10

USB_CLOCK

0x14

ADC_MCO_CLOCK

0x18

RTC_CLOCK

0x1C

PER_CLOCK

0x20

CAN_CLOCK

0x24

TIM_CLOCK

0x28

UART_CLOCK

0x2C

SSP_CLOCK

0x34

ETH_CLOCK












USB



RTC


CAN

TIMER

UART

SSP

Ethernet
52070-2003

85

19861, 19861, 19861, 19861QI, 198614

13.7.1 CLOCK_STATUS
53 CLOCK_STATUS

314
U
0

3
RO
0

2
RO
0

HSE
RDY2

HSE
RDY

1
RO
0
PLL
CPU
RDY

0
RO
0
PLL
USB
RDY

54 CLOCK_STATUS

314
3


HSE
RDY2

HSE
RDY

PLL
CPU
RDY
PLL
USB
RDY

,
.

HSE2 2
0
1
HSE
0
1
CPU PLL
0 PLL
1 PLL
USB PLL
0 PLL
1 PLL

13.7.2 PLL_CONTROL
55 PLL_CONTROL

3112
U
0
-

118
R/W
0000
PLL
CPU
MUL[3:0]

74
R/W
0000
PLL
USB
MUL[3:0]

3
R/W
0
PLL
CPU
PLD

2
R/W
0
PLL
CPU
ON

1
R/W
0
PLL
USB
RLD

0
R/W
0
PLL
USB
ON

56 PLL_CONTROL

3112
11.8
74


PLL
CPU
MUL[3:0]
PLL
USB
MUL[3:0]
PLL
CPU
PLD
PLL
CPU
ON
PLL
USB
RLD
PLL
USB
ON

,
.

CPU PLL:
PLLCPUo = PLLCPUi x (PLLCPUMUL+1)
USB PLL:
PLLUSBo = PLLUSBi x (PLLUSBMUL+1)
PLL

1,
PLL
0 PLL
1 PLL
PLL

1,
PLL
0 PLL
1 PLL

86

19861, 19861, 19861, 19861QI, 198614

13.7.3 HS_CONTROL
57 HS_CONTROL

314
U
0
-

3
R/W
0
HSE
BYP2

2
R/W
0
HSE
ON2

1
R/W
0
HSE
BYP

0
R/W
0
HSE
ON

58 HS_CONTROL

314
3


HSE
BYP2
HSE
ON2
HSE
BYP
HSE
ON

,
.

HSE2 2
0
1
HSE2 2
0
1
HSE
0
1
HSE
0
1

87

19861, 19861, 19861, 19861QI, 198614

13.7.4 CPU_CLOCK
59 CPU_CLOCK

3110
U
0

98
R/W
00

HCLK
SEL[1:0]

74
R/W
0000
CPU
C3
SEL[3:0]

3
U
0
-

2
R/W
0
CPU
C2
SEL

10
R/W
00
CPU
C1
SEL[1:0]

60 CPU_CLOCK

3110
98


HCLK
SEL[1:0]

74
CPU
C3
SEL[3:0]

3
2

CPU
C2
SEL

10
CPU
C1
SEL[1:0]

,
.

HCLK
00 HSI
01 CPU_C3
10 LSE
11 LSI
CPU_C3
0xxx CPU_C3 = CPU_C2;
1000 CPU_C3 = CPU_C2 / 2;
1001 CPU_C3 = CPU_C2 / 4;
1010 CPU_C3 = CPU_C2 / 8;

1111 CPU_C3 = CPU_C2 / 256;

CPU_C2
0 CPU_C1
1 PLLCPUo
CPU_C1
00 HSI
01 HSI/2
10 HSE
11 HSE/2

88

19861, 19861, 19861, 19861QI, 198614

13.7.5 USB_CLOCK
61 USB_CLOCK

319
U
0
-

8
R/W
0
USB
CLK
EN

75
U
000
-

4
R/W
0
USB
C3
SEL

3
U
0
-

2
R/W
0
USB
C2
SEL

10
R/W
00
USB
C1
SEL[1:0]

62 USB_CLOCK

319
8
75
4

3
2


USB
CLK
EN
USB
C3
SEL
USB
C2
SEL

10
USB
C1
SEL[1:0]

,
.

USB
0
1

USB_C3
USB_C3 = USB_C2/(USB_C3_SEL+1);

USB_C2
0 USB_C1
1 PLLUSBo
USB_C1
00 HSI
01 HSI/2
10 HSE
11 HSE/2

89

19861, 19861, 19861, 19861QI, 198614

13.7.6 ADC_MCO_CLOCK
63 ADC_MCO_CLOCK

3114
U
0

13
R/W
0

12
U
0

ADC
CLK
EN

118
R/W
0000
ADC
C3
SEL[3:0
]

76
U
00

54
R/W
00

ADC
C2
SEL[1:0]

32
U
00
-

10
R/W
00
ADC
C1
SEL[1:0]

64 ADC_MCO_CLOCK

3114
13

12
118


ADC
CLK
EN
-

ADC
C3
SEL[3:0]

76
54

ADC
C2
SEL[1:0]

32
10

ADC
C1
SEL[1:0]

,
.

ADC CLK
0
1

ADC_C3
0xxx ADC_C3 = ADC_C2;
1000 ADC_C3 = ADC_C2 / 2;
1001 ADC_C3 = ADC_C2 / 4;
1010 ADC_C3 = ADC_C2 / 8;

1111 ADC_C3 = ADC_C2 / 256;

ADC_C2
00 LSE
01 LSI
10 ADC_C1
11 HSI_C1

ADC_C1
00 CPU_C1
01 USB_C1
10 CPU_C2
11 USB_C2

90

19861, 19861, 19861, 19861QI, 198614

13.7.7 RTC_CLOCK
65 RTC_CLOCK

3110
U
0
-

9
R/W
0
HSI
RTC
EN

8
R/W
0
HSE
RTC
EN

74
R/W
0000

30
R/W
0000

HSI
SEL[1:0]

HSE
SEL[1:0]

66 RTC_CLOCK

3110
9

74


HSI
RTC
EN
HSE
RTC
EN
HSI
SEL[3:0]

30
HSE
SEL[3:0]

,
.

HSI RTC
0
1
HSE RTC
0
1
HSI_C1
0xxx HSI_C1 = HSI;
1000 HSI_C1 = HSI / 2;
1001 HSI_C1 = HSI / 4;
1010 HSI_C1 = HSI / 8;

1111 HSI_C1 = HSI / 256;


HSE_C1
0xxx HSE_C1 = HSE;
1000 HSE_C1 = HSE / 2;
1001 HSE_C1 = HSE / 4;
1010 HSE_C1 = HSE / 8;

1111 HSE_C1 = HSE / 256;

91

19861, 19861, 19861, 19861QI, 198614

13.7.8 PER_CLOCK
67 PER_CLOCK

310
R/W
0
PCLK_EN[31:0]

68 PER_CLOCK

310

PCLK
EN[31:0]

,
.

0
1
PCLK[0] CAN1
PCLK[1] CAN2
PCLK[2] USB
PCLK[3] EEPROM_CNTRL
PCLK[4] RST_CLK
PCLK[5] DMA
PCLK[6] UART1
PCLK[7] UART2
PCLK[8] SPI1
PCLK[9] MIL-STD-1553B1
PCLK[10] MIL-STD-1553B2
PCLK[11] POWER
PCLK[12] WWDT
PCLK[13] IWDT
PCLK[14] TIMER1
PCLK[15] TIMER2
PCLK[16] TIMER3
PCLK[17] ADC
PCLK[18] DAC
PCLK[19] TIMER4
PCLK[20] SPI2
PCLK[21] PORTA
PCLK[22] PORTB
PCLK[23] PORTC
PCLK[24] PORTD
PCLK[25] PORTE
PCLK[26] ARINC429R
PCLK[27] BKP
PCLK[28] ARINC429T
PCLK[29] PORTF
PCLK[30] EXT_BUS_CNTRL
PCLK[31] SPI3

92

19861, 19861, 19861, 19861QI, 198614

13.7.9 CAN_CLOCK
69 CAN_CLOCK

3126

25

24

R/W

R/W

231
6
U

CAN2
CLK
EN

CAN1
CLK
EN

158
R/W
0000000
0
CAN2
BRG
[7:0]

70
R/W
00000000
CAN1
BRG
[7:0]

70 CAN_CLOCK

31...26
25

24

23...16
158


CAN2
CLK
EN
CAN1
CLK
EN
-

,
.

CAN2
0
1
CAN1
0
1

CAN2

CAN2
BRG
[7:0]

xxxxx000 CAN2_CLK == HCLK


xxxxx001 CAN2_CLK == HCLK/2
xxxxx010 CAN2_CLK == HCLK/4

xxxxx111 CAN2_CLK == HCLK/128


CAN1

CAN1
BRG
[7:0]

xxxxx000 CAN1_CLK == HCLK


xxxxx001 CAN1_CLK == HCLK/2
xxxxx010 CAN1_CLK == HCLK/4

xxxxx111 CAN1_CLK == HCLK/128

70

93

19861, 19861, 19861, 19861QI, 198614

13.7.10 TIM_CLOCK
71 TIM_CLOCK

3127

26

25

24

R/W

R/W

231
6
U

TIM3
CLK
EN

TIM2
CLK
EN

TIM1
CLK
EN

TIM3
BRG
[7:0]

158
R/W
0000000
0
TIM2
BRG
[7:0]

70
R/W
00000000
TIM1
BRG
[7:0]

72 TIM_CLOCK

31...27
26

25

24


TIM3
CLK
EN
TIM2
CLK
EN
TIM1
CLK
EN

,
.

TIM3
0
1
TIM2
0
1
TIM1
0
1
TIM3

TIM3
BRG
[7:0]

xxxxx000 TIM3_CLK == HCLK


xxxxx001 TIM3_CLK == HCLK/2
xxxxx010 TIM3_CLK == HCLK/4

xxxxx111 TIM3_CLK == HCLK/128


TIM2

TIM2
BRG
[7:0]

xxxxx000 TIM2_CLK == HCLK


xxxxx001 TIM2_CLK == HCLK/2
xxxxx010 TIM2_CLK == HCLK/4

xxxxx111 TIM2_CLK == HCLK/128


TIM1

TIM1
BRG
[7:0]

xxxxx000 TIM1_CLK == HCLK


xxxxx001 TIM1_CLK == HCLK/2
xxxxx010 TIM1_CLK == HCLK/4

xxxxx111 TIM1_CLK == HCLK/128

23...16

158

70

94

19861, 19861, 19861, 19861QI, 198614

13.7.11 UART_CLOCK
73 UART_CLOCK

3127

26

25

24

R/W

R/W

R/W

231
6
R/W

TIM4
CLK
EN

UART2
CLK
EN

UART 1
CLK
EN

TIM4
BRG
[7:0]

158
R/W
0000000
0
UART 2
BRG
[7:0]

70
R/W
00000000
UART 1
BRG
[7:0]

74 UART_CLOCK

31...27
26

25

24


TIM4
CLK
EN
UART2
CLK
EN
UART1
CLK
EN

,
.

TIM4
0
1
UART2
0
1
UART 1
0
1
TIM4

TIM4
BRG
[7:0]

xxxxx000 TIM4_CLK == HCLK


xxxxx001 TIM4_CLK == HCLK/2
xxxxx010 TIM4_CLK == HCLK/4

xxxxx111 TIM4_CLK == HCLK/128


UART 2

UART2
BRG
[7:0]

xxxxx000 UART 2_CLK == HCLK


xxxxx001 UART 2_CLK == HCLK/2
xxxxx010 UART 2_CLK == HCLK/4

xxxxx111 UART 2_CLK == HCLK/128


UART 1

UART1
BRG
[7:0]

xxxxx000 UART 1_CLK == HCLK


xxxxx001 UART 1_CLK == HCLK/2
xxxxx010 UART 1_CLK == HCLK/4

xxxxx111 UART 1_CLK == HCLK/128

23...16

158

70

95

19861, 19861, 19861, 19861QI, 198614

13.7.12 SSP_CLOCK
75 SSP_CLOCK

3127
U

26
R/W

25
R/W

24
R/W

SSP3
CLK
EN

SSP2
CLK
EN

SSP 1
CLK
EN

2316
R/W
0000000
0
SSP 3
BRG
[7:0]

158
R/W
0000000
0
SSP 2
BRG
[7:0]

70
R/W
00000000
SSP 1
BRG
[7:0]

76 SSP_CLOCK

31...27
26

25

24


SSP3
CLK
EN
SSP2
CLK
EN
SSP1
CLK
EN

,
.

SSP 3
0
1
SSP 2
0
1
SSP 1
0
1
SSP 3

SSP3
BRG
[7:0]

xxxxx000 SSP 3_CLK == HCLK


xxxxx001 SSP 3_CLK == HCLK/2
xxxxx010 SSP 3_CLK == HCLK/4

xxxxx111 SSP 3_CLK == HCLK/128


SSP 2

SSP2
BRG
[7:0]

xxxxx000 SSP 2_CLK == HCLK


xxxxx001 SSP 2_CLK == HCLK/2
xxxxx010 SSP 2_CLK == HCLK/4

xxxxx111 SSP 2_CLK == HCLK/128


SSP 1

SSP1
BRG
[7:0]

xxxxx000 SSP 1_CLK == HCLK


xxxxx001 SSP 1_CLK == HCLK/2
xxxxx010 SSP 1_CLK == HCLK/4

xxxxx111 SSP 1_CLK == HCLK/128

23...16

158

70

96

19861, 19861, 19861, 19861QI, 198614

13.7.13 ETH_CLOCK
77 ETH_CLOCK

31...30
U

2928
R/W

27

26
R/W

25

24
R/W

00

PHY
CLK
SEL

PHY
CLK
EN

SLEEP

MAN
CLK
EN

ETH
CLK
EN

2316
R/W
0000000
0
PHY
BRG
[7:0]

158
R/W
0000000
0
MAN
BRG
[7:0]

70
R/W
0000000
0
ETH
BRG
[7:0]

78 ETH_CLOCK

3130
29...28

PHY_CLK_SEL
[1:0]

27

PHY
CLK
EN

26

SLEEP

25

24

MAN
CLK
EN
ETH
CLK
EN

23...16
PHY
BRG
[7:0]
158
MAN
BRG
[7:0]

70

ETH
BRG
[7:0]

,
.
Ethernet PHY
00 HSI
01 HSE
10 PLLCPUo
11 HSE2 2
Ethernet PHY
0
1

0
1

,
.
520702003
0
1
Ethernet MAC
0
1
PHY
xxxxx000 PHY_CLK == PHY1_CLK
xxxxx001 PHY_CLK == PHY1_CLK/2
xxxxx010 PHY_CLK == PHY1_CLK/4
xxxxx011 PHY_CLK == PHY1_CLK/8

xxxxx111 PHY_CLK == PHY1_CLK/128



52070-2003
xxxxx000 MAN_CLK == HCLK
xxxxx001 MAN_CLK == HCLK/2
xxxxx010 MAN_CLK == HCLK/4

xxxxx111 MAN_CLK == HCLK/128


0

97

19861, 19861, 19861, 19861QI, 198614

14

Trim[2:0]

Low[2:0]

Select_RI[2:0]

JTAGB

JTAGA

CLR_OWF

CLR_ALRF

CLR_SECF



. Ucc SW
BDUcc c Ucc Bucc. Bucc
(),
.

SECF

RTCSEL
[1:0]

RTC_PRL
[19:0]

OWF

HSI
HSE
LSI
LSE

ALRF
M
U
X

RTC_DIV
[19:0]

LSEON

RTC_CNT
[31:0]

0x00

LSEBYP

0x01
RTC_20
[19:0]

LSIRDY

LSION

==

LSITRIM[15:0]
HSION

RTC_ALR
[31:0]

LSERDY
HSIRDY

0x0E (PSS Control)

HSITRIM[5:0]

0x0F (RTC & Generator Control)

WEAKUP

STANDBY
Standby

DATAo[31:0]

CLK

RD

WR

ADR[3:0]

DATAi[31:0]

RTC_CNT_a[19:0]

RTC_DIV_a[19:0]

RTC_PRL_a[19:0]

RTC_ALRM_a[31:0]

WE[3:0]

WEC

RTC_DIV[19:0]

RTC_CNT[31:0]

BDUcc

22 -

14.1

, .
RTCEN.
LSI, LSE, HSE, HSI c
256 (HSE HSI
Ducc, LSI
Ucc, LSE Ucc Bucc).
RTCSEL.
Ucc
LSE, BDUcc.
LSE , ,
.
.
CAL[6:0]. CAL
, 2^20 . ,
CAL . CAL
.

98

19861, 19861, 19861, 19861QI, 198614


RTC_DIV 20-
, , 1 .
RTC_DIV RTC_PRL.
RTC_CNT
RTC_DIV. RTC_ALR
,
. , STANBY, ,
RTC_CNT RTC_ALR.
STANDBY WAKEUP.

14.2
16 32-
. 16- ,
15 .

14.3
79

0x400D_8000

0x00

0x38
0x3C

BKP

BKP_REG_00

BKP_REG_0E
BKP_REG_0F

14
15
RTC, LSE, LSI HSI



ALRF

0x40
0x44

RTC_CNT
RTC_DIV

048
04

RTC_PRL
RTC_ALRM

050

RTC_CS

99

19861, 19861, 19861, 19861QI, 198614

14.3.1 BKP_ REG_[0D00]


BKP_REG_00
BKP_REG_01
BKP_REG_02
BKP_REG_03
BKP_REG_04
BKP_REG_05
BKP_REG_06
BKP_REG_07
BKP_REG_08
BKP_REG_09
BKP_REG_0A
BKP_REG_0B
BKP_REG_0C
BKP_REG_0D
80 REG_[0D00]

310
R/W
0
BKP REG[31:0]

81 REG_[0D00]

310


BKP
REG[31:0]

14.3.2 BKP_REG_0E
82 REG_0E

311
6
U
0
-

15

14

1312

11

108

53

20

R/W
0

U
0

R/W
00

R/W
0

R/W
000

U
0

R/W
0

R/W
000

ilime
n

Trim
[4:3]

FPOR

Trim[2:0]

Stand_
Alone

R/W
000
SelectR
I
[2:0]

LOW
[2:0]

83 REG_0E

3116
15


ilimen

14
1312

Trim[4:3]

,
.

150

1
0


00-1.8
01-1.6
10-1.4
11-1.2

100

19861, 19861, 19861, 19861QI, 198614


11

108

FPOR

Trim[2:0]

7
6

Stand_Alone

53

SelectRI[2:0]

20

LOW[2:0]

POR
1
, 0.
,
,
.

Ducc. Trim
Ducc
000 Ducc + 0,10 .
001 Ducc + 0,06
010 Ducc + 0,04
011 Ducc + 0,01
100 Ducc 0,01
101 Ducc 0,04
110 Ducc 0,06
111 Ducc 0,10

1 StandAlone
0
1.8
000 ~6 ( 300 )
001 ~270 ( 6,6 )
010 ~90 ( 20 )
011 ~24 ( 80 )
100 ~900 ( 2 )
101 ~2 ( 900 )
110 ~400 ( 4,4 )
111 ~100 ( 19 )
1.8
LOW SelectRI

000 10
001 200
010 500
011 1
100
101 40
110 80
111 80

101

19861, 19861, 19861, 19861QI, 198614

14.3.3 BKP_REG_0F
84 REG_0F

31
R/W
0
RTC
RESET

15
R/W
1
LSI
ON

2924
R/W
0000
HSI
TRIM
[5:0]

30
R/W
0
STANDBY

14
U
0
-

13
RO
0
LSE
RDY

125
R/W
0000000
CAL[7:0
]

23
R/W
0

22
R/W
0

21
RO
0

HSI
RDY

HSI
ON

LSI
RDY

4
R/W
0
RTC
EN

3..2
R/W
00
RTC
SEL[1:0]

1
R/W
0
LSE
BYP

2016
R/W
0000
LSI
TRIM
[4:0]
0
R/W
0
LSE
ON

85 REG_0F

31


RTC
RESET

30

STANDBY

29.24

HSI
TRIM[5:0]

23

HSI
RDY

22

HSI
ON

21

LSI
RDY

2016

LSI
TRIM[4:0]

15

LSI
ON

14
13

LSE
RDY

125

CAL[7:0]

,


0
1
Ducc 1.8
0
1
ALRF
WAKEUP.
HSI
24
HSI HSITRIM
HSI
0
1
HSI
0
1
LSI
0
1
LSI
23
LSI LSITRIM
LSI
0
1

LSE
0
1

, 2^20 CAL
.
00000000 0
00000001 1
.
11111111 256
, 32768.00000
CAL = 0 ,
= 32768.00000
CAL = 1 ,
= 32767,96875 ;

102

19861, 19861, 19861, 19861QI, 198614

4
32

CAL = 256 , = 32760.00000 ;



0
1


00 LSI
01 LSE
10 HSIRTC ( CLKRST)
11 HSERTC ( CLKRST)
LSE
0
1 ( )
LSE:
0 ;
1

RTC
EN
RTC
SEL[1:0]

LSE
BYP

LSE
ON

80,00
70,00

LSI,

60,00
50,00
40,00
30,00
20,00
10,00
0,00
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31
LSITRIM

23 LSI LSITRIM

14,00
12,00

HSI,

10,00
8,00
6,00
4,00
2,00
0,00
1 5 9 13 17 21 25 29 33 37 41 45 49 53 57 61
HSITRIM

24 HSI HSITRIM

103

19861, 19861, 19861, 19861QI, 198614

14.3.4 RTC_CNT
86 RTC_CNT

310
R/W
0
RTC_CNT
[31:0]

87 RTC_CNT

310


RTC
CNT[31:0]

,
.

14.3.5 RTC_DIV
88 RTC_DIV

3120
U
0
-

190
R/W
0
RTC_DIV
[19:0]

89 RTC_DIV

3120
190


RTC DIV
[19:0]

,
.

14.3.6 RTC_PRL
90 RTC_PRL

3120
U
0
-

190
R/W
0
RTC_PRL
[19:0]

91 RTC_PRL

3120
190


RTC
PRL
[19:0]

,
.

104

19861, 19861, 19861, 19861QI, 198614

14.3.7 RTC_ALRM
92 RTC_ALRM

310
R/W
0
RTC
ALRM[31:0]

93 RTC_ALRM

310


RTC
ALRM[31:0]

,
.

ALRF

14.3.8 RTC_CS
94 RTC_CS

317
U
0
-

6
R/W
WEC

5
R/W
0
ALRF_IE

4
R/W
0
SECF_IE

3
R/W
0
OWF_IE

2
R/W
0
ALRF

1
R/W
0
SECF

0
R/W
0
OWF

95 RTC_CS

317
6


WEC

ALRF_IE

SECF_IE

OWF_IE

ALRF

SECF

OWF

,
.


0 RTC
1 RTC, .

RTC_ALRM
0
1


0
1

RTC_CNT
0
1
RTC_ALRM
0
1


0
1
RTC_CNT
0
1

105

19861, 19861, 19861, 19861QI, 198614

15

6 /. 16-
,
. ,

.
96 -

IO

ANALOG_EN=0 MODE[1:
0]=00
ANALOG
_EN=1

MODE[1:0]=01
ANALOG_EN=1

MODE[1:0]=10
ANALOG_EN=1

MODE[1:0]=11
ANALOG_EN=1


PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15

PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15

PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15

PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15

D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31

P0
P1
P2
P3
P4
P5

P0
P1
P2
P3
P4
P5


nWR
1
nRD
ALE
UART_TXD1
9
UART_RXD1
EXTINT1
8

EXTINT1
EXTINT2
EXTINT3
EXTINT4
BRK2
BRK3
TMR4_CH1
TMR4_CH1N
TMR4_CH2
TMR4_CH2N
TMR4_CH3
TMR4_CH3N
TMR4_CH4
TMR4_CH4N
BRK4
ETR4

IN1+
IN1IN2+
IN2IN3+
IN3IN4+
IN4IN5+
IN5IN6+
IN6IN7+
IN7IN8+
IN8-

ETR1
ETR2
CLKO
CLE
BUSY
SSP1_TXD

3
13
1

13
10
16

ETR1
ETR2
ETR3
BRK1
FRX
FSD
FXEN
FTX
PRMC+
PRMCPRMD+
PRMDPRDC+
PRDCPRDD+
PRDD-

3
13
10
3
15

TMR3_CH1
TMR3_CH1N
TMR3_CH2
TMR3_CH2N
TMR3_CH3
TMR3_CH3N
TMR3_CH4
TMR3_CH4N
TMR1_CH1N
TMR2_CH1N
TMR1_CH2N
TMR2_CH2N
TMR1_CH3N
TMR2_CH3N
TMR1_CH4N
TMR2_CH4N

10

BRK1
BRK2
BRK3
SIROUT0
SIRIN0
SSP1_RXD

3
13
10
9

14

3
13
3
13
3
13
3
13

14

106

19861, 19861, 19861, 19861QI, 198614

IO

P6
P7
P8
P9
P10
P11
P12
P13
P14
P15

ANALOG_EN=0 MODE[1:
0]=00
ANALOG
_EN=1
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15

PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15

ADC0_REF+ 5
ADC1_REFADC2
ADC3
ADC4
ADC5
ADC6
ADC7
DAC1_REF
6

PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15

PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15

DAC2_REF
6
DAC1_OUT
DAC2_OUT
OSC_IN32
7
OSC_OUT32
-

PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15

PF0
PF1
PF2

OSC_IN25
OSC_OUT25
-

PF0
PF1
PF2

PF3
PF4
PF5
PF6

PF3
PF4
PF5
PF6

MODE[1:0]=01
ANALOG_EN=1

EXTINT2
EXTINT3
EXTINT4
SSP2_TXD
11
SSP2_RXD
SSP2_SCK
SSP2_FSS
PRMA+
4
PRMAPRMB+
D
PRMB4
PRDA+
PRDAPRDB+
PRDBPRD_PRMA
PRD_PRMB
SSP2_TXD
11
SSP2_RXD
SSP2_SCK
SSP2_FSS
A0
1
SSP3_TXD
19
UART_TXD2
12
UART_RXD2
OUT3+
2
E
OUT4+
2
OUT3OUT4TMR1_CH1
3
TMR1_CH2
TMR1_CH3
TMR1_CH4
TMR2_CH1
13
TMR2_CH2
TMR2_CH3
TMR2_CH4
CAN_RX1
17
CAN_TX1
CAN_RX2
18
CAN_TX2
PRD_PRMD
4
F
PRD_PRMA
4
PRD_PRMB
READY/PRD_P 1/4
RMC
PRMC+
4
PRMCPRMD+
PRMD-

MODE[1:0]=10
ANALOG_EN=1

SSP1_RXD
SSP1_SCK
SSP1_FSS
BE0
BE1
BE2
BE3
A30
A31
BUSY

ALE
CLE
SSP1_TXD
SSP1_RXD
SSP1_SCK
SSP1_FSS
nUART2RI
nUART2DCD
nUART2DTR
nUART2DSR
nUART2RTS
nUART2CTS
ETR3
OUT1+
OUT1A13

A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
READY
A30
A31
A0
A1
A2
A3

MODE[1:0]=11
ANALOG_EN=1

SSP1_TXD
FXEN
FTX
CAN_RX1
CAN_TX1
CAN_RX2
CAN_TX2
UART_TXD2
UART_RXD2
TMR2_CH1

15
17
18
12
13

A16
A15
A14
A13
A7
A6
A5
A4
A3
A2
A1
FRX
SSP3_RXD
SIROUT1
SIRIN1
FSD

MDC
nUART2RI
MDIO
TXD[0]
TXD[1]
TXD[2]
TXD[3]
RXD[0]
RXD[1]
RXD[2]
RXD[3]
TXEN
TXER
TXCLK
RXCLK
RXDV

15
12
15

RXER
CRS
COL

15

TMR1_CH1
TMR1_CH2
TMR1_CH3
TMR1_CH4

14

12

10
2
1

15
19
12
15

107

19861, 19861, 19861, 19861QI, 198614

PF7
PF8
PF9
PF10
PF11
PF12
PF13
PF14
PF15

IO

ANALOG_EN=0 MODE[1:
0]=00
ANALOG
_EN=1
PF7
PF8
PF9
PF10
PF11
PF12
PF13
PF14
PF15

MODE[1:0]=01
ANALOG_EN=1

PRDC+
PRDCPRDD+
PRDDPRD_PRMC
PRD_PRMD
OUT2+
OUT2SSP3_RXD

2
19

MODE[1:0]=10
ANALOG_EN=1

A4
A5
A6
A7
A8
A9
A10
A11
A12

MODE[1:0]=11
ANALOG_EN=1

OUT4+
OUT4OUT3+
OUT3OUT2+
OUT2SSP3_FSS
SSP3_SCK
SSP3_TXD

19

:
1 EXT_BUS
2 18977-79
3 1
4 52070-2003
5
6
7 LSE
8
9 UART1
10 3
11 SSP2
12 UART2
13 2
14 SSP1
15 Ethernet 10/100
16 4
17 CAN1
18 CAN2
19 SSP3

108

19861, 19861, 19861, 19861QI, 198614


To Analog
To Analog

PAD

PULL UP
GFEN
Analog

EN

RX

RX
PD

ESD R

PAD

Port_Func[1:0]
MODE

Port_TX

EN

Main_TX

TX

Alter_TX

MUX

Remap_TX

OE

Port_OE
Main_OE
Alter_OE

MUX

Remap_OE
PULL DOWN

25 /

15.1 /
97 -

0x400A_8000
0x400B_0000
0x400B_8000
0x400C_0000
0x400C_8000
0x400E_8000

0x00
004
0x08
0x0C
0x10
0x14
0x18
0x1C
020

GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6


B
C
D
E
F

PORT_RXTX[15:0]
PORT_OE[15:0]
PORT_FUNC[31:0]
PORT_ANALOG[15:0]
PORT_PULL[31:0]
PORT_PD[31:0]
PORT_PWR[31:0]
PORT_GFEN[15:0]
PORT_SETTX[15:0]




(/)




SET_TX 1 1
PORT_RXTX
CLR_TX 1 0
RXTX
,

0x24

PORT_CLRTX[15:0]

0x28

PORT_RDTX

109

19861, 19861, 19861, 19861QI, 198614

15.1.1 PORTx_RXTX
98 RXTX

3116
U
0

150
R/W
0
PORT RXTX
[15:0]

99 RXTX

3116
150


PORT
RXTX[15:0]

15.1.2 PORTx_OE
100 OE

3116
U
0

150
R/W
0
PORT OE
[15:0]

101 OE

3116
150


PORT
OE[15:0]



1
0

15.1.3 PORTx_FUNC
102 FUNC

31
30
R/W
R/W
0
0
MODE15[1:0]

3
2
R/W
R/W
0
0
MODE1[1:0]

1
0
R/W
R/W
0
0
MODE0[1:0]

103 FUNC

312
10


MODEx
MODE0[1:0]

,

MODE0

00
01
10
11

110

19861, 19861, 19861, 19861QI, 198614

15.1.4 PORTx_ANALOG
104 ANALOG

3116
U
0
-

150
R/W
0
ANALOG
EN[15:0]

105 ANALOG

3116
150


ANALOG
EN[15:0]


0
1

15.1.5 PORTx_PULL
106 PULL

3116
R/W
0
PULL
UP[15:0]

150
R/W
0
PULL
DOWN[15:0]

107 PULL

3116

150


PULL
UP[15:0]

PULL
DOWN[15:0]

,



0
1 ( )


0
1 ( )

15.1.6 PORTx_PD
108 PD

3116
R/W
0
PORT
SHM[15:0]

150
R/W
0
PORT
PD[15:0]

109 PD

3116

150


PORT
SHM[15:0]

PORT
PD[15:0]

,
.


0 200 .
1 400 .


0
1

111

19861, 19861, 19861, 19861QI, 198614

15.1.7 PORTx_PWR
110 PWR

31
30
R/W
R/W
0
0
PWR15[1:0]

3
2
R/W
R/W
0
0
PWR1[1:0]

1
0
R/W
R/W
0
0
PWR0[1:0]

111 PWR

312
10


PWRx
PWR0[1:0]

,
.
PWR0

00
01
10
11

15.1.8 PORTx_GFEN
112 GFEN

31
U
0

16
R/W
0
-

150
R/W
0
GFEN[15:0]

113 GFEN

3116
150


GFEN[15:0]

,
.


0
1

112

19861, 19861, 19861, 19861QI, 198614

16

PVD Ucc
Bucc . PVD

.
Ucc PLS[2:0]
PVDCS, Bucc PLBS[1:0] PVDCS.
PVD PBVD.
.
114

, Ucc,
, Bucc,
PVD Ucc, PLS = 000,
PVD Ucc, PLS = 001,
PVD Ucc, PLS = 010,
PVD Ucc, PLS = 011,
PVD Ucc, PLS = 100,
PVD Ucc, PLS = 101,
PVD Ucc, PLS = 110,
PVD Ucc, PLS = 111,
PBVD Bucc, PLS = 00,
PBVD Bucc, PLS = 01,
PBVD Bucc, PBLS = 10,
PBVD Bucc, PBLS = 11,


2,0
1,8

2,0
2,2
2,4
2,6
2,8
3,0
3,2
3,4
1,8
2,2
2,6
3,0


3,6
3,6

115 PVD

0x4005_8000

0x00

POWER

PVDCS [12:0]

16.1.1 PVDCS
116 PVDCS

3113
U
0

12
R/W
0
PVDB
EN

9
R/W
0

8
R/W
0

7
R/W
0

6
R/W
0

IEPVD

IEPVBD

PVD

PVBD

53
R/W
000
PLS
[2:0]

11
R/W
0

10
R/W
0

INV

INVB

21
R/W
00
PBLS
[1:0]

0
R/W
0
PVD
EN

113

19861, 19861, 19861, 19861QI, 198614


117 PVDCS

3113
12


PVDBEN

11

INV

10

INVB

IEPVD

IEPVBD

PVD

PVBD

53

PLS[2:0]

21

PBLS[1:0]

PVDEN

Bucc
0
1
PVD
0
1
,
, ,

PVBD
0
1
,
, ,

PVD
0
1
0,
, .
PVBD
0
1
0,
, .

0 PLS
1 PLS
0,
, .

0 PBLS
1 PBLS
0,
, .

000 2,0
001 2,2
010 2,4
011 2,6
100 2,8
101 3,0
110 3,2
111 3,4

00 1,8
01 2,2
10 2,6
11 3,0
Ucc
0
1

114

19861, 19861, 19861, 19861QI, 198614

17


. 118
, .
118

0x0010_0000 0x1FFF_FFFF
ITCMLAEN=1
0x0000_0000 0x1FFF_FFFF
ITCMLAEN=0
0x5000_0000 0xDFFF_FFFF

256

Code

AHB-Lite

Peripheral
External SRAM


AHB-Lite .
DMA


. ,

, ,
.

17.1 ,


,
EXT_BUS_CONTROL. RAM
, ROM .

WAIT_STATE[3:0].

A, D nRD,
nWR, BE[3:0] CLKO.

A[31:0]

A[31:0]

Byte, Word, DWord

DI[31:0]

Read

D[31:0]

IO

CLKO
BE[3:0]

16453

nRD
nWR

Write

A[31:0]

DO[31:0]

DO[31:0]
DI[31:0]

nRD
nWR
CLKO
BE[3:0]

nRD
nWR
nBHE, nBLE

26

115

19861, 19861, 19861, 19861QI, 198614


tcycle
1/2 tcycle
1/4
tcycle

1/4
tcycle

A [31:0]

BE[3:0]
D [31:0]

nWR

nRD
CLKO
CPOL = 0

CLKO
CPOL = 1

27
tcycle WAIT_STATE[3:0].
nWR, nRD, BE[3:0] . CLKO ,
.
tcycle
tcycle

tcycle

tcycle

A[31:0]

BE[3:0]

D[31:0]

tdacc

tdh

nWR

nRD

CLKO
CPOL = 0

CLKO
CPOL = 1

28

tcycle, . tdh
.

116

19861, 19861, 19861, 19861QI, 198614

17.2 NAND Flash


NAND Flash

EXT_BUS_CONTROL. NAND NAND Flash .



NAND Flash
NAND_CYCLES.
,
NAND Flash D[7:0], ALE, CLE BUSY.

DO[7:0]

A[31:0]

DI[7:0]
DO[31:0]

DI[31:0]

Byte, Word, DWord

D[7:0]

IO
NAND
Flash

nRD
nWR

nRD

ALE

nWR

CLE
Write
Read

BUSY

ALE
CLE
BUSY

nRE
nWR
ALE
CLE
R/nB

29 NAND Flash
BUSY NAND
Flash. BUSY NAND Flash
BUSY. NAND Flash
,
.
( 119).
119

A[31:24]

A[23:21]

A[20]

A[19]
A[18:11]



,

0x100x1F
0x300x3F
0x500xCF
ADR_CYCLES[2:0]
A[23:22]
000 0
001 1
A[21]


111 7

,
,


.

0
1
0
1

117

19861, 19861, 19861, 19861QI, 198614


ECMD[7:0]
0x10/0x11 Page Program
0xD0 Block Erase

SCMD[7:0]
0x00/0x01 Read1
0x50 Read2
0x90 Read ID
0xFF Reset
0x80 Page Program
0x60 Block Erase
0x70 Read Status

A[10:3]

A[2:0]

NAND Flash

NAND Flash .
// ======================================================================
// NAND Flash
// ======================================================================
NAND_CYCLES = 0x02A63466;
// t_rr = 2 HCLK 20 HCLK 100
// t_alea = 10
// t_whr = 6
// t_wp = 3
// t_rea = 4
// t_wc = 6
// t_rc = 6
EXT_BUS_CONTROL = 0x00000004;
// NAND = 1;
// ======================================================================
// ID
// ======================================================================
unsigned char IDH;
unsigned char IDL;
//
*((volatile unsigned char *) (0x77200480)) = 0x00;
// ADR_CYCLE = 1
// SCMD = 0x90 (READ)
// Address 1 cycle = 0x00
//
IDL = *((volatile unsigned char *)(0x77080000));
IDH = *((volatile unsigned char *)(0x77080000));

// ======================================================================
//
// ======================================================================
//
*((volatile unsigned char *)(0x70768300))=0x11;
*((volatile unsigned char *)(0x70768301))=0x22;
*((volatile unsigned char *)(0x70768302))=0x33;
// ADR_CYCLE = 3

118

19861, 19861, 19861, 19861QI, 198614


//
// ECMD= 0xD0
// SCMD = 0x60
// Address 1 cycle = 0x11
// Address 2 cycle = 0x22
// Address 1 cycle = 0x33
while (EXT_BUS_CONTROL!=0x080 ) {};
// R/nB
//
*((volatile unsigned char *)(0x70000380+addon))=0x00;
// ADR_CYCLE = 0
// SCMD = 0x70
//
IDL = *((volatile unsigned char *)(0x77080000));
If (IDL & 0x01==0x01) Error ();
// IO0==1
// ======================================================================
//
// ======================================================================
//
*((volatile unsigned char *)(0x70800400))=0x11;
*((volatile unsigned char *)(0x70800400))=0x22;
*((volatile unsigned char *)(0x70800400))=0x33;
*((volatile unsigned char *)(0x70800400))=0x44;
// ADR_CYCLE = 4
// SCMD = 0x80
//
*((volatile unsigned char *)(0x70088000+addon))=0xBB;
*((volatile unsigned char *)(0x70088000+addon))=0xCC;
*((volatile unsigned char *)(0x70088000+addon))=0xDD;
//
// ECMD= 0x10

*((volatile unsigned char *)(0x70188000+addon))=0xEE;


//
// ECMD= 0x10
// 0 0xBB, 1 0xCC, N 0xEE
// N 1 528
while (EXT_BUS_CONTROL!=0x080 ) {};
// R/nB
//
*((volatile unsigned char *)(0x70000380+addon))=0x00;
// ADR_CYCLE = 0
// SCMD = 0x70
//
IDL = *((volatile unsigned char *)(0x77080000));
If (IDL & 0x01==0x01) Error ();
// IO0==1
// ======================================================================
//
// ======================================================================
//
*((volatile unsigned char *)(0x70800000))=0x11;
*((volatile unsigned char *)(0x70800000))=0x22;
*((volatile unsigned char *)(0x70800000))=0x33;

119

19861, 19861, 19861, 19861QI, 198614


*((volatile unsigned char *)(0x70800000))=0x44;
// ADR_CYCLE = 4
// SCMD = 0x00
while (EXT_BUS_CONTROL!=0x080 ) {};
// R/nB
//
IDL=*((volatile unsigned char *)(0x70080000));
IDH=*((volatile unsigned char *)(0x70080000));
If (IDL != 0xBB || IDH != 0xCC) Error ();
//

120

19861, 19861, 19861, 19861QI, 198614

17.3

120

0x400F_0000

0x50

EXT_BUS
NAND_CYCLES

0x54

EXT_BUS_CONTROL

0x58

RAM_Cycles1

0x5C

RAM_Cycles2

0x60

RAM_Cycles3

0x64

RAM_Cycles4



NAND_Flash




RAM

010000000-01FFFFFFF
2


RAM

050000000-05FFFFFFF
2


RAM

060000000-06FFFFFFF
2


RAM

070000000-0DFFFFFFF
2

121

19861, 19861, 19861, 19861QI, 198614

17.3.1 EXT_BUS_CONTROL
121 CONTROL

15

14

13

12

11

10

R/W

R/W

R/W

R/W

1
R/W
0
RAM

0
R/W
1
ROM

7
RO
1
BUSY

1
1
WAIT_STATE[3:0]
6
R/W
0
LOW16

5
R/W
0
LOW8

1
4
R/W
0
ENDIAN

3
R/W
CPOL

2
R/W
0
NAND

122 CONTROL

3116
1512

118
7


WAIT
STATE[3:0]

BUSY

LOW16

LOW8

4
3

ENDIAN
CPOL

NAND

RAM

ROM

AHB,
/. nRD/nWR
WAIT_STATE,
WAIT_STATE.

NAND Flash .
1
0
16
2
1 16

0
3 32
LOW16=1
.
8
2
1 8

0
3 32
LOW8=1
.

CLKO
0
1
NAND
1 NAND
0 NAND
2..0 ,

RAM
1 RAM
0 RAM
ROM
1 ROM
0 ROM

122

19861, 19861, 19861, 19861QI, 198614


123
WAIT_STATE

nWR
nRD

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8


nWR
nRD
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4



nWR
nRD
0
1
1
1
1
1
2
2
2
2
3
3
3
3
4
4

CE

WAIT_STATE+1
nWR/nRD

* WAIT_STATE+1

* WAIT_STATE+LSB
30

123

19861, 19861, 19861, 19861QI, 198614

17.3.2 NAND_CYCLES
124 NAND_CYCLES

3128
U
-

2724
R/W
0
t_rr

2320
R/W
0
t_alea

1916
R/W
0
t_whr

1512
R/W
0
t_wp

118
R/W
0
t_rea

74
R/W
0
t_wc

30
R/W
0
t_rc

125 NAND_CYCLES

3128
27...24


t_rr[3:0]

23...20

t_alea[3:0]

1916

t_whr[3:0]

1512

t_wp[3:0]

118

t_rea[3:0]

7...4

t_wc[3:0]

30

t_rc[3:0]

,
.

busy
0000 0 HCLK
0001 1 HCLK
.
1111 15 HCLK
NAND Flash 20
ID
t_rr
NAND Flash 100

t_rr
NAND Flash 60

t_rr
NAND Flash 25

t_rr
NAND Flash 35

t_rr
NAND Flash 60

t_rr
NAND Flash 60

124

19861, 19861, 19861, 19861QI, 198614

17.3.3 RAM_CYCLESx
126 RAM_CYCLESx

31...15
U
-

14
R/W
0
USE_READY

1311
R/W
0
WS_HOLD

10...8
R/W
0
WS_SETUP

71
R/W
0
WS_ACTIVE

0
R/W
0
ENABLE_TUNE

127 RAM_CYCLESx

31...15
14

USE_READY

13...11

WS_HOLD

10...8

WS_SETUP

7...1

WS_ACTIVE

ENABLE_TUNE

READY PF[2],

.
1
0
READY
ACTIVE, READY
HOLD
,
,
256. .
nWR/nRD,
1 8
nWR/nRD /,

1 8
nWR/nRD
/,
1 128


1
0

125

19861, 19861, 19861, 19861QI, 198614

18

Stand Alone


Ethernet 52070-2003.
,
.
PLL,
.
, , Stand Alone 2,
8 OSC_IN OSC_OUT. Stand Alone 1
Stand Alone 3
, .
Stand Alone 1 ( Ethernet):
RST_CLK->PLL_CONTROL=0x304;
RST_CLK->HS_CONTROL= 3;
RST_CLK->CPU_CLOCK=0x00000107;
BKP->REG_0E &= ~(1<<7);
BKP->REG_0E |= 1<<6;
RST_CLK->ETH_CLOCK=0x19000000;
Stand Alone 2 ( 52070-2003):
RST_CLK->PLL_CONTROL=0x904;
RST_CLK->HS_CONTROL=1 3; (3 ; 1 )
RST_CLK->CPU_CLOCK=0x00000106;
RST_CLK->PER_CLOCK|=1<<4 | 1<<9| 1<<10 | 1<<27;
BKP->REG_0E &= ~(1<<7);
BKP->REG_0E |= 1<<6;
RST_CLK->ETH_CLOCK=0x02000000;
Stand Alone 3 ( 52070-2003 Ethernet):
RST_CLK->PLL_CONTROL=0x304;
RST_CLK->HS_CONTROL=3;
RST_CLK->CPU_CLOCK=0x00000107;
RST_CLK->PER_CLOCK|=1<<4 | 1<<9| 1<<10 | 1<<27;
BKP->REG_0E &= ~(1<<7);
BKP->REG_0E |= 1<<6;
RST_CLK->ETH_CLOCK=0x1B000000;
Stand Alone 1 3 HSE 25
. Stand Alone 2 HSE
8 , .
Stand Alone
.
( 31, 32).
50 .
,
.
,
50 .

126

19861, 19861, 19861, 19861QI, 198614


100

40

60

A[12:0]

BE[1:0]

D[18:0]

nRD

nWR

nCE1,
nCE2

31
100

100

A[12:0]

BE[1:0]

D[18:0]

nWR

nRD

nCE1,
nCE2

32

127

19861, 19861, 19861, 19861QI, 198614

19

USB

USB
(Device) (Host) USB 2.0.
USB : Full Speed (12 /) Low Speed (1.5 /)
, (CRC), NRZI
/, (Control), (Bulk), (Isochronous)
(Interrupt).
USB Device 1- 4- , SOF ,
. USB Device
FIFO 64 . USB Host 16
. USB Host FIFO 64 .

19.1

USB. .
USB
(HSI) (HSE). USB
48 .
.
PLLUSB.

2 16, PLLUSBMUL PLL_CONTROL.
216 ,
48 .
PLLRDY. PLLUSBON.
USB .

. ( 2 PER_CLOCK).
USB_CLOCK USBCLKEN,
USBC1SEL USBC2SEL. PLLUSBON
PLLUSBMUL PLL_CONTROL, USBPLL.
USB
. RESET_CORE USB_HSCR.
10 .
USB (, , ).

19.2 USB
/
USB USB Host USB Device.
CORE_MODE USB_HSCR (0 Device, 1
Host). / USB
EN_RX EN_TX .
(EN_TX=0).
EN_RX=0.
Device USB_SC.
SCFSR (0 1.5 /, 1 12 /), SCFSP (0 Low speed, 1
Full speed) .
Host USB_TXLC.
FSLR (0 1.5 /, 1 12 /), FSPL (0 Low speed, 1 Full
speed) .

128

19861, 19861, 19861, 19861QI, 198614


Host
. CONEV USB_HIS 1
.

19.3
USB USB_SA.

(SCGEN = 1 USB_SC). EPEN

USB_SEPx.CTRL
,

.
, EPISOEN
USB_SEPx.CTRL.

19.4 IN (Usb Device)


IN USB_SA,
SCTDONE USB_SIS 1.
( EPRDY = 0 USB_SEPx.CTRL),
NAK ( 33). NAKSENT USB_SEPx.STS
1.
EPSSTALL
USB_SEPx.CTRL, STALL ( 33). SCSTALLSENT
USB_SEPx.STS 1.
( 33), SCTTYPE[1:0]
USB_SEPx.TS 1 ,
. .
USB_Epx.TXFD FIFO . 1
USB_Epx.TXFC FIFO 0.
64 . 64
FIFO.
FIFO.
ACK , SCACKRXED
USB_SEPx.STS 1.
EPDATASEQ USB_SEPx.CTRL,
DATA0, DATA1.
SCTDONE USB_SIS
1.

129

19861, 19861, 19861, 19861QI, 198614


USB_SEPx.CTRL
EPISOEN
EPSSTALL
EPDATASEQ
EPRDY
EPEN

SYNC

IN

ADDR

SCTDONE = 1
(USB_SIS)

SYNC

NAK

USB_SEPx.CTRL
EPISOEN
EPSSTALL
EPDATASEQ
EPRDY
EPEN

0
0
X
0
1

ENDPx

CRC5

EOP

NTTYPE[1:0] = 1
(USB_SEP0.NTS)

EOP

SYNC

ADDR

SCTDONE = 1
(USB_SIS)

SYNC

NAKSENT = 1
(USB_SEPx.STS)

IN

STALL

USB_SEPx.CTRL
EPISOEN
EPSSTALL
EPDATASEQ
EPRDY
EPEN

0
1
X
1
1

ENDPx

CRC5

SCTTYPE[1:0] = 1
(USB_SEPx.TS)

SYNC

IN

ADDR

ENDPx

SCTDONE = 1
(USB_SIS)

CRC5

EOP

SCTTYPE[1:0] = 1
(USB_SEPx.TS)

DATA0/1

EOP

SCSTALLSENT = 1
(USB_SEPx.STS)

SCTDONE (SCTDONE = 1)

EOP

1. FIFO
ENDPx (USB_EPx.TXFD)
2.
(EPDATASEQ)

0
0
X
1
1

SYNC

DATA0/1

SYNC

ACK

DATA

CRC16

EOP

SCTDONE (SCTDONE = 1)
EOP

1. FIFO ENDPx (USB_EPx.TXFC = 1)


2. SCTDONE (SCTDONE = 1)
a)

) EPSTALL

33 (, , ) IN (USB Device)

19.5 SETUP/OUT (Usb Device)


SETUP/OUT ,
USB_SA ( EP_READY = 1 ENDPOINTx_CONTROL),
SCTDONE USB_SIS 1.
( EPRDY = 0 USB_SEPx.CTRL),
NAK ( 34). NAKSENT USB_SEPx.ST
1.
EPSSTALL
USB_SEPx.CTRL, STALL ( 34). SCSTALLSENT
USB_SEPx.STS 1.
( 34) SETUP,
SCTTYPE[1:0] USB_SEPx.TS 00
, . OUT, SCTTYPE[1:0] = 2.
DATA0/DATA1 ,
FIFO .
.
USB_Epx.RXFD.

USB_Epx.RXFDC.
FIFO 1 USB_Epx.RXFC.
SCTDONE USB_SIS
1.

130

19861, 19861, 19861, 19861QI, 198614


USB_SEPx.CTRL
EPISOEN
EPSSTALL
EPDATASEQ
EPRDY
EPEN

SYNC

SETUP/
OUT

ADDR

SCTDONE = 1
(USB_SIS)

SYNC

NAK

USB_SEPx.CTRL
EPISOEN
EPSSTALL
EPDATASEQ
EPRDY
EPEN

0
0
X
0
1

ENDPx

CRC5

EOP

NTTYPE[1:0] = 0/2
(USB_SEP0.NTS)

EOP

SYNC

ADDR

SCTDONE = 1
(USB_SIS)

SYNC

NAKSENT = 1
(USB_SEPx.STS)

SETUP/
OUT

STALL

USB_SEPx.CTRL
EPISOEN
EPSSTALL
EPDATASEQ
EPRDY
EPEN

0
1
X
1
1

ENDPx

CRC5

EOP

SCTTYPE[1:0] = 0/2
(USB_SEPx.TS)

EOP

SYNC

SCTDONE (SCTDONE = 1)

ADDR

ENDPx

SCTDONE = 1
(USB_SIS)

SYNC

DATA0/1

CRC5

EOP

SCTTYPE[1:0] = 0/2
(USB_SEPx.TS)

DATA

CRC16

EOP

FIFO ENDPx

SCSTALLSENT = 1
(USB_SEPx.STS)

SCTDONE (SCTDONE = 1)

SETUP/
OUT

0
0
X
1
1

SYNC

ACK

EOP

1. USB_EPx.RXFDC
USB_EPx.RXFD
2. FIFO ENDPx (USB_EPx.RXFC = 1)
3. SCTDONE (SCTDONE = 1)
a)

) EPSTALL

34 (, , ) SETUP/OUT (USB Device)

19.6 SETUP/OUT (Usb Host)


( USB_HTXA),
( USB_HTXE) token ( USB_HTXT).
USB_HTXFD.
64 . 64
FIFO. 1 USB_HTXFDC FIFO 0.
FIFO.
TREQ USB_HTXC. Host Setup/Out
.
TDONE = 1 ( USB_HIS).
1. PID
USB_HRXP.
NAK ( 35), NAKRXED = 1 (
USB_HRXS).
STALL ( 35), STALLRXED = 1 (
USB_HRXS).
ACK ( 35), ACKRXED = 1 (
USB_HRXS).

131

19861, 19861, 19861, 19861QI, 198614


USB_HTXE
EPADDR[3:0]
USB_HTXA
DEVADDR[6:0]
USB_HTXT
TTYPE[1:0]

USB_HTXE
EPADDR[3:0]

ENDP
USB_HTXA
DEVADDR[6:0]

ADDR

USB_HTXT
TTYPE[1:0]

TREQ = 1
(USB_HTXC)

USB_HTXA
DEVADDR[6:0]

ADDR

USB_HTXT
TTYPE[1:0]

2/3

TREQ = 1
(USB_HTXC)

SYNC

SETUP

ADDR

SYNC

NAK

EOP

NAKRXED = 1
(USB_HRXS)

ENDP

CRC5

TDONE = 1
(USB_HTXC)

TDONE (TDONE = 1)

EOP

USB_HTXE
EPADDR[3:0]

ENDP

ENDP

ADDR

2/3

TREQ = 1
(USB_HTXC)

SYNC

OUT

ADDR

SYNC

STALL

EOP

STALLRXED = 1
(USB_HRXS)

ENDP

CRC5

EOP

SYNC

OUT

ADDR

ENDP

CRC5

EOP

DATA0/1
FIFO

TDONE = 1
(USB_HTXC)

SYNC

DATA0/1

SYNC

ACK

DATA

CRC16

EOP

EOP

TDONE (TDONE = 1)

ACKRXED = 1
(USB_HRXS)

TDONE = 1
(USB_HTXC)

1. FIFO ENDPx (USB_HTXFDC = 1)


2. TDONE (TDONE = 1)
a) SETUP NAK

) OUT STALL

) OUT ACK

35 (, , ) SETUP/OUT (USB Host)

19.7 IN (Usb Host)


( USB_HTXA),
( USB_HTXE) token ( USB_HTXT).
TREQ USB_HTXC. Host IN .
TDONE = 1 ( USB_HIS).
1. PID
USB_HRXP.
NAK ( 36), NAKRXED = 1 (
USB_HRXS).
STALL ( 36), STALLRXED = 1 (
USB_HRXS).
DATA0/DATA1 ( 36),
FIFO .
. USB_HRXFD.
USB_HRXFDC.
FIFO 1 USB_HRXFC.
DATASEQ USB_HRXS (0 DATA0, 1
DATA1).

132

19861, 19861, 19861, 19861QI, 198614


USB_HTXE
EPADDR[3:0]
USB_HTXA
DEVADDR[6:0]
USB_HTXT
TTYPE[1:0]

USB_HTXE
EPADDR[3:0]

ENDP
USB_HTXA
DEVADDR[6:0]

ADDR

USB_HTXT
TTYPE[1:0]

TREQ = 1
(USB_HTXC)

USB_HTXA
DEVADDR[6:0]

ADDR

USB_HTXT
TTYPE[1:0]

TREQ = 1
(USB_HTXC)

SYNC

IN

ADDR

SYNC

NAK

EOP

NAKRXED = 1
(USB_HRXS)

ENDP

CRC5

TDONE = 1
(USB_HTXC)

EOP

USB_HTXE
EPADDR[3:0]

ENDP

ADDR

TREQ = 1
(USB_HTXC)

SYNC

IN

ADDR

SYNC

STALL

EOP

STALLRXED = 1
(USB_HRXS)

ENDP

CRC5

EOP

SYNC

SYNC

TDONE = 1
(USB_HTXC)

IN

DATA0/1

ADDR

ENDP

DATA

CRC5

CRC16

EOP

EOP

FIFO

SYNC
TDONE (TDONE = 1)

ENDP

ACK

EOP

TDONE (TDONE = 1)
TDONE = 1
(USB_HTXC)
1. USB_HRXFDC
USB_HRXFD
2. FIFO (USB_HRXFC = 1)
3. TDONE (TDONE = 1)

a) IN NAK

) IN STALL

) IN c

36 (, , ) IN (USB Host)

19.8 SOF (Usb Host)


SOF Full speed
SOFEN USB_HTXSE. FSPL = 1 (
USB_TXLC), SOF 1 . FSPL = 0,
EOP 1 .
SOF SOFS = 1 ( USB_HIS).
1.
.
48 48000 1 .
USB_HSTM. ,
.

133

19861, 19861, 19861, 19861QI, 198614

19.9 USB

128 USB

0x4001_0000

0x380
0x384

USB

USB

USB_HSCR
USB_HSVR

USB
USB

0x00
0x04

HOST
USB_HTXC
USB_HTXT

0x08
0x0C
0x10
0x14

USB_TXLC
USB_HTXSE
USB_HTXA
USB_HTXE

0x18,
0x1C

USB_HFN_L
USB_HFN_H

0x20
0x24

USB_HIS
USB_HIM

0x28
0x2C
0x30

USB_HRXS
USB_HRXP
USB_HRXA

0x34

USB_HRXE

0x38

USB_HRXCS


PID
,
.
,
.

0x3C

USB_HSTM

0x80

USB_HRXFD

0x88,
0x8C
0x90

USB_HRXFDC_L
USB_HRXFDC_H
USB_HRXFC

0xC0
0xD0

USB_HTXFD
USB_HTXFDC

USB
SOF

SOF

SLAVE

0x100
0x110
0x120
0x130
0x104
0x114
0x124
0x134

USB_SEP0.CTRL
USB_SEP1.CTRL
USB_SEP2.CTRL
USB_SEP3.CTRL
USB_SEP0.STS
USB_SEP1.STS
USB_SEP2.STS
USB_SEP3.STS

134

19861, 19861, 19861, 19861QI, 198614


0x108
0x118
0x128
0x138

USB_SEP0.TS
USB_SEP1.TS
USB_SEP2.TS
USB_SEP3.TS

0x10C
0x11C
0x12C
0x13C

USB_SEP0.NTS
USB_SEP1.NTS
USB_SEP2.NTS
USB_SEP3.NTS

0x140
0x144
0x148
0x14C
0x150

USB_SC
USB_SLS
USB_SIS
USB_SIM
USB_SA
USB_SFN_L
USB_SFN_H

NAK

0x154,
0x158

SLAVE
USB
SLAVE
SLAVE


0x180
0x200
0x280
0x300

USB_EP0.RXFD
USB_EP1.RXFD
USB_EP2.RXFD
USB_EP3.RXFD

0x188,
0x18C
0x208,
0x20C
0x288,
0x28C
0x308,
0x30C

USB_EP0.RXFDC_L
USB_EP0.RXFDC_H
USB_EP1.RXFDC_L
USB_EP1.RXFDC_H
USB_EP2.RXFDC_L
USB_EP2.RXFDC_H
USB_EP3.RXFDC_L
USB_EP3.RXFDC_H

0x190
0x210
0x290
0x310

USB_EP0.RXFC
USB_EP1.RXFC
USB_EP2.RXFC
USB_EP3.RXFC

0x1C0
0x240
0x2C0
0x340

USB_EP0.TXFD
USB_EP1.TXFD
USB_EP2.TXFD
USB_EP3.TXFD

0x1D0
0x250
0x2D0
0x350

USB_EP0.TXFC
USB_EP1.TXFC
USB_EP2.TXFC
USB_EP3.TXFC

135

19861, 19861, 19861, 19861QI, 198614

19.9.1 USB_HSCR
129 USB_HSCR

318
U
0

7
R/W
0
DPULL
DOWN

6
R/W
0
DPULL
UP

5
R/W
0
D+
PULL
DOWN

4
R/W
0
D+
PULL
UP

3
R/W
0

2
R/W
0

1
R/W
0

0
R/W
0

EN
RX

EN
TX

RESET
CORE

HOST
MODE

130 USB_HSCR

318
7


DPULLDOWN

DPULLUP

D+
PULLDOWN

D+
PULLUP

EN_RX

EN_TX

RESET_CORE

HOST_MODE

D0
1
D0
1
D+
0
1
D+
0
1
USB
0
1

USB
0
1


1 ( 10
USBCLK)
0

1 HOST
0 Device

19.9.2 USB_HSVR
131 USB_HSVR

318
U
0
-

74
RO
0
REVISION

30
RO
0
VERSION

132 USB_HSVR

318
74
30


REISION
VERSION

136

19861, 19861, 19861, 19861QI, 198614

19.9.3 HOST
USB_HTXC
133 USB_HTXC

314
U
0
-

3
R/W
0
ISOEN

2
R/W
0
PREEN

1
R/W
0
SOFS

0
R/W
0
TREQ

134 USB_HTXC

314
3


ISOEN

PREEN

SOFS

TREQ


1 , ACK
. , TRANS_TYPE_REG
IN_TRANS OUTDATA0_TRANS.
.
0

1 .
host low speed .

full speed
FULL_SPEED_LINE_RATE_BIT.
SOF
1 SOF.
SOF
0

1 ,

0

USB_HTXT
135 USB_HTXT

312
U
0
-

1
R/W
0

0
R/W
0
TTYPE

136 USB_HTXT

312
10


TTYPE


00 setup_trans
01 in_trans
10 outdata0_trans
01 outdata1_trans

137

19861, 19861, 19861, 19861QI, 198614


USB_HTXLC
137 USB_HTXLC

315
U
0
-

4
R/W
0
FSLR

3
R/W
0
FSLP

2
R/W
0
DC

1
0
R/W
R/W
0
0
TXLS[1:0]

138 USB_HTXLC

315
4

10


FSLR

1 12 .
0 1,5

FSPL

1 FULL SPEED USB


0 LOW SPEED USB

DC

host full speed , full speed


.
low speed ,
low speed , low
speed , full speed
.
USB
1 USB
.
0
DIRECT_CONTROL_BIT,
USB.
TX_LINE_STATE[0] = DTX_LINE_STATE[1] = D+

TXLC[1:0]

USB_HTXSE
139 USB_HTXSE

311
U
0
-

0
R/W
0
SOFEN

140 USB_HTXSE

31
1
0

,
.

SOFEN

1 FULL_SPEED_LINE_POLARITY_BIT ,
SOF 1 . SOF
full speed
FULL_SPEED_LINE_RATE_BIT.
FULL_SPEED_LINE_POLARITY_BIT ,
EOP 1 .
low speed (
)
0 SOF/EOP
suspend .

138

19861, 19861, 19861, 19861QI, 198614


USB_HTXA
141 USB_HTXA

317
U
0
-

60
R/W
0
DEVADDR[6:0]

142 USB_HTXA

317
60


DEVADDR[6:0]

USB Device address.

USB_HTXE
143 USB_HTXE

314
U
0
-

30
R/W
0
EPADDR[3:0]

144 USB_HTXE

314
30


EPADDR[3:0]

Endpoint address.

USB_HFN
145 USB_HFN

3111
U
0
-

100
R/W
0
FNUM[10:0]

146 USB_HFN

3111
100


FNUM[10:0]

139

19861, 19861, 19861, 19861QI, 198614


USB_HIS
147 USB_HIS

314
U
0
-

3
R/W
0
SOFS

2
R/W
0
CONEV

1
R/W
0
RESUME

0
R/W
0
TDONE

148 USB_HIS

314
3


SOFS

CONEV

RESUME

TDONE

1 , SOF .
1.
0 SOF
1 ,
.
1.
0
1 ,
. 1.
0 .
1 , .
1.
0 .

USB_HIM
149 USB_HIM

314
U
0
-

3
R/W
0
SOFS
IE

2
R/W
0

1
R/W
0

CONEVIE

RESUMEIE

0
R/W
0
TDONE
IE

150 USB_HIM

314
3


SOFIE

CONEVIE

RESUMEIE

TDONEIE

0
1
0
1

0
1 SOF
0

140

19861, 19861, 19861, 19861QI, 198614


USB_HRXS
151 USB_HRXS

31
8
U
0

R/W
0

R/W
0
NAK
RXED

R/W
0
RX
TO

R/W
0
BSER
R

R/W
0

DATASEQ

R/W
0
STALL
RXED

R/W
0

R/W
0
ACK
RXED

RXOF

CRCER

152 USB_HRXS

ACK
RXED

IN_TRANS,
. DATA0 = 0,
DATA1 = 1.
1 ACK
0 ACK

STALL
RXED

1 STALL
0 STALL

318
7


DATASEQ

NAK
RXED
RXTO

RXOF

BSERR

CRCERR

1 NAK
0 NAK
1
0
1 FIFO
0
1 stuff
0 stuff
1 CRC
0 CRC

USB_HRXP
153 USB_HRXP

314
U
0
-

30
R/W
0
RPID[3:0]

154 USB_HRXP

314
30


RPID[3:0]

Packet identifier

141

19861, 19861, 19861, 19861QI, 198614


USB_HRXA
155 USB_HRXA

317
U
0
-

60
R/W
0
RADDR[6:0]

156 USB_HRXA

317
60


RADDR[6:0]

USB_HRXE
157 USB_HRXE

314
U
0
-

30
R/W
0
RXENDP[3:0]

158 USB_HRXE

314
30


RXENDP[3:0]

USB_HRXCS
159 USB_HRXCS

312
U
0
-

10
R/W
0
RXLS[1:0]

160 USB_HRXCS

312
10


RXLS[1:0]

USB:
DISCONNECT = 0
LOW_SPEED_CONNECT = 1
FULL_SPEED_CONNECT = 2

142

19861, 19861, 19861, 19861QI, 198614


USB_HSTM
161 USB_HSTM

318
U
0
-

70
R/W
0
HSTM[7:0]

162 USB_HSTM

318
70


HSTM[7:0]

,
.

SOF ,
SOF. 48MHz 48000
1 .
,

USB_HRXFD
163 USB_HRXFD

318
U
0
-

70
R/W
0
RX
FIFO
DATA[7:0]

164 USB_HRXFD

318
70


RX
FIFO
DATA[7:0]

,
.

IN_TRANS,
,
.

USB_HRXDC
165 USB_HRXDC

3116
U
0
-

15..0
R/W
0
FIFO
DATA
COUNT[15:0]

166 USB_HRXDC

3116
150


FIFO
DATA
COUNT[15:0]

143

19861, 19861, 19861, 19861QI, 198614


USB_HRXFC
167 USB_HRXFC

311
U
0
-

0
R/W
0
FIFO
FORCE
EMPTY

168 USB_HRXFC

311
0


FIFO
FORCE
EMPTY

1 FIFO

USB_HTXFD
169 USB_HTXFD

318
U
0

7..0
R/W
0
TX
FIFO
DATA[7:0]

170 USB_HTXFD

318
70


TX
FIFO
DATA[7:0]

,
.

OUTDATA0_TRANS
OUTDATA1_TRANS,

USB_HTXFC
171 USB_HTXFC

311
U
0
-

0
R/W
0
FIFO
FORCE
EMPTY

172 USB_HTXFC

311
0


FIFO
FORCE
EMPTY

,
.

1 FIFO

144

19861, 19861, 19861, 19861QI, 198614

19.9.4 USB Slave (Device)


USB_SEP0.CTRL
USB_SEP1.CTRL
USB_SEP2.CTRL
USB_SEP3.CTRL
173 SEP[x].CTRL

315
U
0
-

4
R/W
0
EPISOEN

3
R/W
0
EPSSTALL

2
R/W
0
EPDATASEQ

1
R/W
0
EPRDY

0
R/W
0
EPEN

174 USB_SEPx.CTRL

315
4


EPISOEN

EPSSTALL

EPDATASEQ

EPRDY

EPEN

1
0
-

1 , ,
STALL
0 STALL
1 IN DATA1
0 IN DATA0
1
0
,
.
0
1 .
0
, .
,
, NAK

145

19861, 19861, 19861, 19861QI, 198614

USB_SEP0.STS
USB_SEP1.STS
USB_SEP2.STS
USB_SEP3.STS
175 SEP[x].STS

318
U
0
-

7
R/W
0
SC
DATA
SEQ

6
R/W
0
SC
ACK
RXED

5
R/W
0
SC
STALL
SENT

4
R/W
0

3
R/W
0

NAK
SENT

SC
RXTO

2
R/W
0
SC
RXOF

1
R/W
0
SC
BS
ERR

0
R/W
0
SC
CRC
ERR

176 USB_SEPx.STS


SC
DATA
SEQ
SC
ACK
RXED
SC
STALL
SENT
SC
NAK
SENT
SC
RXTO

OUT_TRANS,
DATA0 = 0, DATA1= 1.

SC
RXOF

1 FIFO

0

SC
BS
ERR
SC
CRC
ERR

1 STUFF

0
1 CRC

318
7

1 ACK
0
1 STALL
0 STALL
1 NAK
0 NAK
1

0

146

19861, 19861, 19861, 19861QI, 198614


USB_SEP0.TS
USB_SEP1.TS
USB_SEP2.TS
USB_SEP3.TS
177 SEP[x].TS

312
U
0
-

1
0
R/W
R/W
0
0
SCTTYPE[1:0]

178 SEP[x].TS

312
10


SCTTYPE[1:0]

,
ENDPOINT_READY_BIT 1 0.
SC_SETUP_TRANS = 0
SC_IN_TRANS = 1
SC_OUTDATA_TRANS = 2

USB_SEP0.NTS
USB_SEP0.NTS
USB_SEP0.NTS
USB_SEP0.NTS
179 SEP[x].NTS

312
U
0
-

1
0
R/W
R/W
0
0
NTTYPE[1:0]

180 USB_SEPx.NTS

312
10


NTTYPE[1:0]

,
NAK
SC_SETUP_TRANS = 0
SC_IN_TRANS = 1
SC_OUTDATA_TRANS = 2

147

19861, 19861, 19861, 19861QI, 198614


USB_SC
181 USB_SC

316
U
0

5
R/W
0

4
R/W
0

3
R/W
0

SCFSR

SCFSP

SCDC

2
1
R/W
R/W
0
0
SCTXLS
[1:0]

0
R/W
0
SCGEN

182 USB_SC

316
5


SCFSR

SCFSP

SCDC

21

SCTXL[1:0]

SCGEN


1 12 /
0 1.5 /
USB
1 FULL SPEED
0 LOW SPEED
USB
1
0
SC_DIRECT_CONTROL_BIT,
SC_TX_LINE_STATE
USB
SC_TX_LINE_STATE [1] = D+
SC_TX_LINE_STATE [0] = D1
0

USB_SLS
183 SLS

312
U
0
-

1
0
R/W
R/W
0
0
SCRXLS[1:0]

184 SLS

312
10


SCRXLS[1:0]

USB
RESET = 0
LOW_SPEED_CONNECT = 1
FULL_SPEED_CONNECT = 2

148

19861, 19861, 19861, 19861QI, 198614


USB_SIS
185 SIS

315
U
0

4
R/W
0
SC
NAK
SENT

3
R/W
0
SC
SOF
REC

2
R/W
0
SC
RESET
EV

1
R/W
0

0
R/W
0

SC
RESUME

SC
TDONE

186 USB_SIS

315
4

1
0


SC
NAK
SENT
SC
SOF
REC
SC
RESET
EV
SC
RESUME
SC
TDONE

1, NAK.
1
1, SOF.
1
1,
USB. 1
1,
. 1
1 .
1

USB_SIM
187 SIM

315
U
0
-

4
R/W
0
SC
NAK
SENT
IE

3
R/W
0

2
R/W
0

1
R/W
0

0
R/W
0

SC
SOF
RECIE

SC
RESET
EVIE

SC
RESUME
IE

SC
TDONE
IE

188 B_SIM

315
4


SC
NAK
SENT
IE
SC
SOF
RECIE
SC
RESET
EVIE
SC
RESUME
IE
SC
TDONE
IE

NAK
1
0
SOF
1
0

1
0

1
0

1
0

149

19861, 19861, 19861, 19861QI, 198614


USB_SA
189 SA

317
U
0
-

60
R/W
0
SDEVADDR[6:0]

190 SA

317
60


SDEVADDR
[6:0]

USB Device

USB_SFN
191 SFN

3111
U
0
-

100
R/W
0
FRAME
NUM [10:0]

192 SFN

3111
100


FRAME
NUM [10:0]

SOF

USB_SEP0.RXFD
USB_SEP1.RXFD
USB_SEP2.RXFD
USB_SEP3.RXFD
193 SEP[x].RXFD

318
U
0
-

70
R/W
0
RX
FIFO
DATA[7:0]

194 SEP[x].RXFD

318
70


RX
FIFO
DATA[7:0]

OUTDATA_TRANS SETUP_TRANS ,
RX_FIFO_DATA

150

19861, 19861, 19861, 19861QI, 198614


USB_SEP0.RXFDC
USB_SEP1.RXFDC
USB_SEP2.RXFDC
USB_SEP3.RXFDC
195 SEP[x].RXFDC

3116
U
0

150
R/W
0
FIFO
DATA
COUNT [15:0]

196 SEP[x].RXFDC

3116
150


FIFO
DATA
COUNT [15:0]

, FIFO

USB_SEP0.RXFC
USB_SEP1.RXFC
USB_SEP2.RXFC
USB_SEP3.RXFC
197 SEP[x].RXFC

311
U
0
-

0
R/W
0
FIFO
FORCE
EMPTY

198 SEP[x].RXFC

311
0


FIFO
FORCE
EMPTY

1 FIFO

151

19861, 19861, 19861, 19861QI, 198614


USB_SEP0.TXFD
USB_SEP1.TXFD
USB_SEP2.TXFD
USB_SEP3.TXFD
199 SEP[x].TXFD

70
R/W
0
TX
FIFO
DATA[7:0]

318
U
0
-

200 SEP[x].TXFD

318
7...0


TX
FIFO
DATA [7:0]

IN_TRANS FIFO

USB_SEP0.TXFDC
USB_SEP1.TXFDC
USB_SEP2.TXFDC
USB_SEP3.TXFDC
201 SEP[x].TXFDC

311
U
0
-

0
R/W
0
FIFO
FORCE
EMPTY

202 SEP[x].TXFDC

311
0


FIFO
FORCE
EMPTY

,
.

1 FIFO

152

19861, 19861, 19861, 19861QI, 198614

20

CAN


CAN. CAN-,
CAN 2.0A 2.0B
1 /.

CAN_TX

...
CAN_L

CAN1
CAN_RX

CAN_H

1986BE91

CAN

...

CAN1

Rt

CAN_RX

CAN_TX

CAN_L

CAN_H

CAN2

CAN

Rt

CAN

CAN
Rt

CAN2

37 CAN
CAN
. CAN .
.
CAN .
( )
,
.
:
CAN CAN 2.0 A B
1 /
32 /

32

153

19861, 19861, 19861, 19861QI, 198614

20.1
CAN- :
, ,
.
( CAN_STATUS: ROM = 0, STM = 0).
CAN_TX CAN_RX .
CAN
TX

CAN_TX

RX

CAN_RX

38

ACK ( CAN_CONTROL
SAP ROP).

Receive Only Mode ( CAN_STATUS:


ROM = 1, STM = 0).
CAN , , ..
1, .
CAN
TX

RX

=1

CAN_TX

CAN_RX

39 Receive Only Mode

Self Test Mode ( CAN_STATUS: STM = 1,


ROM = 0).
CAN_TX CAN_RX ,
.
CAN
TX

CAN_TX

RX

CAN_RX

154

19861, 19861, 19861, 19861QI, 198614


40 Self Test Mode

ACK (
CAN_CONTROL SAP ROP).
.
.
CAN
TX

CAN_TX

RX

CAN_RX

41
CAN- .
CAN ,
. CAN-
. CAN CAN-. , CAN ,
. CAN- 1986 32
32 , CAN-,
.

20.2
,
. ,
. CAN
:

,
;


.
,
. , ,
, ;



. ,
ISO 11898-1. CAN
;

CAN .
.
.
. 11
, , 29 ,
.

155

19861, 19861, 19861, 19861QI, 198614


CAN
, ID .

. DLC
0 8 .
CRC.
, ACK ,
,
. ,
.

.

20.3 (Data Frame)


7 :
(SOF-start of frame);
(arbitration field);
(control field);
(data field);
CRC (CRC field);
(ACK field);
(end of frame).
.

Start of Frame
Arbitration Field
Control Field
Data Field
CRC Field
ACK Field
END of Frame

42 CAN
CAN ,
.
. , ,
, .

20.3.1 (Start of frame)



. .
, . ,
, .

156

19861, 19861, 19861, 19861QI, 198614

20.3.2 (Arbitration field)


:
11
RTR-.

Control field

Data field

CRC field

Delimiter

Byte7

Bit 0

...

...

Byte1

Bit 14

Byte0

Bit 0

Bit 7

Byte0

Bit 0

Bit 1

R0

Bit 3

IDE

RTR

Bit 18

DLC

Bit 19

...

Bit 27

Bit 28

SOF

Standart ID

...

Arbitration field

Bit 2

43
29
, SRR-, IDE- RTR-.
Data field

CRC field

Delimiter

Byte7

Bit 0

...

...

Byte1

Bit 14

Byte0

Bit 0

Bit 7

Byte0

Bit 0

Bit 1

Bit 2

R0

R1

RTR

Bit 0

DLC

Bit 1

...

Bit 16

IDE

Bit 17

SSR

Bit 18

Bit 19

...

Bit 27

SOF

Bit 28

Control field
Extended ID

...

Arbitration field
Standart ID

Bit 3

44

. 11
Standart ID .
Bit28 Bit18. Bit18. 7 (Bit28 Bit 22)
.
. ,
29 . :
Standart ID 11 ;
Extended ID 18 .
Standart ID 11 . Bit28 Bit18.
. Standart ID
.
Extended ID 18 . Bit17 Bit0.
RTR .
RTR
. RTR
. RTR
. Standart ID,
IDE SRR. Extended ID SRR .
SRR ( )
. SRR .
RTR . , RTR
.
,
, Standart ID ,
.

157

19861, 19861, 19861, 19861QI, 198614

IDE ( )

IDE :
;
.
IDE ,
IDE .

20.3.3 (Control field)


.
.
: (DLC), IDE,
(. ), r0.

r1 r0.
, .
(Data length code)
.
, 4 , .
: {0,1, ., 7,8}. .

20.3.4 (Data field)


, .
0 8 , 8 , ,
.

20.3.5 CRC (CRC field)


CRC CRC . 15
CRC , :
, , , ( ).
CRC CRC,
.

20.3.6 (ACK field)


:
.
. , (CRC
), ,
.

20.3.7 (End of frame)



, .

158

19861, 19861, 19861, 19861QI, 198614

20.3.8 (Remote frame)


, ,
-, .
,
. :
(Start of frame);
(Arbitration field);
(Control field);
CRC (CRC field);
(ACK field);
(End of frame).
, RTR
. .
0 8.
. RTR ,
.

20.3.9
,
.
( ).
, ,
.
, ,
, .
, ,
.
, ,
.
CAN ,
.
, .
-
.
,
. A C
, B ,
. B
. , ;
, .
. .
,
. ,
. , CAN
.

159

19861, 19861, 19861, 19861QI, 198614






-
-
-
-

45 CAN
CAN
ID_LOWER.


CAN

CAN

RX

46 - CAN

160

19861, 19861, 19861, 19861QI, 198614

20.4
CAN
. .

( 0 CAN1, 1 CAN2 PER_CLOCK).
CAN_CLOCK CANyCLKEN,
CAN, HCLK
CAN .
CAN,
.
CAN,
CAN. SB,
SJW, SEG2, SEG1, PSEG BRP CAN_BITTMNG.
EN ( )
RXTXn (1 , 0 ) BUF_xx_CON.
CANEN
CONTROL. CAN .

20.5

(
CAN_BUF[x].ID, CAN_BUF[x].DLC, CAN_BUF[x].DATAL CAN_BUF[x].DATAH),
TX_REQ.
. TX_REQ
. ,
PRIOR_0.
PRIOR_0, .
, ,
. ID
CAN ( ) . ID
.

20.6 Remote Transmit Request (RTR)


Remote Transmit Request
,
, RTR .
INT_TX .
(BUFF_CON[x]) , TX_REQ = 0,
PRIOR_0,
RTR (RTR_EN=1), RX_TX = 0
EN = 1 .
SID EID, BUF_xx_DLC ( )
DLC. CAN_BUF[x].DATAL
CAN_BUF[x].DATAH .
CAN .
RTR ,
, .

20.7

161

19861, 19861, 19861, 19861QI, 198614



, . CAN
, .

20.8
,
CAN .
(CAN_BUF_FILTER[x].MASK)
(CAN_BUF_FILTER[x].FILTER) ,
, :
ID & CAN_BUF_FILTER[x].MASK == CAN_BUF_FILTER[x].FILTER
,
.
, .
CAN_BUF_FILTER[x].MASK
CAN_BUF_FILTER[x].FILTER ,
, .
.
.

20.9
.
,
,
OVER_EN. OVER_WR. ,
,
OVER_WR. 1, OVER_WR (
RX_FULL), ,
OVER_WR , , RX_FULL.
.

, ,
, ,
.

, . OVER_WR,
OVER_WR , ,
.

20.10
CAN . CAN
(NRZ).
. ,
. ,
DPLL.
CAN 1 /.
Nominal Bit Time
TBIT = 1/
DPLL Time Quanta (TQ).
4 :
Synchronization Segment (Sync_Seg);

162

19861, 19861, 19861, 19861QI, 198614

Propagation Time Segment (PSEG);


Phase Buffer Segment 1 (SEG1);
Phase Buffer Segment 2 (SEG2).

Nominal Bit Time 8 25 TQ.



Nominal Bit Time = TQ * (Sync_Seg + PSEG + SEG1 + SEG2)
TQ
BRP 1 65536:
TQ (s) = ((BRP+1))/CLK (MHz)

TQ (s) = ((BRP+1)) * Tclk (s)

47
Synchronization Segment
, .
1 TQ. ,
.
Propagation Time Segment
,
.
1 8 TQ
Phase Buffer Segments
,
.
1 8 TQ.

20.11

; ,
, DPLL
.
Hard Synchronization

. , DPLL
, Sync_Seg.
Resynchronization
Sync_Seg, Phase
Segment 1 , Phase Segment 2 ,
. Phase Segment 1 Phase Segment 2

163

19861, 19861, 19861, 19861QI, 198614


,
Synchronization Jump Width (SJW).

20.12
CAN
, .
,
, .
( , CRC )
( ).
, .
, . ,
, STATUS
FRAME_ERR.
8-


1 ()

1 1

1 1 1

64

15

3
0 ()

ACK
ACK
CRC
CRC


()
IDE()
RTR()

48

. ,
, ,
STATUS ACK_ERR.
8-


1 ()

1 1

1 1 1

64

15

3
0 ()


ACK



, ,

,

.

ACK
CRC
CRC


()
IDE()
RTR()

49
CAN 15- CRC,
.
4-
CRC. CRC , ,

164

19861, 19861, 19861, 19861QI, 198614


STATUS
CRC_ERR.
8-


1 ()

1 1 1

64

15

3
0 ()

CRC

ACK
ACK
CRC
CRC


()


15
CRC

IDE()
RTR()

50 CRC
, ,
. , CAN- ,
. ,
,
, . ,
, STATUS
BIT_ERR,
. , ,

.
8-


1 ()

1 1

1 1 1

64

15

3
0 ()


ACK

ACK
CRC
CRC


()
IDE()
RTR()

51
CAN ().
;
,
BIT_STUF_ERR.

, . CAN
.

165

19861, 19861, 19861, 19861QI, 198614


CAN
, .
/

n+1 n+2 n+3 n+4 n+5 n+6 n+7

n+1 n+2 n+3 n+4 n+5

n+6 n+7

52
CAN .
( STATUS, RX_ERR_CNT)
( STATUS, TX_ERR_CNT).
. 128,
CAN error passive.
,
.
255, CAN bus-off
. ( CAN- Error
Active) ,
CAN-, CAN (
) , 128 11 = 1408 .

STATUS. / error passive
RX_ERR_CNT TX_ERR_CNT , error
active.

Error Active
RX_ERR_CNT>127

TX_ERR_CNT>127

RX_ERR_CNT<128
TX_ERR_CNT<128

Error Passive

12811
128
11

Bus Off
TX_ERR_CNT>255

53
CAN . -,
CAN_STATUS
.
ERROR_OVER.

166

19861, 19861, 19861, 19861QI, 198614


CAN_OVER. , CAN_OVER
.

20.13
CAN
. :
( );
( );
.
-
, . CAN
, ,
.
, .

. /

CAN_INT_TX/CAN_INT_RX.
, (. CAN_INT_EN).
CAN_STATUS
CAN_INT_RX

CAN_INT_EN

CAN_RX
CAN_INT_RX 0

&

CAN_INT_RX 1

&

CAN_INT_RX 2

&

CAN_INT_RX 3

&

CAN_INT_RX 4

&

CAN_INT_RX 30

&

CAN_INT_RX 31

&

CAN_RX 0
CAN_RX 1
CAN_RX 2
CAN_RX 3
CAN_RX 4

CAN_RX 30
CAN_RX 31

GLB_INT_EN

RX_READY

RX_INT_EN

&

TX_INT_EN

&

ERR_INT_EN

&

CAN_INT_TX
CAN_TX
CAN_INT_TX 0

&

CAN_INT_TX 1

&

CAN_INT_TX 2

&

CAN_INT_TX 3

&

CAN_TX 0
CAN_TX 1
CAN_TX 2
CAN_TX 3
CAN_INT_TX 4
CAN_TX 4

TX_READY

CAN_INT

&

&
ACK_ERR

CAN_INT_TX 30

&

FRAME_ERR

CAN_INT_TX 31

&

CRC_ERR

CAN_TX 30
CAN_TX 31

BITSTAFF_ERR
BIT_ERR
ERR_OVER

ERR_OVER_INT
_EN

&

54 CAN

167

19861, 19861, 19861, 19861QI, 198614

20.14 CAN
203 CAN

0x4000_0000
0x4000_8000

0x00
0x04
0x08
0x10

CAN1
CAN2

CAN1
CAN2

CAN_CONTROL
CAN_STATUS
CAN_BITTMNG
CAN_INT_EN

CAN
CAN

0x1C

CAN_OVER

0x20
0x24
0x28
0x2C

CAN_RXID
CAN_RXDLC
CAN_RXDATAL
CAN_RXDATAH

ID
DLC

0x30
0x34
0x38
0x3C

CAN_TXID
CAN_TXDLC
CAN_DATAL
CAN_DATAH

ID
DLC

0x40

01

0xBC

CAN_BUF_01_CON

CAN_BUF_32_CON

0xC0
0xC4
0xC8

CAN_INT_RX
CAN_RX
CAN_INT_TX

0xCC

CAN_TX


RX_FULL

~TX_REQ

0x200
0x204
0x208
0x20C
0x210

BUF_01_ID
BUF_01_DLC
BUF_01_DATAL
BUF_01_DATAH
BUF_02_ID

BUF_32_DATAH

ID 01
DLC 01
01
01
ID 02

BUF_01_MASK
BUF_01_FILTER
BUF_02_MASK

BUF_32_FILTER

01
01
02

0x4FC
0x500
0x504
0x508
0x5FC

32

32

32

168

19861, 19861, 19861, 19861QI, 198614

20.14.1 CANx_CONTROL
204 CONTROL

315
U
0

4
R/W
0

3
R/W
0

2
R/W
0

1
R/W
0

ROP

SAP

STM

ROM

0
R/W
0
CAN
EN

205 CONTROL

315
4


ROP

SAP

STM

ROM

CAN_EN

Receive own packets


1
0
Send ACK on own packets
1
0
Self Test Mode
1
0
Read Only Mode
1
0
CAN
1
0

20.14.2 CANx_STATUS
206 STATUS

3124
RO
0
TX
ERR
CNT [7:0]
15...13
R/W
0

7
R/W
0

6
R/W
0

5
R/W
0

ACK
ERR

FRAME
ERR

CRC
ERR

23...16
RO
0
RX
ERR
CNT [7:0]
10
9
RO
RO
0
0

8
R/W
0

ERR
STATUS[1:0]

ID
LOWER

12
RO
0
TX
ERR
CNT8

11
RO
0
RX
ERR
CNT8

4
R/W
0
BIT
STUFF
ERR

3
R/W
0

2
R/W
0

1
RO
0

0
RO
0

BIT
ERR

ERROR
OVER

TX
READY

RX
READY

207 STATUS

169

19861, 19861, 19861, 19861QI, 198614

3124

2316

1513
12

11
109


TX
ERR
CNT [7:0]
RX
ERR
CNT [7:0]
TX
ERR
CNT8
RX
ERR
CNT8
ERR
STATUS[1:0]

ID
LOWER

ACK
ERR

FRAME
ERR

CRC
ERR

BIT
STUFF ERR

BIT
ERR

ERROR
OVER

TX
READY

RX
READY

,

TEC, [7:0]
TEC > 127, ERROR PASSIVE
REC, [7:0]
REC > 127, ERROR PASSIVE
TEC, 8
0 TEC 255
1 TEC 255
REC, 8
0 REC 255
1 REC 255
CAN
00 ERROR ACTIVE,

01 ERROR PASSIVE,

1x BUS OFF,

0
1

0
1

0
1

0
1

0
1

0
1
TEC REC ERROR_MAX
0 ERROR_MAX < TEC REC
1 ERROR_MAX TEC REC

0
1

0
1

170

19861, 19861, 19861, 19861QI, 198614

20.14.3 CANx_BITTMNG
208 BITTMNG

3128
U
0

27
R/W
0

SB

2625
R/W
0
SJW
[1:0]

2422
R/W
0
SEG2
[2:0]

2119
R/W
0
SEG1
[2:0]

1816
R/W
0
PSEG
[2:0]

150
R/W
0
BRP
[15:0]

209 BITTMNG

3128
27


SB

2625

SJW [1:0]

2422

SEG2 [2:0]

2119

SEG1 [2:0]

1816

PSEG[2:0]

150

BRP [15:0]

:
0
1
SJW
11 = Synchronization jump width time = 4 x TQ
10 = Synchronization jump width time = 3 x TQ
01 = Synchronization jump width time = 2 x TQ
00 = Synchronization jump width time = 1 x TQ
SJW ,
CAN.
, SJW.
SEG2
111 = Phase Segment 2 time = 8 x TQ
110 = Phase Segment 2 time = 7 x TQ
101 = Phase Segment 2 time = 6 x TQ
100 = Phase Segment 2 time = 5 x TQ
011 = Phase Segment 2 time = 4 x TQ
010 = Phase Segment 2 time = 3 x TQ
001 = Phase Segment 2 time = 2 x TQ
000 = Phase Segment 2 time = 1 x TQ
SEG2 ,
.
SEG1
111 = Phase Segment 1 time = 8 x TQ
110 = Phase Segment 1 time = 7 x TQ
101 = Phase Segment 1 time = 6 x TQ
100 = Phase Segment 1 time = 5 x TQ
011 = Phase Segment 1 time = 4 x TQ
010 = Phase Segment 1 time = 3 x TQ
001 = Phase Segment 1 time = 2 x TQ
000 = Phase Segment 1 time = 1 x TQ
SEG1 ,
.
PSEG
111 = Propagation time = 8 x TQ
110 = Propagation time = 7 x TQ
101 = Propagation time = 6 x TQ
100 = Propagation time = 5 x TQ
011 = Propagation time = 4 x TQ
010 = Propagation time = 3 x TQ
001 = Propagation time = 2 x TQ
000 = Propagation time = 1 x TQ
PSEG ,
CAN

CLK = PCLK/(BRP + 1);
TQ(us) = (BRP + 1)/CLK(MHz)

171

19861, 19861, 19861, 19861QI, 198614

20.14.4 CANx_INT_EN
210 INT_EN

315
U
0

4
U
0
ERR
OVER
INT
EN

3
R/W
0

2
R/W
0

1
R/W
0

0
R/W
0

ERR
INT
EN

TX
INT
EN

RX
INT
EN

GLB
INT
EN

211 INT_EN

315
4


ERR
OVER
INT
EN
ERR
INT
EN
TX
INT
EN
RX
INT
EN
GLB
INT
EN

TEC REC
ERROR_MAX
0
1

0
1

0
1

0
1
CAN
0
1

20.14.5 CANx_OVER
212 OVER

318
U
0
-

7...0
R/W
0
ERROR_MAX[7:0]

213 OVER

318
70


ERROR
MAX [7:0]


TEC REC,
ERROR_OVER

172

19861, 19861, 19861, 19861QI, 198614

20.14.6 CANx_BUF_xx_CON
214 BUF_CON[x]

318
U
0
-

7
R/W
0
OVER
WR

6
R/W
0
RX
FULL

5
R/W
0
TX
REQ

4
R/W
0
PRIOR
0

3
R/W
0
RTR
EN

2
R/W
0
OVER
EN

1
R/W
0
RX
TXn

0
R/W
0
EN

215 BUF_CON[x]

318
7


OVER_WR

RX_FULL

TX_REQ

PRIOR_0

RTR_EN

OVER_EN

RX_TXn

EN


0
1

0
1

0
1

0
1
RTR
1 RTR
0 RTR

1
0

1
0

1
0

20.14.7 CANx_INT_RX
216 INT_RX

310
R/W
0
CAN_INT_RX[31:0]

217 INT_RX

310


CAN_INT_RX
[31:0]

CAN_INT_RX[0]
CAN_INT_RX[1]

173

19861, 19861, 19861, 19861QI, 198614

20.14.8 CANx_RX
218 RX RX_FULL

310
RO
0
CAN_RX[31:0]

219 RX


CAN_RX[31:0]

310

,

RX_FULL
CAN_RX[0] RX_FULL
CAN_RX[1] RX_FULL ,

20.14.9 CANx_INT_TX
220 INT_TX

310
R/W
0
CAN_INT_TX[31:0]

221 INT_TX

310


CAN_INT_TX
[31:0]

20.14.10

CAN_INT_TX[0]
CAN_INT_TX[1]

CANx_TX
222 TX ~TX_REQ

31..0
RO
0
CAN_TX[31:0]

223 TX

310


CAN_TX[31:0]

,

~TX_REQ
CAN_TX[0] ~TX_REQ
CAN_TX[1] ~TX_REQ ,

174

19861, 19861, 19861, 19861QI, 198614

20.14.11
20.14.12
20.14.13

CANx_RXID
CANx_TXID
CANx_BUF_xx_ID
224 RXID, TXID CAN_BUF[x].ID

2818
R/W
0
SID
[10:0]

3129
U
0
-

170
R/W
0
EID
[17:0]

225 RXID, TXID CAN_BUF[x].ID

3129
2818

170


SID
[10:0]

EID
[17:0]

20.14.14
20.14.15
20.14.16

,
.

SID
CAN
,
.
EID
CAN
,
.

CANx_RXDLC
CANx_TXDLC
CANx_BUF_xx_DLC
226 RXDLC, TXDLC CANx_BUF_xx_DLC

3113
U
0

12
R/W
0

11
R/W
0

10
R/W
0

9
R/W
0

8
R/W
0

74
R/W
0

IDE

SSR

R0

R1

RTR

30
R/W
0
DLC
[3:0]

227 RXDLC, TXDLC CANx_BUF_xx_DLC

3113
12


IDE

11

SSR

10

R0

R1

RTR

,
.

IDE
,
1
0
SSR,
1
R0
0
R1,
1
RTR,
0
1
,
.

175

19861, 19861, 19861, 19861QI, 198614


74
30

20.14.17
20.14.18
20.14.19

DLC,
0000
0001 1
0010 2
0011 3
0100 4
0101 5
0110 6
0111 7
1000 8
1xxx .

DLC[3:0]

CANx_RXDATAL
CANx_TXDATAL
CANx_BUF_xx_DATAL
228 RXDATAL, TXDATAL CANx_BUF_xx_DATAL

3124
R/W
0
DB3[7:0]

2316
R/W
0
DB2[7:0]

158
R/W
0
DB1[7:0]

70
R/W
0
DB0[7:0]

229
RXDATAL, TXDATAL CANx_BUF_xx_DATAL

3124
2316
158
70

20.14.20
20.14.21
20.14.22


DB3[7:0]
DB2[7:0]
DB1[7:0]
DB0[7:0]

,
.
DB3, ,
DB2, ,
DB1, ,
DB0, ,

CANx_RXDATAH
CANx_TXDATAH
CANx_BUF_xx_DATAH
230 RXDATAH,
TXDATAH CANx_BUF_xx_DATAH

3124
R/W
0
DB7[7:0]

2316
R/W
0
DB6[7:0]

158
R/W
0
DB5[7:0]

70
R/W
0
DB4[7:0]

231 RXDATAH,
TXDATAH CANx_BUF_xx_DATAH

3124
2316
158
70


DB7[7:0]
DB6[7:0]
DB5[7:0]
DB4[7:0]

,
.
DB7, ,
DB6, ,
DB5, ,
DB4, ,

176

19861, 19861, 19861, 19861QI, 198614

21

52070-2003


52070-2003 ( 1553),
1553.
/ 1553:
.
. .
, .
,

16-
.

,
.
1553.
, . ,
, , VALMESS.

52070

6
PRMA+
PRMAPRDA+
PRDAPRD_PRMA

Level
shifter
3->5

BUSA

555913

6
PRMB+
PRMBPRDB+
PRDBPRD_PRMB

52070

Level
shifter
3->5

BUSB

555913

6
PRMC+
PRMCPRDC+
PRDCPRD_PRMC

Level
shifter
3->5

BUSC

555913

6
PRMD+
PRMDPRDD+
PRDDPRD_PRMD

Level
shifter
3->5

555913

BUSD

55 52070-2003
:
( 1- 6) ( 7
10) ;
: , ,
;
1 / ;
: ;
116;
116;

;
.

177

19861, 19861, 19861, 19861QI, 198614

21.1
: (),
() ().

,
, .
.
CommandWord1.
3 8 CommandWord2.
StatusWord1.
3 8 StatusWord2.
(), 5, 6 10,
ModeData. CONTROL
BCMODE RTMODE.

,
. ,
,
11111 ( ).
, ()
/ ,
/ . ,
.
CommandWord1, 3 8
CommandWord2.
StatusWord1. ,
3, .
, 5, 6 10,
ModeData.
CONTROL RTMODE BCMODE.


: ,
, .
,
.
CommandWord1, 3 8
CommandWord2. ,
, StatusWord1. 3 8
StatusWord2. ,
5, 6 10, ModeData.
CONTROL RTMODE BCMODE.
MSG.
.

178

19861, 19861, 19861, 19861QI, 198614

21.2
, , ,
.
, 52070-2003, .
, ,
.
, , . t1
t2 . t2
, , 4 , ,
, 4 12 . 14
,
.

56
660 ,
32- .
1 .
2 .
3 .
4 .
5 .
6 .
, ,
11111,
.
7 ( )
.
8 ( )
.
9 .
10 .

179

19861, 19861, 19861, 19861QI, 198614

57
-
,
(57 3) , .

21.3
( )
17 , .
.

58

180

19861, 19861, 19861, 19861QI, 198614


:
;
;
/;
/ ;
/ ;
.
,
. ,
.
00000 11110,
. 11111 , ,
.
/ ,
( ). , ,
.
/
00000 11111.
/ ,
, .
32 . ,
, ,
00000, 32.

16 . ,
17 ( )
.
:
;
;
.
,
. ,
.
,
, .
:
;
;
: , ,
, , ,
, ,
;
.
.
.
. , .

181

19861, 19861, 19861, 19861QI, 198614


CommandWord1

TX_A+, TX_B+

CommandWord2

II TX_A-, TX_B-

1Kx16

ModeData (W)

RX_A+

II RX_A-

APB

StatusWord1
StatusWord2

Mux

1Kx16
B
ModeData (R)

RX_B+

II RX_B-

59

182

19861, 19861, 19861, 19861QI, 198614

StatusWord (W)

1Kx16

ModeData (W)

APB

TX_A+, TX_B+

II TX_A-, TX_B-

RX_A+

II RX_A-


CommandWord1
CommandWord2

Mux

1Kx16
B
ModeData (R)
Status Word (R)

RX_B+

II RX_B-

60

183

19861, 19861, 19861, 19861QI, 198614

RX_A+

II RX_A-


CommandWord1
CommandWord2
APB

Mux

1Kx16
B
ModeData
Status Word1
Status Word2

RX_B+

II RX_B-

61

184

19861, 19861, 19861, 19861QI, 198614

21.4

, . MR
CONTROL . .
CONTROL DIV ,
HCLK
1 . RTMODE BCMODE
.
, ,
, (TRA ,
TRB ).
, . ,
, ,
, .
RTA4 RTA0 CONTROL ,
,
.

*((volatile unsigned int *)( 0x40051000))=0x00000001; // MR=1
*((volatile unsigned int *)( 0x40051000))= 0x00014078;
//RTMODE=1, TRB=TRA=1, RTA=1, DIV=40

*((volatile unsigned int *)( 0x40051000))=0x00000001; // MR=1
*((volatile unsigned int *)( 0x40051000))= 0x00014014;
//BCMODE=1, TRA=1,TRB=0, RTA=0,DIV=40
DIV = 40,
40 , 40 /DIV = 1.

21.5
,
.
StatusWord1.
, ,
-.

*((volatile unsigned int *)(0x40051018))=0x00000800;
5 ,
. .
.
, .
5,
, .
ModeData.

*((volatile unsigned int *)(0x40051014))=0x000055AA;
,
,
.

185

19861, 19861, 19861, 19861QI, 198614



,
, . ,
,
.
.
0x000-0xFFC (
). ,
32- . 2
.
1
addon=0x80;
for(i=1;i<=32;i++)
{
*((volatile unsigned int *)( 0x40050000+addon))=i;
addon=addon+4;
}
, 1
0x80, : n*0x80, n- (n=1-31).
,
VALMESS.
. ,
4 , ,
VALMESS.

i=*((volatile unsigned int *)(0x40051014));
i .
1
addon=0x80;
for(i=1;i<=32;i++)
{
mas[i]=*((volatile unsigned int *)(0x40050000+addon));
addon=addon+4;
}

MSG .
.

.
.

21.6
, ,
-.
BCSTART.
.
.
BCSTART
*((volatile unsigned int *)(0x4005100C))=0x00000820;
// 1
*((volatile unsigned int *)(0x40051010))=0x00000000;
// 2
*((volatile unsigned int *)(START_ADDR_APB+0x1000))=0x00014016;
//

186

19861, 19861, 19861, 19861QI, 198614

, 1 00000,
32 .
1 1.
. BCMODE,
, BCSTART,
, A (TRA=1),
40, 40 .
,
10 1.
( VALMESS ),
.
.
MR, BCSTART.

21.7
,
, .
:
;
;
, ;
.

- .

21.8 52070-2003
232 52070-2003

0x4004_8000
0x4005_0000

0000-0FFC
0x1000
0x1004
0x1008
0x100

MIL-STD-1553B1
MIL-STD-1553B2

1553 1
1553 2

DATA
CONTROL
STATUS
ERROR
CommandWord1

/



1

0x1010

CommandWord2

0x1014
0x1018
0x101
0x1020
01024

ModeData
StatusWord1
StatusWord2
INTEN
MSG


1
2

187

19861, 19861, 19861, 19861QI, 198614

21.8.1 CONTROL
233 CONTROL

31.22
U
-

21
R/W
0
AUTOTUNE

15
R/W
0
DIV4

14
R/W
0
DIV3

7
R/W
0
RTA1

6
R/W
0
RTA0

20
R/W
0
ENFILTER
13
R/W
0
DIV2
5
R/W
0
TRB

12
R/W
0
DIV1
4
R/W
0
TRA

19
R/W
0
INVTR

18
R/W
0
RERR
11
R/W
0
DIV0

3
R/W
0
RTMODE

10
R/W
0
RTA4
2
R/W
0
BCMODE

17
R/W
0
DIV6
9
R/W
0
RTA3
1
R/W
0
BCSTART

16
R/W
0
DIV5
8
R/W
0
RTA2
0
R/W
1
MR

234 CONTROL

3122
21


AUTOTUNE

20

ENFILTER

19

INVTR

18

RERR

1711

DIV6-DIV0

106

RTA4-RTA0

TRB

TRA


( 3)
0
1
NRZ ( 3)
1
0

NRZ , 555967,
.
NRZ
.
( 3)
PRD_PRMA, PRD_PRMB, PRD_PRMC, PRD_PRMD
1
0

1 MR
0 ,
IDLE
MAN_CLK 1
,
MAN_CLK, 1 . MAN_CLK
120 8. MAN_CLK
8, DIV[6:3]=(MAN_CLK/8)+1, DIV[2:0]=0,
.

, ,

RTMODE=1; BCMODE=0
.
1
0
.
1
0

188

19861, 19861, 19861, 19861QI, 198614


32

RTMODE
BCMODE


10
01
11

BCSTART

MR

.
1 .
0 .
.
.
1
0

21.8.2 STATUS
235 STATUS

316
U
-

5
RO
0
RCVB

4
RO
0
RCVA

3
RO
0
ERR

2
RO
0
VALMESS

1
RO
0
RFLAGN

0
RO
1
IDLE

236 STATUS

31...6
5


RCVB

RCVA

ERR

VALMESS

RFLAGN

IDLE

,
.


0
1

0
1
.
0
1
, RERR,
4 .
.
0 ,

1

4 .

7, 9 10.
.
0
1
1
,

.
.
1
0

189

19861, 19861, 19861, 19861QI, 198614

21.8.3 ERROR
237 ERROR

31...7
U
0
-

6
RO
0

5
RO
0

PROERR

CONERR

4
RO
0
GAPERR

3
RO
0
CSYCERR/
SEQERR

2
RO
0
DSYCERR/
SYNCERR

1
RO
0

0
RO
0

MANERR

NORCV

238 ERROR

31...7
6


PROERR

CONERR

GAPERR

CSYCERR/
SEQERR

DSYCERR/
SYNCERR

MANERR

NORCV

.
1

0
.
1
0
.
1 4

0
(CSYCERR).
1 ,

0
(SEQERR).
1
10
10
0
(SEQERR).
1

0
(DSYCERR).
1 ,

0
(SYNCERR).
1 ,

0
NRZ .
1

0
.
1 14

0

190

19861, 19861, 19861, 19861QI, 198614

21.8.4 CommandWord1
239 1 CommandWord1

31...16
U
0
-

1511
R/W
0

10
R/W
0
/

95
R/W
0
/

40
R/W
0
/

240 CommandWord1

31...16
15...11

10

9..5

4..0

,

/
1 -
0 -
,
.
, 00000 11111

.
1 52070-2003

,
.

21.8.5 CommandWord2
241 2 CommandWord2

31...16
U
0
-

1511
R/W
0

10
R/W
0

95
R/W
0
/

40
R/W
/

242 CommandWord2

31...16
15...11

10

9..5

4..0

,

/
1 -
0
,


-.
-, 10.

191

19861, 19861, 19861, 19861QI, 198614

21.8.6 ModeData
243 ModeData

31...16
U
0
-

150
R/W
0

244 ModeData

31..16
15..0


ModeData

,
.

21.8.7 StatusWord1
245 1 StatusWord1

31...16
U
0
-

15...11
R/W
0

10
R/W
0

.

75
U
0

4
R/W
0

3
R/W
0

2
R/W
0
.
.

9
R/W
0
.
1
R/W
0
.
.

8
R/W
0
.
.
0
R/W
0

246 StatusWord1

31...16
15...11

10
9
8
7..5
4
3
2
1
0

.
.
. .
.
. .
. .
. . .
.

, .
,


:
,
- (
).
.
( , )

192

19861, 19861, 19861, 19861QI, 198614

21.8.8 StatusWord2
247 2 StatusWord2

3116
U
0
-

1511
RO
0

10
RO
0

9
RO
0
.

8
RO
0
.

7..5
U
0

4
RO
0

3
RO
0

2
RO
0

.
.

1
0
RO
RO
0
0

248 StatusWord2

31...16
15...11
10
9
8
75
4
3
2
1
0



.
.
. .

, -


.
. .
. .
. . .
.

:
-
( );
-
;
.

21.8.9 INTEN
249 INTEN

314
U
-

3
R/W
0
ERRIE

2
R/W
0
VALMESSIE

1
R/W
0
RFLAGNIE

0
R/W
0
IDLEIE

250 INTEN

31..4
3


ERRIE

VALMESSIE

RFLAGNIE

.
0
1 ,

.
0
1 ,

.
0
1 ,
,

193

19861, 19861, 19861, 19861QI, 198614


0

.
0
1 ,

IDLEIE

21.8.10 MSG
251 MSG

15..14
U

13..0
RO
0

, ,
. .
.
252 MSG

CommandWord1
15:11 10
9:5
4:0

0001
-,

RTA

0080
-,

11111 0 00001-11110 XXXXX

0004
-,

RTA

0100
-,

11111 0 00001-11110 XXXXX

0402
-

RTA

1 00001-11110 XXXXX

1008
-,

0200
-,

15:11

CommandWord2
10
9:5
4:0

0 00001-11110 XXXXX

0 00001-11110 XXXXX

XXXXX 1 00001-11110 XXXXX


RTA

1 00001-11110 XXXXX

0 00001-11110 XXXXX

RTA

1 00001-11110 XXXXX

11111 0 00001-11110 XXXXX

RTA

1 00001-11110 XXXXX


0410 0-15 K=1
,

RTA

0400 0-15 K=1


,

11111 1 00000 11111 0XXXX

2420 16-31 K=1


,

RTA

1 00000 11111 1XXXX

0040 16-31 =0
,

RTA

0 00000 11111 1XXXX

0800 16-31 =0
,

1111

0 00000 11111 1XXXX

1 00000 11111 0XXXX

194

19861, 19861, 19861, 19861QI, 198614

21.8.11 DATA
/ .

( 9 5) .
32x16 32x16 .
2Kx16.

195

19861, 19861, 19861, 19861QI, 198614

22

32- ,
16- .
. ,
( , ).
32- , 16 4- /.
, .
,
/. ,
, .
4 ,
.
DMA.
:
32- , , / ;
16- ;
32- .
()
.
/ DMA;
32- (),
,
/ DMA ;
,
:
- ;
- ;
- () ;
- ;
- .

22.1
,
Fdts - ,
DMA . ,
, .
, ,
,
DMA.
60.

196

19861, 19861, 19861, 19861QI, 198614

Fdts
CNT
CCR1
CCR2

CNT

CCR3

CNT

CNT
==
ARR

CCR4

EVENT

BRK

BRK

Event
Detector

BRKo

1
/

CH0i

CH0o
CH0oe
nCH0o
nCH0oe

CH0o
nCH0o

CNT

2
/

CH1i

CH1o
CH1oe
nCH1o
nCH1oe

CH1o
nCH1o

CNT

3
/

CH2i

CH2o
CH2oe
nCH2o
nCH2oe

nCH2o

CH3o
CH3oe
nCH3o
nCH3oe

nCH3o

CH2o

CNT

4
/

CH3i

ETR

ETR

CH3o

ETRo

62
32- CNT,
/.
:
;
, ;
;
.


. .

( 14 1, 15 2, 16 3,
19 4 PER_CLOCK). TIM_CLOCK
TIMyCLKEN ( 4 UART_CLOCK),
, HCLK
.
.

197

19861, 19861, 19861, 19861QI, 198614



32- , 16-
. ,
.
, .
:
(CNT);
(PSC);
(ARR).
CNT TIM_CLK,
, TxCHO .
:
CNT;
PSG,
CLK= CLK/(PSG+1);
ARR;
CNTRL:
- EVENT_SEL;
- CNT_MODE ( 00 01
, 10 11
);
- DIR;
CNT_EN.

DMA,
.

198

19861, 19861, 19861, 19861QI, 198614

22.2
: CNT_MODE = 00, DIR = 0.
TIMERx->CNTRL = 0x00000000;//
//
TIMERx->CNT = 0x00000004;//
TIMERx->PSG = 0x00000000;//
TIMERx->ARR = 0x00000013;//
// .
TIMERx->CNTRL = 0x00000001;// TIM_CLK.

TIM_CLK
CNT_EN

CNT

04

05

06

07

08

09

0A

0B

0C

0D

PSG

0E

0F

10

11

12

13

00

01

02

03

04

DIR

63 , 0 00013,
00004
: CNT_MODE = 00, DIR = 1
TIMERx->CNTRL = 0x00000000;//
//
TIMERx->CNT = 0x00000004;//
TIMERx->PSG = 0x00000000;//
TIMERx->ARR = 0x00000013;//
// .
TIMERx->CNTRL = 0x00000009;// TIM_CLK.

TIM_CLK
CNT_EN

CNT
PSG

04

03

02

01

00

13

12

11

10

0F

0D

0C

0B

0A

09

08

07

06

05

04

03

DIR

64 , 00013 0,
00004

199

19861, 19861, 19861, 19861QI, 198614

/: CNT_MODE = 01, DIR = 0


TIMERx->CNTRL = 0x00000000;//
//
TIMERx->CNT = 0x00000004;//
TIMERx->PSG = 0x00000000;//
TIMERx->ARR = 0x00000013;//
// .
TIMERx->CNTRL = 0x00000041;// / TIM_CLK.

TIM_CLK
CNT_EN

CNT

04

05

06

07

08

09

0A

0B

0C

0D

PSG

0E

0F

10

11

12

13

12

11

10

0F

0E

DIR

65 , /,
/: CNT_MODE = 01, DIR = 1
TIMERx->CNTRL = 0x00000000;//
//
TIMERx->CNT = 0x00000004;//
TIMERx->PSG = 0x00000000;//
TIMERx->ARR = 0x00000013;//
// .
TIMERx->CNTRL = 0x00000049;// / TIM_CLK.

TIM_CLK
CNT_EN

CNT
PSG

04

03

02

01

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

DIR

66 , /,

200

19861, 19861, 19861, 19861QI, 198614

22.3
:
(TIM_CLK);
(CNT==ARR );
1: TxCHO
;
2: TxCHO
;
3: ETR .
TIMx_CH1_CNTRL
CHFLTR[3:0]

CH1

CHSEL[1:0]

RE
FE
RE CH2

Fdts

T1CHO

T2CHO

T3CHO

T4CHO

RE CH3

TIMx_CH2_CNTRL
CHFLTR[3:0]

CH2

CHSEL[1:0]

RE
FE
RE CH3

Fdts

RE CH4

TIMx_CH3_CNTRL
CHFLTR[3:0]

CH3

CHSEL[1:0]

RE
FE
RE CH4

Fdts

RE CH1

TIMx_CH4_CNTRL
CHFLTR[3:0]

CH4

CHSEL[1:0]

Fdts

RE
FE
RE CH1

TIMx_PSG

RE CH2

PSG[7:0]

TIM_CLK

/1,/2,/3,/4

ETR

FDTS[1:0]
TIMx_CNTRL

ETR

/1,/2,/3,/4

EVENT_SEL
TIMx_CNTRL

ETR_INV

ETRPSC[7:0]

ETR_FILTER[3:0]

TIMx_BRKETR_CNTRL

67

201

19861, 19861, 19861, 19861QI, 198614


(TIM_CLK)
, CNT_MODE = 0x, EVENT_SEL = 0000.
,
,
CNTRL. CNT, PSG ARR
, CNT =
ARR CNT = 0, .
(ARR) ,
ARRB_EN = 1 ( CNTRL).
,
TIM_CLK , ,
. ,
1 .
DIR , : DIR = 0
( 66), DIR = 1 ( 67). CNT_MODE =
00, DIR, CNT_MODE = 01,
/ DIR ( 68).

TIM_CLK
CNT_EN

CNT

F7

PSG

F8

F9

FA

FB

FC

FD

00

01

02

03

TIM_PSG

00

00

01

02

03

00

01

02

03

00

01

02

03

00

01

68 :
(CNT_MODE = 00, EVENT_SEL = 0000, DIR = 0)

TIM_CLK
CNT_EN

CNT
PSG

06

05

04

03

02

01

00

36

35

34

33

TIM_PSG

00

00

01

02

03

00

01

02

03

00

01

02

03

00

01

69 :
(CNT_MODE = 00, EVENT_SEL = 0000, DIR = 1)

202

19861, 19861, 19861, 19861QI, 198614

TIM_CLK
CNT_EN

CNT

04

03

PSG

02

01

00

01

02

03

04

05

06

05

04

03

02

01

00

01

02

03

04

DIR

70 : /
(CNT_MODE = 01, EVENT_SEL = 0000, DIR = 1)
(CNT==ARR )
,
.
,
-
.
,
, /.
,
. .
.

71

203

19861, 19861, 19861, 19861QI, 198614

TIM_CLK
CNT_EN

CNT1

00

CNT2

00

CNT3

00

00

01

02

03

04

00

01

00

02

01

00

03

04

00

04

02

04

00

00

01

02

00

01

03

04

00

01

01

04

00

04

00

01

01

02

03

02

72
DIR_1, DIR_2, DIR_3 = 0;
EVENT_SEL_1 = 0000, EVENT_SEL_2 = 0001, EVENT_SEL_3 = 0010;
CNT_MODE_1, CNT_MODE_2, CNT_MODE_3 = 00;
1. TxCHO
, EVENT_SEL = 01xx CNTRL.

( 71). ,
,
TIM_CLK,
1, 2, 4, 8 TIM_CLK, TIM_CLK
FDTS. CNTRL FDTS.

TIM_CLK
FDTS = 00
FDTS = 01
FDTS = 10
FDTS = 11

73 (FDTS)

204

19861, 19861, 19861, 19861QI, 198614


TIMx_CH1_CNTRL
CHFLTR[3:0]

RE

CH1

CHSEL[1:0]

FE
RE CH2

Fdts

TIM_CLK

T1CHO

T2CHO

T3CHO

RE CH3

T4CHO

Event

ETR

EVENT_SEL
TIMx_CNTRL

74

TIM_CLK
CNT_EN
CH1i
CNT

03

CNT
CNT
CNT

04

03

03

05

04

06

05

04

03

07

06

08

07

05

04

09

08

0A

09

0A

CHSEL = 01
CHFLTR = 0000

CHSEL = 00
CHFLTR = 0001

06

05

CHSEL = 00
CHFLTR = 0000

06

CHSEL = 01
CHFLTR = 0001

75

205

19861, 19861, 19861, 19861QI, 198614

TIM_CLK
CNT_EN
CH1i
CNT

03

CNT
CNT

CHSEL = 00
CHFLTR = 0000

04

03

CHSEL = 00
CHFLTR = 0001

04

03

CHSEL = 00
CHFLTR = 0010

04

CNT

03
N=1

CHSEL = 00
CHFLTR = 0011

04
N=2

N=4

N=8

F sampl = TIM_CLK

76
2. ETR
, EVENT_SEL = 1000 CNTRL.
BRKETR_CNTRL 2, 4 8 (ETRPSC)
, .

T1CHO

T2CHO

T3CHO

Event
T4CHO

TIM_CLK

ETR

/1,/2,/3,/4

ETR_INV

ETRPSC[7:0]

ETR

ETR_FILTER[3:0]

TIMx_BRKETR_CNTRL

EVENT_SEL
TIMx_CNTRL

77 ETR

206

19861, 19861, 19861, 19861QI, 198614

TIM_CLK
CNT_EN
ETR
ETR/2
CNT

03

05

07

ETR = 01
ETRFILTER = 0000

09

78 ETR

22.4
( 79).
TIMx_CH1_CNTRL
CHFLTR[3:0]

CH1

CHSEL[1:0]

RE
FE

RE CH2

Fdts

T1CHO

RE CH3

Capture

CCR

TIMx_CH2_CNTRL
CHFLTR[3:0]

CH2

RE

TIMx_CH1CNTRL

TIMx_CH1_CNTRL2

FE

CHPSC[1:0]

CRRRLD

Fdts

TIMx_CH1_CNTRL2

CNT

CHSEL[1:0]

TIMx_CH3_CNTRL
CHFLTR[3:0]

CH3

RE

FE CH1

FE

FE CH2

T1CHOn

Capture

CCR1

Fdts
CCR1_EN
TIMx_CH1_CNTRL2
TIM_CLK

/1,/2,/3,/4

79 1

CHy_CNTRL 1 CAPnPWM.
Chxi .
Fdts, TIM_CLK.
FILTER.
.
MUX ,
,
. MUX
, ,
. Capture

207

19861, 19861, 19861, 19861QI, 198614


CCR, Capture1 CCR1 CCR CCR1
CNT.

TIM_CLK
CNT_EN

CNT

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

CH1
CCR

26

CCR1

2C

80
CCR
, CCR1
. IE
, DMA_RE
DMA.

208

19861, 19861, 19861, 19861QI, 198614

INV

22.5

CNT==CCR

REF
CH
OUTPUT
CONTROL

CCR

DEAD-TIME
Generator

nINV

ETDS

DTG[7:0]

Fdts

ETRO

DTGX[3:0]

nCH

BRKO

CNT>CCR

CHxoe

SELOE[3:0]

OUTPUT

SELO[3:0]

OCCE

OCM[2:0]

CNT

ETRen

BRKen

CHxo

nCHxo

nCHxoe

nSELOE[3:0]

nSELO[3:0]

OUTPUT

81

CHy_CNTRL 0 CAPnPWM.
CCR
CNT CCR, CCR1 CNT.
ChxO nCHxO.
DEAD TIME Generator
. : .
, , ..
,
ChxOE ( ) CHxNOE ( ) 1.
(, ), 0
. OE ,
, SELOE nSELOE,
, REF.

CNT

00

01

02

03

04

05

06

07

00

01

02

03

04

05

06

07

00

01

02

03

04

CNT_EN
REF,CCR=7
REF,CCR=4

82 , CCR1_EN=0

209

19861, 19861, 19861, 19861QI, 198614


ARR = 7,DIR = 0, CCR = 4
CNT

00

01

02

03

04

05

06

07

00

01

02

03

04

05

06

07

00

01

02

03

04

CNT_EN
REF, OCCM=001
REF,OCCM=010
REF, OCCM=011
REF, OCCM=110
REF, OCCM=111

83 , CCR1_EN=0
REF ETR
PCLK BRK.

CNT

00

01

02

03

04

05

06

07

00

01

02

03

04

05

06

07

00

01

02

03

04

05

06

07

00

01

02

03

04

CNT_EN
ETR
REF,ETREN=0,
OCCE = 1
REF,ETREN=1,
OCCE = 1

84 , CCR1_EN = 0

T1NO:

DTGdel = 0, DTGx = 0, DTG = 0

T2NO:

DTGdel = 1, DTGx = 1, DTG = 0

T3NO:

DTGdel = 2, DTGx = 2, DTG = 0

T4NO:

DTGdel = 3, DTGx = 3, DTG = 0

85 DTG
CCR1_EN = 1, CNT
CCR CCR1,
REF ( CHy_CNTRL OCCM)
.

210

19861, 19861, 19861, 19861QI, 198614

DIR = 0, CCR1_EN = 1, CCR=4, CCR1=B


CNT

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

00

01

02

03

04

CNT_EN
REF, OCCM = 001
REF, OCCM = 110
REF, OCCM = 011

86 , CCR1_EN = 1
CCR CCR1, RRRLD,
CCR1 CCR CNT = 0,
. WR_CMPL.

22.6

RST_CLK->PER_CLOCK = 0xFFFFFFFF;
RST_CLK->TIM_CLOCK = 0x07000000;
TIMERx->CNTRL = 0x00000000;
//
TIMERx->CNT = 0x00000000;//
TIMERx->PSG = 0x00000000;//
TIMERx->ARR = 0x0000000F;//
TIMERx->IE = 0x00000002;// CNT = ARR
TIMERx->CNTRL = 0x00000001;// TIM_CLK. .

CNT

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

00

01

CNT_EN
INT

87

RST_CLK->PER_CLOCK = 0xFFFFFFFF;//
RST_CLK->TIM_CLOCK = 0x07000000;//
TIMERx->CNTRL = 0x00000000;//
//
TIMERx->CNT = 0x00000000;//
TIMERx->PSG = 0x00000000;//
TIMERx->ARR = 0x000000FF;//

211

19861, 19861, 19861, 19861QI, 198614


TIMERx->IE = 0x00001E00;//
// CAP
//
TIMERx->Chy_CNTRL[0] = 0x00008000;
TIMERx->Chy_CNTRL[1] = 0x00008002;
TIMERx->Chy_CNTRL[2] = 0x00008001;
TIMERx->Chy_CNTRL[3] = 0x00008003;
//
TIMERx->Chy_CNTRL1[0]= 0x00000000;
TIMERx->Chy_CNTRL1[1]= 0x00000000;
TIMERx->Chy_CNTRL1[2]= 0x00000000;
TIMERx->Chy_CNTRL1[3]= 0x00000000;
TIMERx->CNTRL = 0x00000001;// TIM_CLK. .

TIM_CLK
CNT

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

CNT_EN
CH0i

CH1i

CH2i

CH3i
CCR1
CCR2
CCR3
CCR4

00

03

00

06

00

09

00

0C

INT

88

RST_CLK->PER_CLOCK = 0xFFFFFFFF;//
RST_CLK->TIM_CLOCK = 0x07000000;//
TIMERx->CNTRL = 0x00000000;//
//
TIMERx->CNT = 0x00000000;//
TIMERx->PSG = 0x00000000;//
TIMERx->ARR = 0x00000010;//
TIMERx->IE = 0x0000010;//

212

19861, 19861, 19861, 19861QI, 198614


// REF
//
TIMERx->Chy_CNTRL[0] = 0x00000200;
TIMERx->Chy_CNTRL[1] = 0x00000200;
TIMERx->Chy_CNTRL[2] = 0x00000400;
TIMERx->Chy_CNTRL[3] = 0x00000600;
//
TIMERx->Chy_CNTRL1[0]= 0x00000099;
TIMERx->Chy_CNTRL1[1]= 0x00000099;
TIMERx->Chy_CNTRL1[2]= 0x00000099;
TIMERx->Chy_CNTRL1[3]= 0x00000099;
// .
TIMERx->CNTRL = 0x00000001;// TIM_CLK.

TIM_CLK
CNT

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

CNT_EN
CCR1

00

03

CCR2

00

06

CCR3

00

09

CCR4

00

0F

CH0o
CH1o
CH2o
CH3o
INT

89

213

19861, 19861, 19861, 19861QI, 198614

22.7
253

0x4007_0000
0x4007_8000
0x4008_0000
0x4009_8000

0x00
004
0x08
0x0C
0x10
0x14
0x18
0x1
0x20
0x24
0x28
0x2
0x30
0x34
0x38
0x3
0x40
0x44
0x48
0x4
0x50
0x54
0x58
0x5C

Timer1
Timer2
Timer3
Timer4

Timer1
Timer2
Timer3
Timer4

CNT[31:0]
PSG[15:0]
ARR[31:0]
CNTRL[11:0]
CCR1[31:0]
CCR2[31:0]
CCR3[31:0]
CCR4[31:0]
CH1_CNTRL[15:0]
CH2_CNTRL[15:0]
CH3_CNTRL[15:0]
CH4_CNTRL[15:0]
CH1_CNTRL1[15:0]
CH2_CNTRL1[15:0]
CH3_CNTRL1[15:0]
CH4_CNTRL1[15:0]
CH1_DTG[15:0]
CH2_DTG[15:0]
CH3_DTG[15:0]
CH4_DTG[15:0]
BRKETR_CNTRL[15:0]
STATUS[15:0]
IE[15:0]
DMA_RE[15:0]





, 1
, 2
, 3
, 4
1
2
3
4
1 1
1 2
1 3
1 4
DTG 1
DTG 2
DTG 3
DTG 4
BRK ETR


DMA

2 1
2 2
2 3
2 4
, 1 1
, 1 2
, 1 3
, 1 4
DMA
1
DMA
2
DMA
3
DMA
4

0x60
0x64
0x68
0x6
0x70
0x74
0x78
0x7
0x80

CH1_CNTRL2[15:0]
CH2_CNTRL2[15:0]
CH3_CNTRL2[15:0]
CH4_CNTRL2[15:0]
CCR11[31:0]
CCR21[31:0]
CCR31[31:0]
CCR41[31:0]
DMA_RE1[15:0]

0x84

DMA_RE2[15:0]

0x88

DMA_RE3[15:0]

0x8

DMA_RE4[15:0]

214

19861, 19861, 19861, 19861QI, 198614

22.7.1 CNT
254 CNT

310
R/W
0
CNT[31:0]

255 CNT

310


CNT[31:0]

22.7.2 PSG
256 PSG

31..16
R/W
0
-

15..0
R/W
0
PSG[15:0]

257 PSG

31...16
150


PSG[15:0]



CLK = TIM_CLK/(PSG+1)

22.7.3 ARR
258 ARR

310
R/W
0
ARR[31:0]

259 ARR

310


ARR[31:0]

,


CNT = [0ARR]

215

19861, 19861, 19861, 19861QI, 198614

22.7.4 CNTRL
260 CNTRL

3112
R/W
0
-

118
R/W
0000
EVENT
SEL
[3:0]

76
R/W
00
CNT
MODE
[1:0]

54
R/W
00

3
R/W
0

2
R/W
0

1
R/W
0

0
R/W
0

FDTS
[1:0]

DIR

WR
CMPL

ARRB
EN

CNT
EN

261 CNTRL

3112
11...8


EVENT_SEL
[3:0]

7..6

CNT_MODE
[1:0]

5...4

FDTS[1:0]

DIR

WR_CMPL

ARRB_EN

CNT_EN

,
.


4b0000 0
4b0001 CNT == ARR 1
4b0010 CNT == ARR 2
4b0011 CNT == ARR 3
4b0100
4b0101
4b0110
4b0111
4b1000 ETR
4b1001 ETR
4b1010 CNT == ARR 4

2b00 DIR=0
c DIR=1
PSG = 0
2b01 / DIR
CNT = 0 CNT = ARR
2b1x DIR=0
c DIR=1
EVENT = 1
FDTS
2b00 TIM_CLK
2b01 TIM_CLK
2b10 TIM_CLK
2b11 TIM_CLK

0 , 0 ARR
1 , ARR 0
,
CNT, PSG ARR
1
0
ARR
0 ARR ARR
1 ARR CNT

0
1

216

19861, 19861, 19861, 19861QI, 198614

22.7.5 CCRy
262 / y CCRy

310
R/W
0
CCR[31:0]

263 CCRy

310


CCR[31:0]

,

CCR, c CNT
.
CNT,
,

22.7.6 CCRy1
264 / y CCRy1

310
R/W
0
CCR1[31:0]

265 CCRy1

310


CCR1[31:0]

,

CCR1, c CNT
.
CNT,
,

22.7.7 CHy_CNTRL
266 y Chy_CNTRL

3116
U
0

15
R/W
0
CAP
nPWM

14
R/W
0
WR
CMPL

13
R/W
0

12
R/W
0

ETREN

BRKEN

119
R/W
000
OCCM
[2:0]

8
R/W
0
OCCE

76
R/W
00
CHPSC
[1:0]

54
R/W
00
CHSEL
[1:0]

30
R/W
0000
CHFLTR
[3:0]

267 Chy_CNTRL

31...16
15


CAP
nPWM


1
0

217

19861, 19861, 19861, 19861QI, 198614


14

WR
CMPL

13

ETREN

12

BRKEN

119

OCCM[2:0]

OCCE

76

CHPSC[1:0]

54

CHSEL[1:0]

30

CHFLTR[3:0]

,
CCR
1
0
ETR
0
1
BRK
0
1
REF
CCR1_EN = 0:
000 0
001 1, CNT = CCR
010 0, CNT = CCR
011 REF, CNT =CCR
100 0
101 1
110 1, DIR= 0 ( ), CNT<CCR, 0
0, DIR= 1 ( ), CNT<CCR, 1
111 0, DIR= 0 ( ), CNT<CCR, 1
1, DIR= 1 ( ), CNT<CCR, 0
CCR1_EN = 1:
000 0;
001 1, CNT = CCR CNT = CCR1;
010 0, CNT = CCR CNT = CCR1;
011 REF, CNT =CCR CNT =CCR1;
100 0;
101 1;
110 1, DIR = 1 ( ), CCR1 < CNT < CCR, 0;
0, DIR= 0 ( ), CCR < CNT < CCR1, 1;
111 0, DIR = 1 ( ), CCR1 < CNT < CCR, 1;
1, DIR = 0 ( ), CCR< CNT< CCR1, 0;
ETR
0 ETR
1 ETR

00
01 /2
10 /4
11 /8

00
01
10
2
3
4
1
11
3
4
1
2
:
0000 1 TIM_CLK
0001 2 TIM_CLK
0010 4 TIM_CLK
0011 8 TIM_CLK
0100 6 FDTS/2
0101 8 FDTS/2
0110 6 FDTS/4

218

19861, 19861, 19861, 19861QI, 198614


0111 8 FDTS/4
1000 6 FDTS/8
1001 8 FDTS/8
1010 5 FDTS/16
1011 6 FDTS/16
1100 8 FDTS/16
1101 5 FDTS/32
1110 6 FDTS/32
1111 8 FDTS/32

22.7.8 CHy_CNTRL1
268 1 y Chy_CNTRL1

3113
R/W
0

12
R/W
0

1110
R/W
00

NINV

NSELO
[1:0]

98
R/W
00
NSELO
E
[1:0]

75
R/W
0

4
R/W
0

32
R/W
00

10
R/W
00

INV

SELO
[1:0]

SELOE
[1:0]

269 Chy_CNTRL1

31...13
12


NINV

11...10

NSELO[1:0]

98

NSELOE[1:0]

75
4

INV

32

SELO[1:0]

10

SELOE[1:0]

,
.


0
1

00 0,
01 1,

10 REF.
11 DTG.

00 OE 0,
01 OE 1,
10 OE REF, REF = 0 , REF = 1
.
11 OE DTG, CHn = 0 , CHn =
1


0
1

00 0,
01 1,

10 REF.
11 DTG.

00 OE 0,
01 OE 1,
10 OE REF, REF = 0 , REF = 1
.
11 OE DTG, CH = 0 , CH = 1

219

19861, 19861, 19861, 19861QI, 198614

22.7.9 CHy_CNTRL2
270 2 y Chy_CNTRL2

314
U
0

3
R/W
0

CRRRLD

2
R/W
0
CCR1_E
N

10
R/W
00
CHSEL
[1:0]

271 Chy_CNTRL2

31...4
3

2
10


CRRRLD

CCR1_EN

CHSEL1[1:0]

CCR CCR1
0
1 CNT = 0
CCR1
0 CCR1
1 CCR1
CAP1
00 Chi
01 Chi
10
2
3
4
1
11
3
4
1
2

22.7.10 CHy_DTG
272 CHy_DTG DTG

31..16
U
0
-

158
R/W
00000000
DTG[7:0]

75
U
000
-

4
R/W
0
EDTS

30
R/W
0000
DTGx [3:0]

273 CHy_DTG

31...16
158


DTGx[7:0]

75
4

EDTS

30

DTG
[3:0]


DTGdel = DTGx*(DTG+1).

DTG
0 TIM_CLK
1 FDTS

DTG

220

19861, 19861, 19861, 19861QI, 198614

22.7.11 BRKETR_CNTRL
274 BRKETR_CNTRL BRK ETR

318
U

74
R/W
0000
ETR
FILTER
[3:0]

32
R/W
00
ETR
PSC
[1:0]

1
R/W
0

0
R/W
0

ETR
INV

BRK
INV

275 BRKETR_CNTRL

31...8
74

32


ETR
FILTER[3:0]

ETRPSC[1:0]

ETR
INV

BRK
INV

ETR.
:
0000 1 TIM_CLK
0001 2 TIM_CLK
0010 4 TIM_CLK
0011 8 TIM_CLK
0100 6 FDTS/2
0101 8 FDTS/2
0110 6 FDTS/4
0111 8 FDTS/4
1000 6 FDTS/8
1001 8 FDTS/8
1010 5 FDTS/16
1011 6 FDTS/16
1100 8 FDTS/16
1101 5 FDTS/32
1110 6 FDTS/32
1111 8 FDTS/32

00
01 /2
10 /4
11 /8
ETR
0
1
BRK
0
1

221

19861, 19861, 19861, 19861QI, 198614

22.7.12 STATUS
276 STATUS

31...17
U
0
-

4
R/W
0
BRK
EVENT

1613
U
0
CCR
CAP1
EVENT
[3:0]
3
R/W
0
ETR
FE
EVENT

129
R/W
0
CCR
REF
EVENT
[3:0]
2
R/W
0
ETR
RE
EVENT

1
R/W
0
CNT
ARR
EVENT

85
R/W
0
CCR
CAP
EVENT
[3:0]
0
R/W
0
CNT
ZERO
EVENT

277 STATUS

3117
1613

129

85


CCR
CAP1
EVENT[3:0]

CAP1
0
1
0,
, .

CCR
REF
EVENT[3:0]

0
3
REF
0
1
0,
, .

CCR
CAP
EVENT[3:0]

0
3
CAP
0
1
0,
, .

BRK
EVENT

ETR
FE
EVENT

ETR
RE
EVENT

0
3
PCLK BRK,
0 BRK == 0
1 BRK == 1
0, 0 BRK
ETR
0
1
0,
, .
ETR
0
1
0,
, .

222

19861, 19861, 19861, 19861QI, 198614


1

CNT
ARR
EVENT

CNT
ZERO
EVENT

CNT ARR
0
1
0,
, .

CNT ARR ,
.
CNT
0
1
0,
, .

CNT , .

22.7.13 IE
278 IE

31...17
U
0
-

4
R/W
0
BRK
EVENT
IE

1613
R/W
0
CCR
CAP1
EVENT
IE
[3:0]
3
R/W
0
ETR
FE
EVENT
IE

129
R/W
0
CCR
REF
EVENT
IE
[3:0]
2
R/W
0
ETR
RE
EVENT
IE

1
R/W
0
CNT
ARR
EVENT
IE

85
R/W
0
CCR
CAP
EVENT
IE
[3:0]
0
R/W
0
CNT
ZERO
EVENT
IE

279 IE

3117
16...13

129

85


CCR
CAP1
EVENT
IE [3:0]


CAP1
0
1

CCR
REF
EVENT
IE[3:0]

0
3

REF
0
1

CCR
CAP
EVENT
IE [3:0]

0
3

CAP
0
1
0

223

19861, 19861, 19861, 19861QI, 198614

BRK
EVENT
IE

ETR
FE
EVENT
IE
ETR
RE
EVENT
IE
CNT
ARR
EVENT
IE
CNT
ZERO
EVENT
IE

3
PCLK
BRK,
0
1

ETR
0
1

ETR
0
1
CNT
ARR
0
1
CNT

0
1

22.7.14 DMA_RE
280 DMA_RE DMA

31...17
U
0
-

4
R/W
0
BRK
EVENT
RE

1613
R/W
0
CCR
CAP1
EVENT
RE
[3:0]
3
R/W
0
ETR
FE
EVENT
RE

129
R/W
0
CCR
REF
EVENT
RE
[3:0]
2
R/W
0
ETR
RE
EVENT
RE

1
R/W
0
CNT
ARR
EVENT
RE

85
R/W
0
CCR
CAP
EVENT
RE
[3:0]
0
R/W
0
CNT
ZERO
EVENT
RE

281 DMA_RE

31...17
1613


CCR
CAP1
EVENT
RE [3:0]

DMA
CAP1
0 DMA
1 DMA
0
3

224

19861, 19861, 19861, 19861QI, 198614


129

85

CCR
REF
EVENT
RE[3:0]

DMA
REF
0 DMA
1 DMA

CCR
CAP
EVENT
RE [3:0]

0
3
DMA
CAP
0 DMA
1 DMA

BRK
EVENT
RE

ETR
FE
EVENT
RE
ETR
RE
EVENT
RE
CNT
ARR
EVENT
RE
CNT
ZERO
EVENT
RE

0
3
PCLK
BRK,
0 DMA
1 DMA
DMA
ETR
0 DMA
1 DMA
DMA
ETR
0 DMA
1 DMA
DMA CNT
ARR
0 DMA
1 DMA
DMA CNT

0 DMA
1 DMA

225

19861, 19861, 19861, 19861QI, 198614

23

( 1)

12- .
8 D ,
.
500 .
:
8 ;
;
;
;

.
28 CLK.
CPU_CLK
ADC_CLK .
Cfg_REG_CLKS.
Cfg_REG_DIVCLK[3:0]. CLK
14 .

Vop

Temp

1.23V

tC

TS_EN

SEL_TS

TS_BUF_EN

ADCOP2

ADCOP1

SEL_VREF

TS_EN

TS_BUF_EN

30

31
7

ADC7

ADC
Control

ADC6

Analog
Matrix
ADC1

12

Ain

Result

Chanel
Select
REF

ADC1_REF-

18

ADC0_REF+

90

226

19861, 19861, 19861, 19861QI, 198614


Cfg_REG_ADON.

.
, , TS_EN 1.

. ADC1_OP .
, , D,
, - .

23.1
ADC1_CFG Cfg_REG_CHS[4:0]
.
( Cfg_M_REF = 0) ( Cfg_M_REF = 1),
ADC0_REF+ ADC1_REF-.
Cfg_REG_CHCH, Cfg_REG_RNGC, Cfg_REG_SAMPLE, TS_BUF_EN, SEL_VREF, SEL_TS
Cfg_Sync_Conver .
1 Cfg_REG_GO.
Flg_REG_EOCIF
ADC1_STATUS. ADC1_RESULT .
Flg_REG_EOCIF .
,
, ADC1_RESULT
, Flg_REG_EOCIF
Flg_REG_OVERWRITE. Flg_REG_OVERWRITE
ADC1_STATUS.

23.2

ADC1_CHSEL
.
( Cfg_M_REF = 0)
(Cfg_M_REF = 1), ADC0_REF+ ADC1_REF-.
Cfg_REG_RNGC, TS_BUF_EN, SEL_VREF, SEL_TS Cfg_Sync_Conver
, Cfg_REG_SAMPLE Cfg_REG_CHCH .
Delay_GO .
1 Cfg_REG_GO.
Flg_REG_EOCIF
ADC1_STATUS. ADC1_RESULT .
Flg_REG_EOCIF .
,
, ADC1_RESULT
, Flg_REG_EOCIF
Flg_REG_OVERWRITE. Flg_REG_OVERWRITE
ADC1_STATUS.

ADC1_CHSEL Cfg_REG_CHCH 1,
Cfg_REG_CHS[4:0] Cfg_REG_CHCH 0.

.

.

227

19861, 19861, 19861, 19861QI, 198614

23.3


ADC1_L_LEVEL ADC1_H_LEVEL. Cfg_REG_RNGC,

Flg_REG_AWOIFEN. .

23.4

.
, TS_EN 1.
,
. ADC1_OP .

Cfg_REG_CHS 30 . TS_BUF_EN
SEL_VREF. .
1 Cfg_REG_GO.
Flg_REG_EOCIF
ADC1_STATUS. ADC1_RESULT .
Flg_REG_EOCIF .
,
, ADC1_RESULT
, Flg_REG_EOCIF
Flg_REG_OVERWRITE. Flg_REG_OVERWRITE
ADC1_STATUS.

ADC1_CHSEL 30 Cfg_REG_CHCH
1, 30- Cfg_REG_CHS[4:0]
Cfg_REG_CHCH 0.
.
TS_BUF_EN SEL_VREF.

23.5

.
, TS_EN 1.
,
. ADC1_OP .

Cfg_REG_CHS 31 , TS_BUF_EN SEL_TS,
.
1 Cfg_REG_GO.
Flg_REG_EOCIF
ADC1_STATUS. ADC1_RESULT .
Flg_REG_EOCIF .
,
, ADC1_RESULT
, Flg_REG_EOCIF
Flg_REG_OVERWRITE. Flg_REG_OVERWRITE
ADC1_STATUS.

ADC1_CHSEL 31 Cfg_REG_CHCH 1,
31- Cfg_REG_CHS[4:0] Cfg_REG_CHCH

228

19861, 19861, 19861, 19861QI, 198614


0.
. TS_BUF_EN SEL_TS.

23.6
:
,
. ,
,
.
,
.
RAIN
:

RAIN < (TS/(fC ADC*CADC*ln(2N)))-RADC


:

TS
fC ADC
CADC
N
RADC

- ;
- ;
- (~15-20);
- ;
- (~500 ).

12 1/4 LSB,
N = 14. 10 1 LSB,
N=10. TS = DelayGo[2:0]
. DelayGo[2:0]
CPU_CLK, ADC_CLK
CPU_CLK .
282

000

1 x CPU_CLK

TS


4 x CLK + 1 x CPU_CLK

28 x CLK + 1 x CPU_CLK

001

2 x CPU_CLK

4 x CLK + 2 x CPU_CLK

28 x CLK + 2 x CPU_CLK

010

3 x CPU_CLK

4 x CLK + 3 x CPU_CLK

28 x CLK + 3 x CPU_CLK

011

4 x CPU_CLK

4 x CLK + 4 x CPU_CLK

28 x CLK + 4 x CPU_CLK

100

5 x CPU_CLK

4 x CLK + 5 x CPU_CLK

28 x CLK + 5 x CPU_CLK

101

6 x CPU_CLK

4 x CLK + 6 x CPU_CLK

28 x CLK + 6 x CPU_CLK

110

7 x CPU_CLK

4 x CLK + 7 x CPU_CLK

28 x CLK + 7 x CPU_CLK

111

8 x CPU_CLK

4 x CLK + 8 x CPU_CLK

28 x CLK + 8 x CPU_CLK

DelayGo[2:0]

, ,
,
EDLADC, EILADC EOFFADC.
ADC1_CFG
GO,
.

229

19861, 19861, 19861, 19861QI, 198614

23.7
283

0x4008_8000

0x00
0x04
0x08
0x10
0x18
0x20
0x28

ADC

ADC

ADC
ADC
ADC
ADC
ADC
ADC

ADC

ADC1_CFG
ADC2_CFG
ADC1_H_LEVEL
ADC1_L_LEVEL
ADC1_RESULT
ADC1_STATUS
ADC1_CHSEL

23.7.1 ADCx_CFG
284 ADC1_CFG

3128

3128
R/W
0

2725
U
0

Delay
ADC
[3:0]

Delay
Go
[2:0]

20
R/W
0

19
R/W
0

18
R/W
0

TR[3:0]

SEL
VREF

SEL
TS

TS_BU
F
EN

11
R/W
0

10
R/W
0

9
R/W
0

Cfg
M_REF

Cfg
REG
RNGC

Cfg
REG
CHCH


Delay
ADC
[3:0]

27.25

Delay
Go
[2:0]

2421

TR[3:0]

20

2421
R/W
0

SEL
VREF

84
R/W
0
Cfg
REG
CHS
[4:0]

3
R/W
0

17
R/W
0
TS_EN
/
ADC1
OP

2
R/W
0

16
R/W
0
Cfg
Sync
Conver

1
R/W
0

1512
R/W
0
Cfg
REG
DIVCL
K
[3:0]
0
R/W
0

Cfg
Cfg
Cfg
Cfg

REG
REG
REG
REG
285
SAMPLE
CLKS
GO
ADON

ADC1_CFG

,

ADC1
, .
0000 0 CLK
0001 1 CLK

1111 15 CLK

000 0 CLK
001 1 CLK

111 7 CLK

91

1,23
0
1

Cfg_REG_CHS = 30

230

19861, 19861, 19861, 19861QI, 198614


19

SEL
TS

18

TS
BUF
EN

17

TS
EN

17

ADC1
OP

16

Cfg
Sync
Conver
Cfg
REG
DIVCLK
[3:0]
Cfg
M_REF

1512

11

10

Cfg
REG
RNGC

Cfg
REG
CHCH

84

Cfg
REG
CHS
[4:0]

Cfg
REG
SAMPLE

Cfg
REG
CLKS
Cfg
REG
GO
Cfg
REG
ADON


0
1

Cfg_REG_CHS = 31
ADC1_CFG


0
1
TS_EN = 1. .
ADC1_CFG

0
1

1.
ADC2_CFG
1,23
0 ( )
1 ()


0000 CLK 0001 CLK/2 0010 CLK/4 0011 CLK/8

1111 CLK/32768

0 ( Audd Auss)
1 ( Uref+ Uref-)

1 ,

0

1 ( ,
)
0
,

00000 0
00001 1

11111 31
.
1 ,

0
CLK ADC
1 ACLK
0 PCLK

1 ,


1
0

231

19861, 19861, 19861, 19861QI, 198614

1,215
1,210

Vref,

1,205
1,200
1,195
1,190
1,185
1,180
1

TRIM

91

23.7.2 ADC1_H_LEVEL
286 ADCx_H_LEVEL

3112
U
0
-

110
R/W
0
REG
H
LEVEL [11:0]

287 ADCx_H_LEVEL

3112
110


REG
H
LEVEL [11:0]

23.7.3 ADC1_L_LEVEL
288 ADCx_L_LEVEL

3112
U
0
-

110
R/W
0
REG
L
LEVEL [11:0]

289 ADCx_L_LEVEL

3112
110


REG
L
LEVEL [11:0]

232

19861, 19861, 19861, 19861QI, 198614

23.7.4 ADC1_RESULT
290 ADCx_RESULT

31.21
U
0

2016
RO
0

1512
U
0

CHANNEL [11:0]

110
RO
0
RESULT
[11:0]

291 ADCx_RESULT

3121
2016
1512
110


CHANNEL [11:0]
RESULT
[11:0]

23.7.5 ADC1_STATUS
292 ADCx_STATUS

31...5
U
0

4
R/W
0

3
R/W
0

2
R/W
0

1
R/W
0

ECOIF
IE

AWOIFIE

Flg
REG
EOCIF

Flg
REG
AWOIFEN

0
R/W
0
Flg
REG
OVERWRIT
E

293 ADCx_STATUS

315
4


ECOIF_IE

AWOIF_IE

Flg
REG
EOCIF

Flg
REG
AWOIFEN

Flg
REG
OVERWRITE


Flg_REG_ECOIF
0
1

Flg_REG_AWOIFEN
0
1
,
.
ADCx_RESULT.
1
0
,

.
ADCx_RESULT
0
1
,
.
0
1 ,

233

19861, 19861, 19861, 19861QI, 198614

23.7.6 ADC1_CHSEL
294 ADCx_CHSEL

31..0
R/W
0
Sl_Ch_Ch_REF[31:0]

295 ADCx_CHSEL

310


Sl_Ch_Ch_REF[31:
0]

,


0
1

234

19861, 19861, 19861, 19861QI, 198614

24

( 2)

12- .
8 D ,
.
500 .
:
8 ;
;
;
;

.
28 CLK.
CPU_CLK
ADC_CLK .
Cfg_REG_CLKS.
Cfg_REG_DIVCLK[3:0]. CLK
14 .

Vop

Temp

1.23V

tC

TS_EN

SEL_TS

SEL_VREF_BUF

ADCOP2

ADCOP1

SEL_VREF

TS_EN

TS_BUF_EN

30

31
7

ADC7

ADC
Control

ADC6

Analog
Matrix
ADC1

12

Ain

Result

Chanel
Select
REF

ADC1_REF-

18

ADC0_REF+

92

235

19861, 19861, 19861, 19861QI, 198614


Cfg_REG_ADON.

.
, TS_EN 1.

. ADC1_OP .
, , D,
, - .

24.1
ADC1_CFG Cfg_REG_CHS[4:0]
.
( Cfg_M_REF = 0) (Cfg_M_REF = 1),
ADC0_REF+ ADC1_REF-.
Cfg_REG_CHCH, Cfg_REG_RNGC, Cfg_REG_SAMPLE, TS_BUF_EN, SEL_VREF, SEL_TS
Cfg_Sync_Conver .
1 Cfg_REG_GO.
Flg_REG_EOCIF
ADC1_STATUS. ADC1_RESULT .
Flg_REG_EOCIF .
,
, ADC1_RESULT
, Flg_REG_EOCIF
Flg_REG_OVERWRITE. Flg_REG_OVERWRITE
ADC1_STATUS.

24.2

ADC1_CHSEL ,
.
( Cfg_M_REF = 0)
(Cfg_M_REF = 1),
ADC0_REF+ ADC1_REF-. Cfg_REG_RNGC, TS_BUF_EN, SEL_VREF, SEL_TS
Cfg_Sync_Conver , Cfg_REG_SAMPLE Cfg_REG_CHCH
. Delay_GO
.
1 Cfg_REG_GO.
Flg_REG_EOCIF
ADC1_STATUS. ADC1_RESULT .
Flg_REG_EOCIF .
,
, ADC1_RESULT
, Flg_REG_EOCIF
Flg_REG_OVERWRITE. Flg_REG_OVERWRITE
ADC1_STATUS.

ADC1_CHSEL Cfg_REG_CHCH 1,
Cfg_REG_CHS[4:0] Cfg_REG_CHCH 0.

.

.

236

19861, 19861, 19861, 19861QI, 198614

24.3


ADC1_L_LEVEL ADC1_H_LEVEL. Cfg_REG_RNGC,

Flg_REG_AWOIFEN. .

24.4

.
, TS_EN 1.
,
. ADC1_OP .

Cfg_REG_CHS 30 , SEL_VREF_BUF
SEL_VREF, .
1 Cfg_REG_GO.
Flg_REG_EOCIF
ADC1_STATUS. ADC1_RESULT .
Flg_REG_EOCIF .
,
, ADC1_RESULT
, Flg_REG_EOCIF
Flg_REG_OVERWRITE. Flg_REG_OVERWRITE
ADC1_STATUS.

ADC1_CHSEL 30 Cfg_REG_CHCH
1, 30- Cfg_REG_CHS[4:0]
Cfg_REG_CHCH 0.
.
SEL_VREF_BUF SEL_VREF.

24.5

.
, TS_EN 1.
,
. ADC1_OP .

Cfg_REG_CHS 31 . TS_BUF_EN SEL_TS,
.
1 Cfg_REG_GO.
Flg_REG_EOCIF
ADC1_STATUS. ADC1_RESULT .
Flg_REG_EOCIF .
,
, ADC1_RESULT
, Flg_REG_EOCIF
Flg_REG_OVERWRITE. Flg_REG_OVERWRITE
ADC1_STATUS.

ADC1_CHSEL 31 Cfg_REG_CHCH 1,
31- Cfg_REG_CHS[4:0], Cfg_REG_CHCH

237

19861, 19861, 19861, 19861QI, 198614


0.
. TS_BUF_EN SEL_TS.

24.6
:
,
. ,
,
.
,
.
RAIN
:

RAIN < (TS/(fC ADC*CADC*ln(2N)))-RADC


:

TS
fC ADC
CADC
N
RADC

-
-
- (~15-20)
-
- (~500 )

12 1/4 LSB,
N = 14. 10 1 LSB,
N=10. TS = DelayGo[2:0]
. DelayGo[2:0]
CPU_CLK, ADC_CLK
CPU_CLK .
296

000

1 x CPU_CLK

001

2 x CPU_CLK

4 x CLK + 2 x CPU_CLK

28 x CLK + 2 x CPU_CLK

010

3 x CPU_CLK

4 x CLK + 3 x CPU_CLK

28 x CLK + 3 x CPU_CLK

011

4 x CPU_CLK

4 x CLK + 4 x CPU_CLK

28 x CLK + 4 x CPU_CLK

100

5 x CPU_CLK

4 x CLK + 5 x CPU_CLK

28 x CLK + 5 x CPU_CLK

101

6 x CPU_CLK

4 x CLK + 6 x CPU_CLK

28 x CLK + 6 x CPU_CLK

110

7 x CPU_CLK

4 x CLK + 7 x CPU_CLK

28 x CLK + 7 x CPU_CLK

111

8 x CPU_CLK

4 x CLK + 8 x CPU_CLK

28 x CLK + 8 x CPU_CLK

DelayGo[2:0]

TS

4 x CLK + 1 x CPU_CLK
28 x CLK + 1 x CPU_CLK

, ,
,
EDLADC, EILADC EOFFADC.
ADC1_CFG
GO,
.

238

19861, 19861, 19861, 19861QI, 198614

24.7
297

0x4008_8000

0x00
0x04
0x08
0x10
0x18
0x20
0x28
0x30

ADC

ADC

ADC
ADC
ADC
ADC
ADC
ADC

ADC

ADC1_CFG
ADC2_CFG
ADC1_H_LEVEL
ADC1_L_LEVEL
ADC1_RESULT
ADC1_STATUS
ADC1_CHSEL
ADC1_TRIM

24.7.1 ADCx_CFG
298 ADCx_CFG

3128
R/W
0

2725
U
0

2421
R/W
0

20
R/W
0

19
R/W
0

18
R/W
0

17
R/W
0

16
R/W
0

Delay
ADC
[3:0]

Delay
Go
[2:0]

TR[3:0]

SEL
VREF

SEL
TS

TS_BUF
EN

TS_EN
/
ADC1
OP

Cfg
Sync
Conver

11
R/W
0

10
R/W
0

9
R/W
0

Cfg
M_REF

Cfg
REG
RNGC

Cfg
REG
CHCH

84
R/W
0
Cfg
REG
CHS
[4:0]

1512
R/W
0
Cfg
REG
DIVCL
K
[3:0]

3
R/W
0

2
R/W
0

1
R/W
0

0
R/W
0

Cfg
REG
SAMPLE

Cfg
REG
CLKS

Cfg
REG
GO

Cfg
REG
ADON

299 ADCx_CFG

3128


Delay
ADC
[3:0]

2725

Delay
Go
[2:0]

2421
20

SEL
VREF

,

ADC1
, .
0000 0 CLK
0001 1 CLK

1111 15 CLK


000 0 CLK
001 1 CLK

111 7 CLK

1,23
0
1
Cfg_REG_CHS
= 30.

239

19861, 19861, 19861, 19861QI, 198614


19

SEL
TS

18

TS
BUF
EN

17

TS
EN

17

ADC1
OP

16

Cfg
Sync
Conver
Cfg
REG
DIVCLK
[3:0]

1512

11

Cfg
M_REF

10

Cfg
REG
RNGC

Cfg
REG
CHCH

84

Cfg
REG
CHS
[4:0]

Cfg
REG
SAMPLE

Cfg
REG
CLKS
Cfg
REG
GO
Cfg
REG
ADON


0
1
Cfg_REG_CHS
= 31.
ADC1_CFG.

0
1
TS_EN = 1. .
ADC1_CFG.

0
1

1 .
ADC2_CFG.
1,23
0 ()
1 ()


0000 CLK
0001 CLK/2
0010 CLK/4
0011 CLK/8

1111 CLK/32768

0 ( Audd Auss)
1 ( Uref+ Uref-)

1
,

0

1 ( ,
)
0
,

00000 0
00001 1

11111 31

1 ,

0
CLK ADC
1 ACLK
0 PCLK

1 ,


1
0

240

19861, 19861, 19861, 19861QI, 198614

24.7.2 ADC1_H_LEVEL
300 ADC1_H_LEVEL

110
R/W
0
REG
H
LEVEL [11:0]

3112
U
0
-

301 ADC1_H_LEVEL

3112
110


REG
H
LEVEL [11:0]

24.7.3 ADC1_L_LEVEL
302 ADC1_L_LEVEL

110
R/W
0
REG L
LEVEL [11:0]

3112
U
0
-

303 ADC1_L_LEVEL

3112
110


REG
L
LEVEL [11:0]

24.7.4 ADC1_RESULT
304 ADC1_RESULT

3121
U
0
-

2016
RO
0
CHANNEL [11:0]

1512
U
0
-

110
RO
0
RESULT [11:0]

305 ADC1_RESULT

3121
2016
1512
110


CHANNEL [11:0]
RESULT
[11:0]

241

19861, 19861, 19861, 19861QI, 198614

24.7.5 ADC1_STATUS
306 ADC1_STATUS

31...5
U
0

4
R/W
0

3
R/W
0

2
R/W
0

1
R/W
0

ECOIF
IE

AWOIFIE

Flg
REG
EOCIF

Flg
REG
AWOIFEN

0
R/W
0
Flg
REG
OVERWRIT
E

307 ADC1_STATUS

315
4


ECOIF_IE

AWOIF_IE

Flg
REG
EOCIF

Flg
REG
AWOIFEN

Flg
REG
OVERWRITE


Flg_REG_ECOIF
0
1

Flg_REG_AWOIFEN
0
1
, ,
.
ADCx_RESULT
1
0
,

.
ADCx_RESULT
0
1
,
.
0
1 ,

242

19861, 19861, 19861, 19861QI, 198614

24.7.6 ADC1_CHSEL
308 ADC1_CHSEL

310
R/W
0
Sl_Ch_Ch_REF[31:0]

309 ADC1_CHSEL

310


Sl_Ch_Ch_REF[31:0]

,


0
1

24.7.7 ADC1_TRIM
310 ADC1_TRIM

317
U
0
-

6
R/W
0
SEL_VREF_BUF

5
R/W
1

4
3
2
R/W
R/W
R/W
0
0
0
TS_TRIM[4:0]

1
R/W
0

0
R/W
0
-

311 ADC1_TRIM

317
6


SEL
VREF
BUF

51
0

TS_TRIM[4:0]
-

0
1
TS_EN = 1.
.

243

19861, 19861, 19861, 19861QI, 198614

25

.
Cfg_ON_DACx 1, D
, - .
DACx_DATA DACx_OUT
, .
(Cfg_M_REFx = 0) (Cfg_M_REFx = 1) .
,
0 Aucc.
0
DACx_REF.

DAC1
12

Aout

DAC1

REF

REFD1

DAC
Control
DAC0
12

Aout

DAC0

REF

REFD0

93

244

19861, 19861, 19861, 19861QI, 198614

25.1
312

0x4009_0000

0x00
004
0x08

DAC

DAC

DAC_CFG
DAC0_DATA
DAC1_DATA

DAC
DAC0
DAC1

25.1.1 DAC_CFG
313 CFG

315
U
0

4
R/W
0
Cfg
SYNCA

3
R/W
0
Cfg
ON
DAC1

2
R/W
0
Cfg
ON
DAC0

1
R/W
0

0
R/W
0

Cfg
M_REF1

Cfg
M_REF0

314 CFG

Cfg_SYNC_A

Cfg_ON_DAC1

Cfg_ON_DAC0

Cfg_M_REF1

Cfg_M_REF0

DAC0 DAC1
0
1
DAC1
1
0
DAC0
1
0
DAC1
0
Aucc.
1
DACx_REF
DAC0,
Cfg_M_REF1

315

245

19861, 19861, 19861, 19861QI, 198614

25.1.2 DAC0_DATA
315 DAC0_DATA

3128
U
0
-

2716
R/W
0
DAC1_DATA[11:0]

1512
U
0
-

110
R/W
0
DAC0_DATA[11:0]

316 DAC0_DATA

3128
2716
1512
110

DAC1
DATA[11:0]
-

DAC1 Cfg_SYNC_A=1.
. DAC1_DATA

DAC0
DATA[11:0]

DAC0

25.1.3 DAC1_DATA
317 DAC1_DATA

3128
U
0
-

2716
R/W
0
DAC0_DATA[11:0]

1512
U
0
-

110
R/W
0
DAC1_DATA[11:0]

318 DAC1_DATA

3128
2716
1512
110

DAC0
DATA[11:0]
-

DAC0 Cfg_SYNC_A=1.
. DAC0_DATA

DAC1
DATA[11:0]

DAC1

Cfg_SYNC_A 1,
DAC0 DAC1 DACx_DATA.

246

19861, 19861, 19861, 19861QI, 198614

26

18977-79

8 4 1897779 ( ARINC). (
). 16 (32 3) 8 . ,
, /.
32-
, RZ. 32-
, . ,
.
FIFO . FIFO
3232 25632. FIFO
FIFO.
. 1 ,
/ ,
.

18977-79

18977-79

IN1+
IN1IN2+
IN2IN3+
IN3IN4+
IN4IN5+
IN5IN6+
IN6IN7+
IN7IN8+
IN8OUT1+
OUT1OUT2+
OUT2OUT3+
OUT3OUT4+
OUT4-

14853

14853

14853

14853

14852
14852
14852
14852

94 18977-79
:
/ 12,5 100 ;
168 (328 3)
/ ;
32 , , ;
/ ;
FIFO : 25632, 6432;
FIFO : 25632, 6432, 3232;

FIFO
.

247

19861, 19861, 19861, 19861QI, 198614

26.1
ARINC 32 , 5 :
, SSM, , /, .
, , .
ARINC :
8,7,6,5,4,3,2,1,9,10,11,12,1332.
32

31

30

29
11

SSM

DATA
MSB

10
SDI

1
LABEL

LSB

95
. ,
. , 32
. , 1-31
, , , 131 , .
31 30 .
FIFO
.
31 30 ,
( 319).
319 30, 31

31
0
0
1
1

30
0
1
0
1

, , , , ,


, , , , ,

10 9 / .
ARINC, ,
. ,
. .
, ARINC
20 . ,
, ,
FIFO.
1 8 ,
, , .
,

, FIFO. ,
, ,
.
,
FIFO.

248

19861, 19861, 19861, 19861QI, 198614

96
CLK = 1 ,
0,1 %.
10 ,
(Ones), (Zeros) (Null),
. , One Zero
Null
. ,
Null
Null.
.
8 12 .
.
Null
10 ( 80 12,5 )
. Null , .
.
, .
, .
32
(EOS). LB_EN, SD_EN, SDI1, SDI2
FIFO.
9 10 ,
FIFO. , ,
FIFO .

249

19861, 19861, 19861, 19861QI, 198614

320 FIFO
LB_EN

0
1
1
0
0
1
1
1
1


ARINC c

X
X

SD_EN

0
0
0
1
1
1
1
1
1

9,10
ARINC
SDI1, SDI2

FIFO

FIFO, DR,
. ,
FIFO, .
, FIFO, HF , FIFO
FF , FIFO .
. ,
.

250

19861, 19861, 19861, 19861QI, 198614

26.2
TX_R , , FIFO ,
31 32 .
FIFO . TX_R
, FIFO
. FIFO , FFx , FIFO
. FIFO ,
HFx, FIFO.
32-
. ODD .
(EN_PAR) , 32- ,
FIFO.
CH_EN FIFO ,
FIFO , FIFO
CH_EN.

97

251

19861, 19861, 19861, 19861QI, 198614

26.3 18977-79
321 18977-79

0x400D_0000

ARINC429R


ARINC-429

0x0000
0x0004
0x0008
0x000
0x0010
00014

CONTROL1
CONTROL2
CONTROL3
STATUS1
STATUS2
CONTROL4

00018

CONTROL5

0x001
0x0020
00024
0x0030

CHANNEL
LABEL
DATA_R
DATA_R1

0x0034

DATA_R2

0x0038

DATA_R3

0x003

DATA_R4

0x0040

DATA_R5

0x0044

DATA_R6

0x0048

DATA_R7

0x004

DATA_R8

00068

INTMASK

0x0070
0x0074

CONTROL8
CONTROL9

1
2
3
1
2

1-4 2

5-8 2

FIFO
FIFO
FIFO 1 CHANNEL=14 (
3)
FIFO 2 CHANNEL=14 (
3)
FIFO 3 CHANNEL=14 (
3)
FIFO 4 CHANNEL=14 (
3)
FIFO 5 CHANNEL=14 (
3)
FIFO 6 CHANNEL=14 (
3)
FIFO 7 CHANNEL=14 (
3)
FIFO 8 CHANNEL=14 (
3)

FIFO
8 ( 4)
9 ( 4)

0x400E_0000

ARINC429T


ARINC-429

0x0000
0x0004
0x0008
0x000
0x0010
0x0014
00018
0001

CONTROL1
CONTROL2
STATUS
DATA1_T
DATA2_T
DATA3_T
DATA4_T
CONTROL3

00020

CONTROL4

1
2

1
2
3
4

2
4 ( 4)

252

19861, 19861, 19861, 19861QI, 198614

26.3.1 CONTROL1
322 1 CONTROL1

31
R/W
0
DIV3
21
R/W
0
CLK8

30
R/W
0
DIV2
20
R/W
0
CLK7

7
R/W
0
CH_EN
8

6
R/W
0
CH_EN
7

19
R/W
0
CLK6

29
R/W
0
DIV1
18
R/W
0
CLK5

5
R/W
0
CH_EN
6

17
R/W
0
CLK4

4
R/W
0
CH_EN
5

28
R/W
0
DIV0
16
R/W
0
CLK3
3
R/W
0
CH_EN
4

15
R/W
0
CLK2
2
R/W
0
CH_EN
3

2722
U
14
R/W
0
CLK1
1
R/W
0
CH_EN
2

13..8
U
0
R/W
0
CH_EN
1

323 CONTROL1

3128


DIV[3:0]

2722
2114

CLK8-CLK1

138
70

CH_EN8-CH_EN1

,

1
4 ,
, 1 .
125 .


= /80
(12,5 DIV 0)
= /10
(100 DIV 0)

CONTROL4 CONTROL5, DIV=0 2


1
0

253

19861, 19861, 19861, 19861QI, 198614

26.3.2 CONTROL2
324 2 CONTROL2

31
R/W
0
DA
20
R/W
0
SD_EN
4
7
R/W
0
LB_EN5

3025
U
0
19
R/W
0
SD_EN
3

24
R/W
0
SD_EN8

18
R/W
0
SD_EN
2

6
R/W
0
LB_EN4

17
R/W
0
SD_EN
1

5
R/W
0
LB_EN3

23
R/W
0
SD_EN7
1611
U
0
-

4
R/W
0
LB_EN2

22
R/W
0
SD_EN6
10
R/W
0
LB_EN
8

3
R/W
0
LB_EN1

21
R/W
0
SD_EN5

9
R/W
0
LB_EN
7
2
R/W
0
DIV6

1
R/W
0
DIV5

8
R/W
0
LB_EN
6
0
R/W
0
DIV4

325 CONTROL2

31

30...25
24...17

16...11
10...3

2...0


DA

SD_EN8
SD_EN1

LB_EN8
LB_EN1

DIV[6:4]

,

FIFO1 FIFO2 ( 3)
1 1 2 FIFO
( FIFO: DRx, HFx, FFx
),

0x400D1000 0x400D13FC FIFO1
0x400D1400 0x400D14FC FIFO2
0 FIFO
, 32
.
CHANEL= 0 1


.

9 10
1 9 10
SDI1 SDI2
0 ,
FIFO


1 8
0 ,
FIFO
1
3 ,
, 1

254

19861, 19861, 19861, 19861QI, 198614

26.3.3 CONTROL3
326 3 CONTROL3

31
R/W

30
R/W
0
INTEFF

INTEHF

20
R/W
0
SDI2_7
7
R/W
0
SDI1_8

19
R/W
0
SDI2_6
6
R/W
0
SDI1_7

18
R/W
0
SDI2_5
5
R/W
0
SDI1_6

29
R/W
0
INTEER

28
R/W
0
INTEDR

2722
U
0
-

21
R/W
0
SDI2_8

17
R/W
0
SDI2_4

16
R/W
0
SDI2_3

15
R/W
0
SDI2_2

14
R/W
0
SDI2_1

138
U
0
-

4
R/W
0
SDI1_5

3
R/W
0
SDI1_4

2
R/W
0
SDI1_3

1
R/W
0
SDI1_2

0
R/W
0
SDI1_1

327 CONTROL3

31


INTEHF

30

INTEFF

29

INTEER

28

INTEDR

27...22
21...14

SDI2_1
SDI2_8

13...8
7...0

SDI1_1
SDI1_8

,

FIFO
1 , FIFO
0
FIFO
1 FIFO
0

1
4T
(
CH_EN)
0
FIFO
1 , FIFO

SDI2
10
, SD_EN

SDI1
9 ,
SD_EN

255

19861, 19861, 19861, 19861QI, 198614

26.3.4 CONTROL4 ( 2)
328 4 CONTROL4

3124
R/W
0
DIV_CH4

2316
R/W
0
DIV_CH3

158
R/W
0
DIV_CH2

70
R/W
0
DIV_CH1

329 CONTROL4

31...24


DIV_CH4

23...16

DIV_CH3

15...8

DIV_CH2

7...0

DIV_CH1

,


4

3

2

1

26.3.5 CONTROL5 ( 2)
330 5 CONTROL5

3124
R/W
0
DIV_CH8

2316
R/W
0
DIV_CH7

158
R/W
0
DIV_CH6

70
R/W
0
DIV_CH5

331 CONTROL5

31...24


DIV_CH8

2316

DIV_CH7

158

DIV_CH6

7...0

DIV_CH5

,


8

7

6

5

256

19861, 19861, 19861, 19861QI, 198614

26.3.6 CONTROL8 ( 4)
332 8 CONTROL8

3130
R/W
0
-

29
R/W
0
DA1

28
R/W
0
DA0

2714
R/W
1
ODD

130
R/W
1
ENPAR

333 CONTROL8

31...30
29


DA1

28

DA0

27..14

ODD

13...0

ENPAR

FIFO2
( DA = 0 CONTROL2)
1 2 FIFO (
FIFO: DR2, HF2, FF2
),

0x400D1400 0x400D14FC
0 FIFO
, 32
.
CHANEL= 1 14


.
FIFO1
( DA=0 CONTROL2)
1 1 FIFO (
FIFO: DR1, HF1, FF1
),

0x400D1000 0x400D13FC
0 FIFO
, 32
.
CHANEL= 0 14


.
18
1
( 2 ,
1, 0)
0
( 2
, 1,
0)
32 1-8
1 32-
0 32-

257

19861, 19861, 19861, 19861QI, 198614

26.3.7 CONTROL9 ( 4)
334 9 CONTROL9

3124
R/W
0
-

2316
R/W
0
-

158
R/W
0
-

70
R/W
0
ENSYNC

335 CONTROL9

31...8
7...0


ENSYNC[7:0]

1
0
ENSYNC
IN_A (D), IN_B
(SYN).

26.3.8 INTMASK ( 3)
336 INTMASK

31

30

29

28

27

26

25

24

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0
IEHF8

0
IEFF8

0
IEER8

0
IEDR8

0
IEHF7

0
IEFF7

0
IEER7

0
IEDR7

23

22

21

20

19

18

17

16

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0
IEHF6

0
IEFF6

0
IEER6

0
IEDR6

0
IEHF5

0
IEFF5

0
IEER5

0
IEDR5

15

14

13

12

11

10

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0
IEHF4

0
IEFF4

0
IEER4

0
IEDR4

0
IEHF3

0
IEFF3

0
IEER3

0
IEDR3

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0
IEHF2

0
IEFF2

0
IEER2

0
IEDR2

0
IEHF1

0
IEFF1

0
IEER1

0
IEDR1

258

19861, 19861, 19861, 19861QI, 198614


337 INTMASK

3128
2724
2320
1916
1512
118
75
30

,

8
7
6
5
4
3
2
1
IEDR1
1 , FIFO

0
IEER1
1
4T
(
CH_EN)
0
IEFF1
1 FIFO
0
IEHF1
1 , FIFO
0

26.3.9 STATUS1
338 1 STATUS1

3122
U
0
-

21
R/W
0
ERR8

15
R/W
0
ERR2

14
R/W
0
ERR1

7
R/W
0
DR8

6
R/W
0
DR7

20
R/W
0
ERR7

19
R/W
0
ERR6

18
R/W
0
ERR5

17
R/W
0
ERR4

16
R/W
0
ERR3

1
R/W
0
DR2

0
R/W
0
DR1

138
U
0
5
R/W
0
DR6

4
R/W
0
DR5

3
R/W
0
DR4

2
R/W
0
DR3

339 STATUS1

3122
2114


ERR8 ERR1

138
70

DR8 DR1


0
1

FIFO
0 FIFO
1 FIFO

259

19861, 19861, 19861, 19861QI, 198614

26.3.10 STATUS2
340 2 STATUS2

31.22
U

21
R/W
0
HF8

15
R/W
0
HF2

14
R/W
0
HF1

7
R/W
0
FF8

6
R/W
0
FF7

20
R/W
0
HF7

19
R/W
0
HF6

18
R/W
0
HF5

17
R/W
0
HF4

16
R/W
0
HF3

138
U
5
R/W
0
FF6

4
R/W
0
FF5

3
R/W
0
FF4

2
R/W
0
FF3

1
R/W
0
FF2

0
R/W
0
FF1

341 STATUS2

3122
2114


HF8 HF1

138
70

FF8 FF1

FIFO
0 FIFO
1 FIFO

FIFO
0 FIFO
1 FIFO

26.3.11 CHANNEL
342 CHANNEL

314
U
0
-

3
R/W
0
CHAN3

2
R/W
0
CHAN2

1
R/W
0
CHAN1

0
R/W
0
CHAN0

343 CHANNEL

314
30


CHAN[3:0]

.
,
.
0000 1
0001 2
0010 3
0011 4
0100 5
0101 6
0110 7
0111 8
1110 1 2 DA=1,
FIFO (
3)

260

19861, 19861, 19861, 19861QI, 198614

26.3.12 LABEL
FIFO , 8 ,
LB_EN . FIFO 16x8, 328
3. FIFO
CHANNEL. FIFO FIFO .
FIFO CHANNEL.

26.3.13 DATA_R
FIFO .
FIFO 32 ,
. FIFO :
1 25632;
2 25632;
3 6432;
4 6432;
5 6432;
6 6432;
7 3232;
8 3232.
FIFO
CHANNEL. FIFO DR, HF,
FF .

26.3.14 DATA_R1 DATA_R8 ( 3)


FIFO CHANNEL 14.

26.3.15 CONTROL1
344 1 CONTROL1

31...21
U
0
-

20
R/W
0
INTE_HFT2

15
R/W
0
INTE_FFT1

14
R/W
0
DIV6

19
R/W
0
INTE_TXR2
13
R/W
0
DIV5

12
R/W
0
DIV4

18
R/W
0
INTE_FFT2
11
R/W
0
DIV3

7
R/W
0

6
R/W
0

5
R/W
0

4
R/W
0

3
R/W
0

ODD2

EN_PAR2

CLK2

CH_EN2

ODD1

17
R/W
0
INTE_HFT1
10
R/W
0
DIV2
2
R/W
0
EN_PAR
1

16
R/W
0
INTE_TXR1
9
R/W
0
DIV1

8
R/W
0
DIV0

1
R/W
0

0
R/W
0

CLK1

CH_EN1

261

19861, 19861, 19861, 19861QI, 198614


345 CONTROL1

31.21
20


INTE_HFT2

19

INTE_TXR2

18

INTE_FFT2

17

INTE_HFT1

16

INTE_TXR1

15

INTE_FFT1

148

DIV[6:0]

ODD2

EN_PAR2

CLK2

CH_EN2

ODD1

EN_PAR1

CLK1

FIFO
2
1 , FIFO
0
FIFO 2
1 , FIFO
0
FIFO
2
1 FIFO
0
FIFO
1
1 FIFO
0
FIFO 1
1 FIFO
0
FIFO
1
1 FIFO
0
1
, ,
1

2
1 (
2 ,
1, 0)
0 (
2 ,
1, 0)
32 2
1 32-
0 32-
2 2
= /80
(12,5 DIV )
= /10
(100 DIV )
2
1
0

1
1 (
2 ,
1, 0)
0 (
2 ,
1, 0)
32 1
1 32-
0 32-
1 2
= /80

262

19861, 19861, 19861, 19861QI, 198614

(12,5 DIV )
= /10
(100 DIV )
1
1
0

CH_EN1

26.3.16 CONTROL2
346 2 CONTROL2

31...21
U
0
-

20
R/W
0
INTE_
HFT4

7
R/W
0
ODD4

19
R/W
0
INTE_
TXR4

6
R/W
0
EN_PAR4

18
R/W
0

17
R/W
0

INTE_FFT4

INTE_HFT3

5
R/W
0
CLK4

4
R/W
0
CH_EN4

3
R/W
0
ODD3

16
R/W
0
INTE_
TXR3

2
R/W
0
EN_PAR3

15
R/W
0

148
U

INTE_FFT3

1
R/W
0
CLK3

0
R/W
0
CH_EN3

347 CONTROL2

3121
20


INTE_HFT4

19

INTE_TXR4

18

INTE_FFT4

17

INTE_HFT3

16

INTE_TXR3

15

INTE_FFT3

148


FIFO 4
1 , FIFO
0
FIFO
4
1 , FIFO
0

FIFO 4
1 FIFO

0

FIFO 3
1 , FIFO
0
FIFO
3
1 , FIFO
0

FIFO 3
1 FIFO

263

19861, 19861, 19861, 19861QI, 198614


7

ODD4

EN_PAR4

CLK4

CH_EN4

ODD3

EN_PAR3

CLK3

CH_EN3


4
1
( 2 ,
1, 0)
0
( 2
, 1,
0)
32 4
1 32-
0 32-
4 2
= /80
(12,5 DIV )
= /10
(100 DIV )
4
1
0

3
1
( 2 ,
1, 0)
0
( 2
, 1,
0).
32 3
1 32-
0 32-
3 2
= /80
(12,5 DIV )
= /10
(100 DIV )
3
1
0

264

19861, 19861, 19861, 19861QI, 198614

26.3.17 CONTROL3
348 3 CONTROL3

2316
R/W
0
DIV_CH3

3124
R/W
0
DIV_CH4

158
R/W
0
DIV_CH2

70
R/W
0
DIV_CH1

349 CONTROL3

3124


DIV_CH4

2316

DIV_CH3

158

DIV_CH2

70

DIV_CH1

,


4

3

2

1

26.3.18 CONTROL4 ( 4)
350 4 CONTROL4

3124
R/W
0
-

2316
R/W
0
-

154
R/W
0
-

30
R/W
0
ENSYNC

351 CONTROL4

314
70


ENSYNC[3:0]

1
0
ENSYNC
OUT_A (D), OUT_B
(SYN).

265

19861, 19861, 19861, 19861QI, 198614

26.3.19 STATUS
352 STATUS

3114
U
0
-

13
R/W
0
HFT4

12
R/W
0
FFT4

11
R/W
1
TX_R4

10
R/W
0
HFT3

9
R/W
0
FFT3

8
R/W
1
TX_R3

76
U
0
-

5
R/W
0
HFT2

4
R/W
0
FFT2

3
R/W
1
TX_R2

2
R/W
0
HFT1

1
R/W
0
FFT1

0
R/W
1
TX_R1

353 STATUS

3114
13


HFT4

12

FFT4

11

TX_R4

10

HFT3

FFT3

TX_R3

76
5

HFT2

FFT2

TX_R2

HFT1

FFT1

TX_R1

FIFO 4
1 FIFO
0 FIFO
FIFO 4
1 FIFO
0 FIFO
FIFO 4
1 FIFO
0 FIFO
FIFO 3
1 FIFO
0 FIFO
FIFO 3
1 FIFO
0 FIFO
FIFO 3
1 FIFO
0 FIFO

FIFO 2
1 FIFO
0 FIFO
FIFO 2
1 FIFO
0 FIFO
FIFO 2
1 FIFO
0 FIFO
FIFO 1
1 FIFO
0 FIFO
FIFO 1
1 FIFO
0 FIFO
FIFO 1
1 FIFO
0 FIFO

266

19861, 19861, 19861, 19861QI, 198614

26.3.20 DATA1_T
FIFO 1.
FIFO 25632 1.
FIFO TX_R1, HFT1, FFT1.

26.3.21 DATA2_T
FIFO 2.
FIFO 6432 2.
FIFO TX_R2, HFT2, FFT2.

26.3.22 DATA3_T
FIFO 3.
FIFO 6432 3.
FIFO TX_R3, HFT3, FFT3.

26.3.23 DATA4_T
FIFO 4.
FIFO 6432 4.
FIFO TX_R4, HFT4, FFT4.

267

19861, 19861, 19861, 19861QI, 198614

27

SSP

(SSP Synchronous Serial Port)




:
SPI Motorola;
SSI Texas Instruments;
Microwire National Semiconductor.
, SSP :
, FIFO
( 16- ),
;

FIFO ( 16-
).
:
FIFO ;
FIFO ;
FIFO .
:
SPI;
Microwire;
SSI.

27.1 SSP

, ;
;
(8 16 )
FIFO (First In First Out ,
);
: SPI, Microwire, SSI;
4 16 ;
FIFO ,
FIFO , ;
,
;
(DMA).

( 98).

268

19861, 19861, 19861, 19861QI, 198614


SSPTXINTR

PRESETn

PWDATAIn [15:0]

PSEL

PCLK

RxFRdData
[15:0]

PENABLE
PWRITE
PADDR [11:2]
PRDATA[15:0]
PRDATA[15:0]

PCLK

SSPTXINTR
TxFIFO
8 16

TxRdDataIn [15:0]

RxFIFO
8 16

SSPRXINTR
SSPRORINTR
SSPRTINTR

FIFO

SSPINTR

PCLK

PCLK

DATAIN

SSPRTRINTR
SSPRORINTR
SSPRXINTR

DATAOUT

nSSPOE
SSPTXD

SSPCLK

SSPCLK

SSPFSSOUT

PCLK
nSSPRST

SSPCLK

SSPCLKDIV

nSSPCTLOE
SSPCLKIN

SSPRXDMACLR
SSPTXDMACLR

SSPCLKOUT

SSPRXDMASREQ

SSPRXDMABREQ
SSPTXDMASREQ

SSPTXDMABREQ


FIFO

SSPFSSIN
RxWrData [15:0]

SSPRXD

98 SSP

269

19861, 19861, 19861, 19861QI, 198614

27.2
:
;
;
;
;
;
4 16 ;
.

27.3 SPI
SPI Motorola :
;
.

27.4 Microwire
Microwire National Semiconductor :


.

27.5 SSI
SSI Texas Instruments :
;
()
.

27.6 SSP
SSP
,
SPI Motorola, Microwire
National Semiconductor, SSI Texas Instruments.
:
, ,
;
, ,
;
,
;
FIFO
16
.
SSPTXD
SSPRXD.
SSP ,
SSPCLK (, SSPSCK
) ,
SSPCLK (, SSP

270

19861, 19861, 19861, 19861QI, 198614


). 2 ,
SSPCLK .
,
CR0 CR1.
:
SSPTXINTR
;
SSPRXINTR
;
SSPRORINTR
FIFO;
SSPRTINTR
FIFO.
, SSPINTR,
,
NVIC.
(DMA)
DMA.
SSPFSSOUT
( SSI, ),
( SPI Microwire,
).

27.6.1

SSPCLK ,
.
2 254 2
CPSR.
,
. , ,
(
).

, SSPCLK.
1
256 CR0.

27.6.2 FIFO
16 , 8 ,
FIFO ( , ).
, .

27.6.3 FIFO
16 , 8 ,
FIFO ( , ).
,
.

27.6.4

271

19861, 19861, 19861, 19861QI, 198614



SSPCLK . ,
SSPCLK.
FIFO
.
,
SSPCLK, SSPTXD .
,
SSPRXD, .
FIFO , .


SSPCLK.
, ,
FIFO, .

SSPTXD.
, ,
SSPRXD SSPCLK,
, FIFO ,
.

27.6.5
SSP
. ,
.
NVIC,
,
.

27.6.6

DMA.

DMA

27.6.7

.
,
(SPI Motorola, SSI Texas
Instruments, Microwave National Semiconductor),
CR0 CR1.
,

SSPCLK PSR.

27.6.8
SSE CR1.
FIFO

272

19861, 19861, 19861, 19861QI, 198614


16- ,
.

SSPTXD SSPRXD.

27.6.9

CPU_CLK SSPCLK. SSPCLK CPU_CLK.
,
SSPCLK
CPU_CLK ,
:
FSSPCLK <= FPCLK
SSPCLK
, .
SSPCLK, SSP_CLK.
SSPTXD SSPCLK,
.
SSPRXD SSPCLK ,
.
, SSPCLK 12 ,
SSPCLK.
SSPCLK
.
SSPCLK SSPCLK
12, .

1,8432 / SSPCLK 3,6864 .
CPSR 2, SCR[7:0] CR0
0.

SSPCLK 22,12 .
CPSR 12, SCR[7:0] CR0
0.
SSPCLK
SSPCLKOUT 254 * 256.
SSPCLK
, :
FSSP_CLK (min) => 2 x FSSPCLKOUT (max) [for master mode]
FSSP_CLK (min) => 12 x FSSPCLKIN (max) [for slave mode].
, SSPCLK
, :
FSSP_CLK (max) <= 254 x 256 x FSSPCLKOUT (min) [for master mode]
FSSP_CLK (max) <= 254 x 256 x FSSPCLKIN (min) [for slave mode].

27.6.10 CR0
CR0 :
;

273

19861, 19861, 19861, 19861QI, 198614

;
.


SSPCLK .
SCR (Serial Clock Rate
) CR0 CPSDVSR (clock prescale divisor value
) CPSR.
FRF,
DSS CR0.
SPI Motorola (
SPH SPO).

27.6.11 CR1
CR1 :

;
;
.
0 MS CR1
( ).
1 MS .
SSPTXD
SOD (slave mode SSPTXD output disable
SSPTXD ) CR1.
.
,
1 SSE (Synchronous Serial Port Enable
).

27.6.12

SSP_CLK.
CPSDVSR, 2 254,
CPSR.
(1 + SCR) 1 256, SCR
CR0.
SSPCLK
:
FSSPCLK = FSSP_CLK / (CPSDVR * (1+SCR)).
, , SSP_CLK 3,6864 ,
CPSDVSR = 2, SSPCLK 7,2
1,8432 .

274

19861, 19861, 19861, 19861QI, 198614

27.6.13

4 16 .
. :
SSI Texas Instruments;
SPI Motorola;
Microwire National Semiconductor.
SSPCLK
, . SSPCLK
,
.
SPI Microwire
SSPFSS
.
SSI Texas Instruments
SSPFSS ,
. SSP,
,
SSPCLK, .
SSI SPI, Microwire
National Semiconductor
, .

.
-
. ,

,
.
4 16 ,
13 25 .

275

19861, 19861, 19861, 19861QI, 198614

27.6.14 SSI Texas Instruments

99 SSI ( )
SSP SSPCLK
SSPFSS , SSPTXD
.
FIFO
SSPFSSOUT ,
SSPCLK. FIFO
. SSPCLK
(4 16 )
SSPTXD ..
SSP,

SSPCLK. FIFO

SSPCLK.
SSI
Texas Instruments 99 (
) 100 ( ).

100 SSI ( )

27.6.15 SPI Motorola


SPI Motorola ,
SSPFSS .
SPI
SSPCLK ( )
SPO SPH CR0.
SPO
SPO 0, SSPCLK
. SSPCLK
.
SPH.

276

19861, 19861, 19861, 19861QI, 198614


SPH ,
.
SPH 0,
,
.

27.6.16 SPI Motorola, SPO=0, SPH=0


SPI
SPO=0, SPH=0 101 ( ) 102 (
).

101 SPI, SPO=0, SPH=0


( )
Q .

102 SPI, SPO=0, SPH=0


( )
:
SSPCLK ;
SSPFSS ;
SSPTXD .
FIFO
, SSPFSS ,

SSPRXD . SSPTXD
.
SSPCLK SSPTXD
.
, , .
SSPCLK .

SSPCLK.

277

19861, 19861, 19861, 19861QI, 198614



SSPFSS
SSPCLK.
SSPFSS
.
, SPH=0
.
SSPFSS ,
. SSPFSS
, ,
SSPCLK.

27.6.17 SPI Motorola, SPO=0, SPH=1


SPI
SPO=0, SPH=1 103 ( ).

103 SPI, SPO=0, SPH=1


Q .
:
SSPCLK ;
SSPFSS ;
SSPTXD .
FIFO
, SSPFSS ,

SSPRXD . SSPTXD
.
SSPCLK , ,
.
SSPCLK .

SSPCLK.

SSPFSS
SSPCLK.
SSPFSS
,
, .

278

19861, 19861, 19861, 19861QI, 198614

27.6.18 SPI Motorola, SPO=1, SPH=0


SPI
SPO=1, SPH=0 104 ( ) 105 (
).

104 SPI, SPO=1, SPH=0


( )
Q .

105 SPI, SPO=1, SPH=0


( )
:
SSPCLK ;
SSPFSS ;
SSPTXD .
FIFO
, SSPFSS ,

SSPRXD . SSPTXD
.
SSPCLK, SSPTXD
.
, , .
SSPCLK .

SSPCLK.

SSPFSS
SSPCLK.
SSPFSS
.
, SPH=0
.
SSPFSS ,
. SSPFSS

279

19861, 19861, 19861, 19861QI, 198614


, ,
SSPCLK.

27.6.19 SPI Motorola, SPO=1, SPH=1


SPI
SPO=1, SPH=1 106 ( ).

106 SPI, SPO=1, SPH=1


Q .
:
SSPCLK ;
SSPFSS ;
SSPTXD .
FIFO
, SSPFSS ,

SSPRXD . SSPTXD
.
SSPCLK , ,
.
SSPCLK .

SSPCLK.

SSPFSS
SSPCLK.
SSPFSS

, .

280

19861, 19861, 19861, 19861QI, 198614

27.6.20 Microwire National Semiconductor


Microwire
107 ( ) 108 ( ).

107 Microwire ( )
Microwire
SPI,
, ,
.

.
- . ,
,
,
.
4 16 , ,
13 25 .
:
SSPCLK ;
SSPFSS ;
SSPTXD .

FIFO . SSPFSS
, ,
, SSPTXD. SSPFSS
. SSPRXD
.

SSPCLK.
,
SSP.
SSPRXD SSPCLK.
.

SSPFSS ,
,
FIFO .

SSPCLK
, SSPFSS .

281

19861, 19861, 19861, 19861QI, 198614


,
. SSPFSS
.
.

SSPCLK.

108 Microwire ( )
SSPFSS
SSPCLK Microwire
SSP, Microwire ,
SSPCLK SSPFSS
. , SSPCKL,
SSPFSS
SSPCLK.
109.
SSPCLK,
SSP, SSPFSS
SSPCLK, .
SSPCLK
.

109 Microwire,
SSPFSSIN

282

19861, 19861, 19861, 19861QI, 198614

27.6.21
110, 111, 112
PrimeCell SSP (PL022) ,
.
SSP
/.
.

110 SSP
110 SSP,
, .

SSPTXD.

SSPTXD SSPRXD .

283

19861, 19861, 19861, 19861QI, 198614

111 SSP ,
SPI
111 SSP,
, , SPI
Motorola.
Slave Select (SS).
,
SSPTXD. SSPRXD

MISO.

284

19861, 19861, 19861, 19861QI, 198614

112 , SPI,
SSP
112 , SPI
Motorola, SSP,
. Slave Select (SS)
.
MOSI .
SSPTXD
, SSPTXD
SSPRXD .

285

19861, 19861, 19861, 19861QI, 198614

27.7
SSP
. DMA DMACR.
DMA :
:
SSPRXDMASREQ ,
. ,
FIFO , , ;
SSPRXDMABREQ ,
. ,
FIFO ;
SSPRXDMACLR DMA, DMA
.
,
.
:
SSPTXDMASREQ ,
.
, FIFO , ,
;
SSPTXDMABREQ ,
. ,
FIFO ;
SSPTXDMACLR DMA, DMA
.
,
.

, . , ,
,
,
.
, .
, . , ,
19 . DMA
, .
SSP
.
DMA
DMACLR.

DMA .
DMA ,
DMA.
354
, DMABREQ.

286

19861, 19861, 19861, 19861QI, 198614


354
DMA

(
(
)
)

4
4
113
DMA, DMACLR.
PCLK.

113 DMA

287

19861, 19861, 19861, 19861QI, 198614

27.8
27.8.1

:
+0x028 +0x07C +0xFD0 +0xFDC
;
+0x080 +0x088
.

27.8.2 SSP
SSP ( 355).
355 SSP

0x4004_000
0
0x400A_000
0
0x400F_800
0

SSP1

0x000
0x004
0x008

CR0
CR1
DR

0x00
0x010

SS2
SSP3

RW
RW
RW

0x0000
0x0
0x----

16
4
16

SR
CPSR

RO
RW

0x03
0x00

3
8

0x014
0x018

IMSC
RIS

RW
RO

0x0
0x8

4
4

0x01C

MIS

RO

0x0

0x020
0x024

ICR
DMACR

WO
RW

0x0
0x0

4
2


SSP1

SSP2

SSP3

0
1
FIFO ()
FIFO ()

: RW ,
RO , WO .

288

19861, 19861, 19861, 19861QI, 198614


0 CR0
CR0 ,
SSP.
( 356).
356 CR0

158

SCR

SPH

SPO

54

FRF

30

DSS

.
SCR
.
:
SSP_CLK / (CPSDVR * (1 + SCR)),
CPSDVR 2 254
(. SSPCPSR), SCR 0 255.
SSPCLK (
SPI Motorola). . SPI
Motorola .
SSPCLK (
SPI Motorola). .
SPI Motorola .
.
00 SPI Motorola;
01 SSI Texas Instruments;
10 Microwire National Semiconductor;
11 .
.
0000 .
0001 .
0010 .
0011 4 .
0100 5 .
0101 6 .
0110 7 .
0111 8 .
1000 9 .
1001 10 .
1010 11 .
1011 12 .
1100 13 .
1101 14 .
1110 15 .
1111 16 .

289

19861, 19861, 19861, 19861QI, 198614


1 CR1
CR1 ,
SSP.
( 357).
357 CR1

154

SOD

MS

SSE

LBM

.
.
0.
.

(MS=1).
,
.
SOD ,
SSP
SSPTXD.

.
0 SSPTXD
.
1 SSPTXD
.
:
0 ( );
1 .
:
0 ;
1 .
:
0 ;
1
.

DR
DR 16
.
FIFO
. FIFO .
FIFO .
.
,
SSPTXD .
16 ,
DR .
.
.
Microwire National Semiconductor SSP
(
). . FIFO
, SSE
0.
, .
DR ( 358).
358 DR

290

19861, 19861, 19861, 19861QI, 198614

150

DATA

()
()

16 , DR
.
.

.

SR

FIFO SSP.
359 SR.
359 SR

155

BSY

RFF

RNE

TNF

TFE

.
.
.
:
0 SSP ;
1 SSP /
, FIFO .
FIFO :
0 ;
1 .
FIFO :
0 ;
1 .
FIFO :
0 ;
1 .
FIFO :
0 ;
1 .

CPSR
CPSR .
2 254.
.
CPSR , ,
.
CPSR ( 360).
360 CPSR

158

70

CPSDVSR

.
.
.
.
2
254.
.

IMSC

291

19861, 19861, 19861, 19861QI, 198614


.
. 1
, 0 .
.
IMSC ( 361).
361 IMSC

154

TXIM

RXIM

RTIM

RORIM

.
.
.

FIFO .
1 ;
0 .

FIFO .
1 ;
0 .
( FIFO

).
1 ,
0 .
.
1 ,
0 .

RIS

. , , .
RIS ( 362).
362 RIS

154

TXRIS

RXRIS

RTRIS

RORRIS

.
.
SSPTXINTR.
1 FIFO
;
0 FIFO
.
SSPRXINTR.
1 FIFO
;
0 FIFO
.
SSPRTINTR.
1 ;
0 .
SSPRORINTR.
1 ;
0
.

MIS

292

19861, 19861, 19861, 19861QI, 198614



. , , .
MIS ( 363).
363 MIS

154

TXMIS

RXMIS

RTMIS

RORMIS

.
.
SSPTXINTR.
1 FIFO
;
0 FIFO
.
SSPRXINTR.
1 FIFO
;
0 FIFO
.
SSPRTINTR.
1 ;
0 .
SSPRORINTR.
1 ;
0
.

ICR

1 .
0 .
ICR ( 364).
364 ICR

152

RTIC

.
.
SSPRTINTR.

RORIC

SSPRORINTR.

293

19861, 19861, 19861, 19861QI, 198614


DMACR
. .
DMACR ( 365).
365 DMACR

152

TXDMAE

RXDMAE

.
.
.
DMA .
1
FIFO ;
0
FIFO .
DMA .
1
FIFO ;
0
FIFO .

DMA

DMA

DMA

DMA

27.9
,
, ,
, .
:
SSPRXINTR FIFO .
SSPTXINTR FIFO .
SSPRORINTR FIFO .
SSPRTINTR .
SSPINTR SSPRXINTR, SSPTXINTR, SSPRTINTR
SSPRORINTR.

SSPx_IMSC. 1
, 0 .
,
,
, , .
SSPRXINTR SSPTXINTR
.
,
FIFO .

SSPx_RIS, SSPx_MIS.

294

19861, 19861, 19861, 19861QI, 198614

27.9.1 SSPRXINTR
FIFO ,
.

27.9.2 SSPTXINTR
FIFO ,
.

SSP.
. -,
, . -,

.

27.9.3 SSPRORINTR
FIFO ,

. ,
.

27.9.4 SSPRTINTR
, FIFO
, ,
32 . ,
.

,
SSPRXD. 1 RTIC
SSPx_ICR.

27.9.5 SSPINTR

SSPRXINTR, SSPTXINTR, SSPRTINTR
SSPRORINTR .
,
.

295

19861, 19861, 19861, 19861QI, 198614

28

UART

(UART Universal
Synchronous Asynchronous Receiver Transmitter)
.
(ENDEC Encoder/Decoder)
() SIR (SIR
Serial Infra Red) Infrared Data Association (IrDA).

28.1 UART
UART ,
,
(SIR).
(16x12) (16x8) FIFO
(First In First Out , ),
.
FIFO .
,
(1x16 65535x16).
,
3,6864 .

, ,
.
FIFO ,
FIFO , , ,
.
UART DMA-
.
.
.
( CTS, DCD, DSR, RTS, DTR RI)
3.
.

:
5, 6, 7 8 ;
(
, , , );
1 2 ;
0 UART_CLK/16 .
- IrDA SIR :

IrDA SIR;
115200 /
;
(3/16)
(1,41 2,23 );
UART_CLK
.

296

19861, 19861, 19861, 19861QI, 198614

28.2
:
;
;
;
;
FIFO (
16 , );
FIFO (1/8, 1/4, 1/2,
3/4 7/8);
(
1,8432 ) 1,42 2,12

( -);
.

28.3 UART 16C650

16C650 :
FIFO
1/8, 1/4, 1/2, 3/4 7/8;
FIFO
1/8, 1/4, 1/2, 3/4 7/8;

;
.
16C650 :
( 1 2
);
.

28.4
:
, ,
;
, ,
.
,
.
FIFO, 16
.
:
,

UART_CLK;
,
UART 16C650;
:
- UART 921600 /;

297

19861, 19861, 19861, 19861QI, 198614


-

IrDA 460800 /;
IrDA 115200 /.


LCR_H
(IBRD) (FBRD).
:
(
), ,
;
, ,
;
(DMA)
DMA.
, ,

FIFO.
, FIFO .
FIFO ,

.
: (Clear To
Send, CTS), (Data Carrier Detected, DCD),
(Data Set Ready, DSR) (Ring Indicator, RI),
: (Request to Send, RTS)
(Data Terminal Ready, DTR). ,
.

nUARTCTS nUARTRTS.

IrDA SIR ENDEC.
UARTTXD
UARTRXD, nSIROUT SIRIN.
UARTTXD
( ), ,
UARTRXD. SIR ENDEC
,
.
IrDA SIR,
10 .

298

19861, 19861, 19861, 19861QI, 198614

28.5 UART
[11:0]
nUARTRST

[7:0]

PCLK

168

FIFO

txd [7:0]

rxd [11:0]

1612

FIFO

PRESETn
PSEL
PENABLE
PWRITE
PADDR [11:2]

APB

UARTTXD

PRDATA[15:0]

nSIROUT

Baud 16
UARTRXD

PRDATA[15:0]

UARTCLK

UARTRXDMACLR
UARTTXDMACLR
UARTRXDMASREQ
UARTRXDMABREQ
UARTTXDMASREQ
UARTTXDMABREQ

FIFO

SIRIN

FIFO

UARTTXINTR
UARTRXINTR
UARTMSINTR
UARTRTINTR
nUARTDTR
nUARTRTS

FIFO
nUARTRI
nUARTCTS
nUARTDSR

nUARTDCD
FIFO
nUARTDTR
nUARTRTS

nUARTOut1
nUARTOut2

114 - (UART)

28.5.1
,
Baud16 IrLPBaud16.
Baud16

, UART_CLK
, 16 .
IrLPBaud16
,
.

28.5.2 FIFO
8 , 16 ,
FIFO ( , ). ,
APB, ,
. FIFO
,
.

299

19861, 19861, 19861, 19861QI, 198614

28.5.3 FIFO
12 , 16 ,
FIFO ( , ).

, APB. FIFO
,
.

28.5.4
,
, .
: , ,
, , , , ,
, .

28.5.5
,
,
. : ,
, .
.

28.5.6

. ,
.

,
, .

.
.
,

.
. .

28.5.7

DMA.

DMA

28.5.8
,
CPU_CLK UART_CLK.
.
.
,
CPU_CLK UART_CLK, .

300

19861, 19861, 19861, 19861QI, 198614

28.6 IrDA SIR


113.

115 IrDA

28.6.1
,
(NRZ).
IrDA SIR
(RZI),
.
.
IrDA , ,
3 Baud16, 3/16
, .
IrDA 3/16
, , 115200 /.

IrLPBaud16 1,8432 , ,
UART_CLK. IrLPBaud16
ILPR.
.
,
, .
, ,

() .
,
Baud16 Baud16
UART_CLK.
,
UART_CLK. IrDA SIR,
13 %. , UART_CLK
3,6834 , 115200 /,
9 %. , .

301

19861, 19861, 19861, 19861QI, 198614

28.6.2
, ,
,
UART. .
, .

.
UART
, SIRIN , :
3/16 Baud16 IrDA;
3/16 IrLPBaud16 IrDA
.

302

19861, 19861, 19861, 19861QI, 198614

28.7 UART
28.7.1

.
.

28.7.2
FUART_CLK
:
FUART_CLK(min) >= 16 * baud_rate_max;
FUART_CLK(max) <= 16 * 65535 * baud_rate_min.
, 110 460800
FUART_CLK 7,3728 115,34 .
FUART_CLK, ,
.
FCPU_CLK
FUART_CLK. FUART_CLK 5/3 FCPU_CLK.
FUART_CLK <= (5/3) * FCPU_CLK.
, UART
921600 , FUART_CLK = 14,7456 , FCPU_CLK
8.85276 . , UART
FIFO.

28.7.3
LCR.
30 , APB
:
LCR_H :
- ;
- ;
- ;
- ;
- ;
- ;

IBRD
;
FBRD
.

303

19861, 19861, 19861, 19861QI, 198614

28.7.4

22 , 16 , 6
.
,
UART_CLK 3,6864 .
16- IBRD.
FBRD.
:
= FUART_CLK / (16 * ) = IBRD + FBRD,

IBRD , FBRD .

116
, FBRD,
, 64 (
2n, n FBRD) :
M = integer(FBRD * 2n + 0.5),

integer , n = 6.
Baud16,
, UART_CLK
, 16 .

28.7.5
16- FIFO,
FIFO
.
FIFO .
,
, LCR_H.
FIFO .
FIFO BUSY .
. BUSY
, FIFO ,
( ) . BUSY
,
.
( ) ,
.
(
UARTRXD )
( ), ,
Baud16,
( )
( ) Baud16.

304

19861, 19861, 19861, 19861QI, 198614



SIR IrDA.
, UARTRXD
Baud16
.
.
,
.
16 Baud16 (
). (
) ( ).
, (
UARTRXD). ,
. ,
, FIFO ,
, .

28.7.6
, ,
[10:8] FIFO .
FIFO, 11 .
366 FIFO
.

28.7.7

. , FIFO
, ( ).

. ,
FIFO
.
.
366 FIFO-
FIFO
11
10
09
08
0700

28.7.8 FIFO
FIFO .
UART
.
, ,
.
FIFO ,
.
, FIFO , (
), ,
.

305

19861, 19861, 19861, 19861QI, 198614



( )
1 LBE CR.

28.7.9 IrDA SIR


,
, IrDA SIR. .

.
:
IrDA nSIROUT
3/16
.
.
,
.
, . ,
, SIRIN.
IrDA

IrLPBaud16 ( 1.63 1.8432
). SIR_LP
CR.
, :
,
;

.
IrDA SIR,
,
10 .
. ,

.
,
() .
IrLPBaud16 UART_CLK
, ILPR.
:
= FUART_CLK / IrLPBaud16,

IrLPBaud16 1,8432 .
, :
1,42 < IrLPBaud16 < 2,12 .

1 LBE
CR 1 SIRTEST
TCR.
, nSIROUT,
SIRIN.

306

19861, 19861, 19861, 19861QI, 198614



.

117

118 IrDA

307

19861, 19861, 19861, 19861QI, 198614

28.8

(DTE),
(DCE).
367 DTE DCE

nUARTCTS

nUARTDSR

nUARTDCD

nUARTRI

nUARTCTS

nUARTDTR

nUARTOut1

nUARTOut2

28.8.1

( )
nUARTRTS nUARTCTS.

.

119

RTS, nUARTRTS
, FIFO
.
CTS,
nUARTCTS .

308

19861, 19861, 19861, 19861QI, 198614



RTSEn CTSEn CR. 363
.
368

CTSEn

RTSEn

CTS RTS

CTS

RTS

RTS,
RTS CR
RTS.

28.8.2 RTS
RTS
FIFO .
RTS, nUARTRTS
, FIFO
.
nUARTRTS ( ), , ,
.
.
nUARTRTS
FIFO , ,
.
RTS ,
UART ,
FIFO, .

28.8.3 CTS
CTS
nUARTCTS
. ,
, ,
.
nUARTCTS
, .
CTS ,
UART
FIFO .

309

19861, 19861, 19861, 19861QI, 198614

28.9

.
DMA DMACR.
DMA :
:
UARTRXDMASREQ

UART. 12 .
, FIFO
.
UARTRXDMABREQ ,
. ,
FIFO .
FIFO IFLS.
UARTRXDMACLR

DMA,

.
,
.
:
UARTTXDMASREQ ,
. .
, FIFO ,
, .
UARTTXDMABREQ ,
. ,
FIFO .
FIFO IFLS.
UARTTXDMACLR DMA, DMA
. ,
.

, . , ,
,
, .

. ,
. , , 19
, FIFO .
DMA ,
.
UART
.
DMA
DMACLR.

DMA .
DMA ,
DMA TXDMAE RXDMAE DMA
DMACR.

310

19861, 19861, 19861, 19861QI, 198614


FIFO
, , DMA .
DMA UARTRXDMASREQ UARTTXDMASREQ.
FIFO . LCR_H.
FIFO ,
, ,
. 369
UARTRXDMABREQ
UARTTXDMABREQ .
369
DMA

1/8




(
( )
)
14
2
12
4
8
8

12

7/8

14

DMA DMACR DMAONERR,


DMA
UARTEINTR. DMA:
UARTRXDMASREQ UARTRXDMABREQ
() UARTEINTR. DMA, ,
UARTEINTR .
120
DMA, DMACLR.
CPU_CLK. ,
DMA DMA .

120 DMA

311

19861, 19861, 19861, 19861QI, 198614

28.10
11 .
,
, .
:
UARTRXINTR .
UARTTXINTR .
UARTRTINTR .
UARTMSINTR :
UARTRIINTR, nUARTRI;
UARTCTSINTR, nUARTCTS;
UARTDCDINTR, nUARTDCD;
UARTDSRINTR, nUARTDSR.
UARTEINTR :
UARTOEINTR, ;
UARTBEINTR, ;
UARTPEINTR, ;
UARTFEINTR, .
UARTINTR UARTRXINTR, UARTTXINTR,
UARTRTINTR, UARTMSINTR UARTEINTR.

IMSC. 1
, 0 .
, ,
,
, ,
.
UARTRXINTR UARTTXINTR
.
UARTRXINTR UARTTXINTR
FIFO
.
UARTEINTR
.
.

.

RIS, MIS.

28.10.1 UARTMSINTR

(nUARTCTS, nUARTDCD, nUARTDSR, nUARTRI).
1 (
, ) ICR.

312

19861, 19861, 19861, 19861QI, 198614

28.10.2 UARTRXINTR

:
FIFO
. .

, ,
;
FIFO ( ),
. .
,
.

28.10.3 UARTTXINTR

:
FIFO
.
.
,
, ;
FIFO ( ),
.
.
, .
FIFO
,
.
,
.
FIFO , .
FIFO.

28.10.4 UARTRTINTR
, FIFO
, ,
32 .
(
, FIFO ), 1
ICR.

313

19861, 19861, 19861, 19861QI, 198614

28.10.5 UARTEINTR

. :
;
;
;
.
,
RIS, MIS.

ICR. 7
10.

28.10.6 UARTINTR

UARTRXINTR, UARTTXINTR, UARTRTINTR,
UARTMSINTR UARTEINTR .
,
.

314

19861, 19861, 19861, 19861QI, 198614

28.11

:
.
.
. .

:
-
;
-
;
- ( )
0
.

370
:
- RW ;
- RO ;
- WO .

315

19861, 19861, 19861, 19861QI, 198614

28.12

.
370

0x40030000

UART1

0x40038000

UART2


UART1

UART2

0x000

DR

RW

0x---

0x004

RSR_ECR

RW

0x0

4/0

FR

RO

0b-10010---

12/8

0x008-0x014
0x018

0x01C
0x020

ILPR

RW

0x00

0x024

IBRD

RW

0x0000

16

0x028

FBRD

RW

0x00

0x02C

LCR_H

RW

0x00

0x030

CR

RW

0x0300

16

0x034

IFLS

RW

0x12

0x038

IMSC

RW

0x000

11


FIFO

0x03C

RIS

RO

0x00-

11

0x040

MIS

RO

0x00-

11

0x044

ICR

WO

11

0x048

DMACR

RW

0x00

0x080

TCR

RW

0x00

316

19861, 19861, 19861, 19861QI, 198614

28.12.1 DR
:
FIFO , ,
, FIFO .
,
( FIFO).
.
, (
) .
.
:
FIFO ,
(, , , ) 12-
.

( FIFO).

UART_DR .
RSR_ECR ( 371).
371 UARTDR

1512
11

OE

10

BE

PE

FE

70

DATA

. 1
, ,
. 0 ,
.
. 1
,

,
( ,
). FIFO
,
.
,

1
.
. 1 ,

EPS SPS
LCR_H.

FIFO

,
.
. 1 ,

( 1).
FIFO
, .
()
()


.
,
.

317

19861, 19861, 19861, 19861QI, 198614

28.12.2 / RSR_ECR
RSR.
,
, DR.
,
( , DR,
).
ECR , ,
, . , 0
.
372 RSR_ECR.
372 RSR_ECR

74

OE

BE

PE

FE

.

.
1 , ,
. 0
ECR.
, .

, FIFO.
. 1
,

, ,
( ,
).
0 ECR.
FIFO
, .


1
.
. 1
,
EPS SPS
LCR_H. 0
ECR. FIFO
,
.
. 1
,
(
1). 0
ECR.

FIFO

,
.

RSR ,
, DR.
, RSR
DR. ,
DR.

318

19861, 19861, 19861, 19861QI, 198614

28.12.3 FR
TXFF, RXFF BUSY 0,
TXFE RXFE 1. 373 .
373 FR

159

. .
.
nUARTRI

RI

TXFE

RXFF

TXFF

RXFE

BUSY

DCD

FIFO .
FEN
LCR_H.

FIFO
,

1,
. 1,
FIFO .

.
FIFO .
FEN
LCR_H. FIFO ,
1,
. 1,
FIFO .
FIFO .
FEN
LCR_H. FIFO ,
1, .
1,
FIFO .
FIFO .
FEN
LCR_H.

FIFO
,

1,
. 1,
FIFO .
UART . 1 ,
.
, ,
, .
, 1
FIFO ,
( ).
nUARTDCD.

DSR

nUARTDSR.

CTS

nUARTCTS.

319

19861, 19861, 19861, 19861QI, 198614

28.12.4
ILPR
, ,
UART_CLK,
IrLPBaud16. ( 374).
IrLPBaud16
: ILPDVSR = FUART_CLK / FIrLPBaud16,
FIrLPBaud16 1,8432 .
,
: 1,42 < FIrLPBaud16 < 2,12 , , ,
1,41 2,11 (
IrLPBaud16).
374 LPR

70

ILPDVSR

UART_CLK, IrLPBaud16.
0.
0
. IrLPBaud16
.

, IrDA
SIRIN
, IrLPBaud16.

28.12.5 IBRD
.
375 IBRD

150

BAUDDIV_INT


.
0.

320

19861, 19861, 19861, 19861QI, 198614

28.12.6 FBRD
.
376 BFRD

50

BAUDDIV_FRAC


.
0.

:
BAUDDIV = FUART_CLK / (16 * Baud_rate),
FUART_CLK UART, Baud_rate
( /).
BAUDDIV BAUDDIV_INT
BAUDDIV_FRAC, .
IBRD FBRD
.
1, 65535 (2^16
1). , IBRD, 0 ,
FBRD .
, IBRD 65535 (0xFFFF), FBRD
. .
.
.
230400 /,
FUART_CLK = 4 . :
= (4*10^6)/(16*230400) = 1,085.
, BRDI = 1, BRDF = 0,085.
, , BFRD,
m = integer((0.085*64)+0.5) = 5.
= 1+5/64 = 1.078.
= (4*10^6)/(16*1.078) = 231911 /.
= (231911-230400)/230400 * 100% = 0.656%.

BFRD = 1/64*100 % = 1,56 %.
m = 1, 64 .
375
FUART_CLK = 7,3728 .
, , FBRD
.

321

19861, 19861, 19861, 19861QI, 198614


377 FUART_CLK = 7,3728

0x0001

460800

0x0002

230400

0x0004

115200

0x0006

76800

0x0008

57600

0x000C

38400

0x0018

19200

0x0020

14400

0x0030

9600

0x00C0

2400

0x0180

1200

0x105D

110

378
FUART_CLK = 4 .
378 FUART_CLK = 4

231911

, %

0x05

230400

0x001
0x002

0x0B

115200

115101

0.086

0x003

0x10

76800

76923

0.160

0x006

0x21

38400

38369

0.081

0x011

0x17

14400

14401

0.007

0x068

0x0B

2400

2400

~0

0x8E0

0x2F

110

110

~0

0.656

322

19861, 19861, 19861, 19861QI, 198614

28.12.7 LCR_H
29 22 LCR.
LCR_H .
.
379 LCR_H

158
7

65

SPS

WLEN

FEN

STP2

EPS

PEN

BRK

. .
.
.
0 ;
1
EPS,
. ( EPS=0
1, EPS=1 0).
SPS ,
PEN
( 380).

:
0b11 8 , 0b10 7 , 0b01 6 , 0b00 5 .
FIFO
.
0 , 1 .
.
0 ;
1 .
.
/. 0

, 1 . EPS
, PEN
( 380).
. 0
, 1
( 380).
. 1,

UART_TXD
.

, ,
.

0.

LCR_H, IBRD FBRD 30 LCR, ,


LCR_H. , ,
, IBRD
/ FBRD LCR_H.
:
:
IBRD, FBRD, LCR_H;
FBRD, IBRD, LCR_H.

323

19861, 19861, 19861, 19861QI, 198614


(IBRD FBRD)
:
IBRD ( FBRD), LCR_H.
380
SPS, EPS, PEN LCR_H.
380

PEN

EPS

SPS

:
LCR_H, IBRD FBRD :
;
(
) .
FIFO :
BRK;

FIFO, .

28.12.8 CR
, 9 8
. 9 8 .
.
381 CR

15

CTSEn

14

RTSEn

13

Out2

CTS.
1 ,
nUARTCTS.
0 .
RTS.
1 ,

FIFO .
0 .

nUARTOut2. (DTE)

(RI).
1 .
0 .

324

19861, 19861, 19861, 19861QI, 198614


12

Out1

11

RTS

10

DTR

RXE

TXE

LBE

63
2

SIRLP


nUARTOut1. (DTE)

(DCD).
1 .
0 .

nUARTRTS.
1 .
0 .

nUARTDTR.
1 .
0 .
.
1 .

,
SIR, SIREN.

,
.
0 .
.
1 .

,
SIR, SIREN.

,
.
0 .

1 .
0 .
:
SIREN=1 TCR SIRTEST=1,
nSIROUT
SIRIN. SIRTEST 1
,
, SIR.
SIRTEST
0.
SIRTEST=0,
UART_TXDx
UART_RXDx.
SIR, UART,

.
0.
. . .

.
1
IrLPBaud16
.
,
.
0 3/16
.

325

19861, 19861, 19861, 19861QI, 198614


1

SIREN

UARTEN

IrDA
SIR:
1 .
nSIROUT SIRIN.
UART_TXDx .
UART_RXDx
.
UARTEN=0 .
0 . nSIROUT
, SIRIN .
.
0 .
/
.
1 .
,
SIR, SIREN.

,
1 TXE UARTEN. ,
1 RXE UARTEN.

:
.
/ .
FEN LCR_H 0.
CR.
.

28.12.9 FIFO IFLS



,
UARTTXINTR UARTRXINTR, .
.
,
. .
382 IFLS

156

. . .

53

RXIFLSEL

20

TXIFLSEL

:
b000 = 1/8
b001 = 1/4
b010 = 1/2
b011 = 3/4
b100 = 7/8
b101-b111 = .
:
b000 = 1/8
b001 = 1/4
b010 = 1/2
b011 = 3/4
b100 = 7/8
b101-b111 = .

326

19861, 19861, 19861, 19861QI, 198614

28.12.10

IMSC

.
.
.
IMSC .
383 IMSC

1511

. . .

10

OEIM

BEIM

PEIM

FEIM

RTIM

TXIM

RXIM

DSRMIM

DCDMIM

CTSMIM

RIMIM

UARTOEINTR. 1 ;
0 .
UARTBEINTR.
1 ;
0 .

UARTPEINTR.
1 ;
0 .

UARTFEINTR.
1 ;
0 .

UARTRTINTR.
1 ;
0 .
UARTTXINTR.
1 ;
0 .
UARTRXINTR.
1 ;
0 .
UARTDSRINTR
nUARTDSR.
1 ;
0 .
UARTDCDINTR
nUARTDCD.
1 ;
0 .
UARTCTSINTR
nUARTCTS.
1 ;
0 .
UARTRIINTR
nUARTRI.
1 ;
0 .

327

19861, 19861, 19861, 19861QI, 198614

28.12.11

RIS


. , , .
. ,
( 3 0), 0.
.
RIS .
384 RIS

. . .

1511
10

OERIS

BERIS

PERIS

FERIS

RTRIS

TXRIS

RXRIS

DSRRMIS

DCDRMIS

CTSRMIS

RIRMIS


UARTOEINTR.
1 ;
0 .
UARTBEINTR.
1 ;
0 .

UARTPEINTR.
1 ;
0 .

UARTFEINTR.
1 ;
0 .

UARTRTINTR1.
1 ;
0 .
UARTTXINTR.
1 ;
0 .
UARTRXINTR.
1 ;
0 .
UARTDSRINTR
nUARTDSR.
1 ;
0 .
UARTDCDINTR
nUARTDCD.
1 ;
0 .
UARTCTSINTR
nUARTCTS.
1 ;
0 .
UARTRIINTR
nUARTRI.
1 ;
0 .


.
MIS RIS .

328

19861, 19861, 19861, 19861QI, 198614

28.12.12

MIS


. , , .
,
( 3 0), 0.
.
MIS .
385 MIS

1511

. . .

10

OEMIS

BEMIS

PEMIS

FEMIS

RTMIS

TXMIS

RXMIS

DSRMMIS

DCDMMIS

CTSMMIS

RIMMIS

UARTOEINTR.
1 ;
0 .

UARTBEINTR.
1 ;
0 .

UARTPEINTR.
1 ;
0 .

UARTFEINTR.
1 ;
0 .

UARTRTINTR.
1 ;
0 .

UARTTXINTR.
1 ;
0 .

UARTRXINTR.
1 ;
0 .
UARTDSRINTR
nUARTDSR.
1 ;
0 .
UARTDCDINTR
nUARTDCD.
1 ;
0 .
UARTCTSINTR
nUARTCTS.
1 ;
0 .
UARTRIINTR
nUARTRI.
1 ;
0 .

329

19861, 19861, 19861, 19861QI, 198614

28.12.13

ICR


1 . 0
.
ICR .
386 ICR

1511

. . .

10

OEIC

BEIC

PEIC

FEIC

RTIC

TXIC

RXIC

DSRMIC

DCDMIC

CTSMIC

RIMIC

UARTOEINTR.
1 ;
0 .
UARTBEINTR.
1 ;
0 .

UARTPEINTR.
1 ;
0 .

UARTFEINTR.
1 ;
0 .

UARTRTINTR.
1 ;
0 .
UARTTXINTR.
1 ;
0 .
UARTRXINTR.
1 ;
0 .
UARTDSRINTR
nUARTDSR.
1 ;
0 .
UARTDCDINTR
nUARTDCD.
1 ;
0 .
UARTCTSINTR
nUARTCTS.
1 ;
0 .
UARTRIINTR
nUARTRI.
1 ;
0 .

330

19861, 19861, 19861, 19861QI, 198614

28.12.14

DMACR

. .
DMACR .
387 DMACR

1513
123

. . .

DMAONERR

TXDMAE

RXDMAE

DMA
.
1
DMA
UARTRXDMASREQ UARTRXDMABREQ.
0 DMA .
DMA .
1 DMA
FIFO .
0 DMA .
DMA .
1 DMA
FIFO ;
0 DMA .

28.12.15

TCR

. .
TCR .
388 TCR

1513
123

. .

SIRTEST

TESTFIFO

ITEN


IrDA .
1
0
LBE
CR
FIFO
FIFO .
1
0
UART
1
0

331

19861, 19861, 19861, 19861QI, 198614

29

DMA

29.1 DMA
:
32 DMA;
DMA ;
DMA ;
, ,
DMA;
:
- ;
- ;
- ;

DMA ;
;
DMA
;
;
;
DMA 1
1024;
.

29.2
389

.

(.
)
. :
=1 DMA 1
=23 DMA 23

32.

,
DMA

.
,
DMA .
,
.

DMA

DMA,
N

DMA

, .
DMA,

332

19861, 19861, 19861, 19861QI, 198614

,
DMA,
.
DMA DMA,
( )
. DMA,

.
,
,

.
,
chnl_pri_alt_set 0.

2, DMA,
. DMA
1 1024 2
0 2 100

,
4 DMA ,
,
.
DMA,
. ,
,
4 DMA ,

.
DMA,
.

,

. dma_done,

.

333

19861, 19861, 19861, 19861QI, 198614

29.3
.

121
:
, APB;
, AHB;
DMA.

334

19861, 19861, 19861, 19861QI, 198614

29.3.1 DMA
390 DMA

0
1
2
3
4
5
6
7
8
9
10

req

sreq

UART1_TX_DMA_BREQ
UART1_RX_DMA_BREQ
UART2_TX_DMA_BREQ
UART2_RX_DMA_BREQ
SSP1_TX_DMA_BREQ
SSP1_RX_DMA_BREQ
SSP2_TX_DMA_BREQ
SSP2_RX_DMA_BREQ
SSP3_TX_DMA_BREQ
SSP3_RX_DMA_BREQ
TIM1_DMA_REQ

UART1_TX_DMA_SREQ
UART1_RX_DMA_SREQ
UART2_TX_DMA_SREQ
UART2_RX_DMA_SREQ
SSP1_TX_DMA_SREQ
SSP1_RX_DMA_SREQ
SSP2_TX_DMA_SREQ
SSP2_RX_DMA_SREQ
SSP3_TX_DMA_SREQ
SSP3_RX_DMA_SREQ
TIM1_DMA_REQ

11

TIM2_DMA_REQ

TIM2_DMA_REQ

12

TIM3_DMA_REQ

TIM3_DMA_REQ

13

TIM4_DMA_REQ

TIM4_DMA_REQ

14

TIM1_DMA_REQ1

15

TIM1_DMA_REQ2

16

TIM1_DMA_REQ3

17

TIM1_DMA_REQ4

18

TIM2_DMA_REQ1

19

TIM2_DMA_REQ2

20

TIM2_DMA_REQ3

21

TIM2_DMA_REQ4

22

TIM3_DMA_REQ1

23

TIM3_DMA_REQ2

24

TIM3_DMA_REQ3

25

TIM3_DMA_REQ4

26

TIM4_DMA_REQ1

27

TIM4_DMA_REQ2

28

TIM4_DMA_REQ3

29

TIM4_DMA_REQ4

30

ADC_DMA_SREQ

31

UART1
UART1
UART2
UART2
SPI1
SPI1
SPI2
SPI2
SPI3
SPI3

TIMER1

TIMER2

TIMER3

TIMER4
1
TIMER1
2
TIMER1
3
TIMER1
4
TIMER1
1
TIMER2
2
TIMER2
3
TIMER2
4
TIMER2
1
TIMER3
2
TIMER3
3
TIMER3
4
TIMER3
1
TIMER4
2
TIMER4
3
TIMER4
4
TIMER4

335

19861, 19861, 19861, 19861QI, 198614

29.3.2 , APB
, ,
APB . 4 .

29.3.3 , AHB
DMA Bus, ,
32- , .
AHB.

29.3.4 DMA
,
:
;
;
;
DMA Bus;

DMA;
DMA;
DMA
;
DMA :
- ;
- ;
- .

29.3.5
.
.
,
AHB,
. DMA
AHB,
.

29.3.6
8, 16
32 . 374 HSIZE.
391 HSIZE
HSIZE[2]*
0
0
0

HSIZE[1]
0
0
1
1

HSIZE[0]
0
1
0
1

()
8
16
32
**

* - .
**-
32-
.
.

336

19861, 19861, 19861, 19861QI, 198614

29.3.7
AHB-Lite,
HPROT[3:1]. :
;
;
.
392 HPROT.
392
HPROT[3]

HPROT[2]

HPROT[0]
/

HPROT[1]

0
1

0
1
-

1*
-

HPROT[0] ,
.
DMA
. .
DMA .
DMA.

29.3.8

.
. .
393

8
16
32


, ,
,


. ,
, .
.
.

, , FIFO,
(.
).

337

19861, 19861, 19861, 19861QI, 198614

29.4 DMA
29.4.1
( 394),
:
DMA ,
chnl_enable_set[C] master_enable;
dma_req[C] dma_sreq[C] ,

chnl_req_mask_set [C];
,
int_test_en_bit[C].
394 , ,

2
3
4

5
6
7
8
9

10
11

dma_active[C] 0, 1 dma_req[C] dma_sreq[C]


HCLK,
,
1 dma_active[C]
1 dma_active[C]

DMA,
, dma_active[C] 1 ,
R
, 2 ,
n_minus_1.
,
dma_active[C] 1 DMA ,
.
R
, 2 ,
,
R
, 2 ( ,
n_minus_1), .
dma_active[C] 0
dma_active[C] 0
HCLK , dma_active[C] dma_active[] 1
, ,
1 dma_done[]
dma_req[C] 1 , dma_active[C]
dma_stall 1, ,
cycle_ctrl 3b100, 3b101, 3b110,
3b111, dma_done[C] 1
, cycle_ctrl
dma_done[C], dma_active[] :
dma_stall 0, dma_done[]
1 HCLK
dma_stall 1, . ,
dma_stall 0, dma_done[]
1 HCLK
dma_waitonreq[C]
dma_waitonreq[C] 1, dma_active[C]
0 , :
R
2 ( ,
n_minus_1);
dma_req[C] 0;
dma_sreq[C] 0

338

19861, 19861, 19861, 19861QI, 198614


12

13
14
15

16

17

18

HCLK dma_active[C] 0 dma_stall


1,
dma_active[C] 0 HCLK;
, 0 dma_stall
dma_sreq[C], dma_waitonreq[C] 0
*)
dma_sreq[C], chnl_useburst_set[C] 1
DMA,
R
, 2
chnl_useburst_set[C] 0,
R
, 2 .

chnl_useburst_set[C] 0 ,

R
, 2 .
DMA,
, HCLK dma_active[C]
1 dma_sreq[C] dma_waitonreq[C] 1 dma_req[C] 0,
DMA .
,
HCLK dma_active[C] 1 dma_sreq[C] dma_waitonreq[C]
R
1 dma_req[C] 0, 2
.
,

DMA,
, HCLK dma_active[C]
1, dma_sreq[C] dma_req[C] 1,
R
dma_req[c], 2 ( ,
n_minus_1) DMA .
,
HCLK dma_active[C] 1 dma_sreq[C] dma_req[C]
R
1, dma_req[c], 2
,
,
R
2 ( , n_minus_1),

chnl_req_mask_set[C] 1,
dma_sreq[C] dma_req[C]

*)

. ,
n_minus_1 , 2R,
chnl_useburst_set dma_sreq[C] .
dma_req[C] 1,
.
DMA ,
.
395 DMA

19

20

21

dma_req[C] 1, dma_done[C] 1.
,
()
dma_sreq[C] 1, dma_done[C] 1
dma_waitonreq[C] 1 chnl_useburst_set[C] 0.
,
()
dma_active[C] 0

339

19861, 19861, 19861, 19861QI, 198614

29.4.2 DMA

( 394):
;
;
;
.
, 122 125,
:

122 DMA
.

122

396
1
4
4-7

7-9
9-10
10
10-11
11

(. 1) ,
chnl_req_mask_set[C] 0 (. 18) .
dma_active[C] (. 2 3) DMA
.
, :
rc , channel_cfg;
rsp , src_data_end_ptr;
rdp , dst_data_end_ptr.
dma_active[C] 1 , chnl_req_mask_set[C]
0,
(. 7).

DMA , :
RD ;
WD
, channel_cfg,
wc , channel_cfg.
dma_active[C],
DMA (. 4).
dma_active[C] 0 HCLK (.
5).
,
dma_active[C], 7 (.
2 3).

340

19861, 19861, 19861, 19861QI, 198614


12

14
17
17-18
18

dma_active[C] 1 , chnl_req_mask_set[C]
0,
(. 7).
.
- ,
12.
dma_active[C],
DMA (. 4).
dma_active[C] HCLK (.
5).
,
dma_active[C], 12 (.
2 3).

.
123 DMA
.

123
397

1
( 394, 1)
4
4-7

7-9
9-10
10

10-11
11
11-14
14-16

, chnl_req_mask_set[C] 0 (. 18)
dma_active[C] (. 2 3) DMA

, :
rc , channel_cfg;
rsp , src_data_end_ptr;
rdp , dst_data_end_ptr.
DMA , :
RD ;
WD .
, channel_cfg,
wc , channel_cfg
dma_active[C],
DMA (. 4).
(. 1)
, chnl_req_mask_set[C] 0 (. 18).
dma_active[C] 0 HCLK (.
5)
,
dma_active[C] DMA

DMA

341

19861, 19861, 19861, 19861QI, 198614


15-16
T16-T17
17

, DMA
dma_req[C]
channel_cfg
dma_active[C],
DMA (. 4)

,
, ,
dma_stall. dma_stall
.

124 () dma_done[]
:
dma_stall dma_waitonreq[] 0;
dma_stall 1;
dma_waitonreq[] 1.

124 dma_done
398 dma_done, 0 2
1

dma_active[C],
DMA (. 4).

1-2

DMA, cycle_ctrl[2] 0,
1 dma_done[C] HCLK (. 8 9).
dma_done[C] 0 (. 6).

399 dma_done, 10 15
11
12-13
14-15

dma_active[C],
DMA (. 4).
dma_stall.
DMA, cycle_ctrl[2] 0,
1 dma_done[C] HCLK (. 8 9).
dma_done[C] 0 (. 6).

11 dma_done[C],
dma_stall 1 HCLK (. 9 12).

342

19861, 19861, 19861, 19861QI, 198614


400 dma_done, 20 25
20

21-25

DMA, - 1 dma_waitonreq[C]
0 dma_req[C],
dma_active[C] (. 11) dma_done[C] (. 9).
dma_req[C].

24

dma_active[C],
DMA (. 4).

24-25

DMA , cycle_ctrl[2] 0,
1 dma_done[C] HCLK (. 8 9).
dma_done[C] 0 (. 6)


,
2R :
DMA
dma_waitonreq;
DMA
dma_waitonreq dma_sreq.

125 DMA dma_waitonreq

343

19861, 19861, 19861, 19861QI, 198614


401 DMA
dma_waitonreq
0-16
0-1
3-4
4
4-7

7-9
9-11
11-13
15-16
16

dma_waitonreq[C]
(. 10).
(. 1)
, chnl_req_mask_set[C] 0 (. 18).
dma_req[C] dma_sreq[C] 1.
dma_sreq[C] dma_req[C]
(. 16 17).
dma_active[C] (. 2 3) DMA


, :
rc , channel_cfg;
rsp , src_data_end_ptr;
rdp , dst_data_end_ptr.
DMA , :
RD ;
WD .
2 rsp rdp.
dma_req[C] dma_sreq[C].
, channel_cfg,
wc , channel_cfg.
dma_active[C],
DMA (. 11).
chnl_useburst_set[C] 0,
R
2 (. 15).

126 DMA dma_waitonreq 1


DMA .

126 DMA dma_waitonreq dma_sreq

344

19861, 19861, 19861, 19861QI, 198614


402 DMA
dma_waitonreq dma_sreq
0-13
0-1
3-4
4
4-7

7-9

10-11
12_13
13

dma_waitonreq[C]
(. 10).
(. 1)
, chnl_useburst_set[C] 0 (. 13
14).
dma_sreq[C] (. 16).
dma_active[C] (. 2 3) DMA
.
, :
rc , channel_cfg;
rsp , src_data_end_ptr;
rdp , dst_data_end_ptr.
DMA , :
RD ;
WD .
dma_sreq[], , R=0 , ,
1 DMA .
dma_sreq[C].
, channel_cfg,
wc , channel_cfg.
dma_active[C],
DMA (. 11).

29.4.3 DMA
DMA.

.
4 ,
AHB . R 2; R
2 R. , R
4, 16 DMA.
403 .
403 AHB
R
4b0000
4b0001
4b0010
4b0011
4b0100
4b0101
4b0110
4b0111
4b1000
4b1001
4b1010 4b1111

DMA
1
2
4
8
16
32
64
128
256
512
1024

R
,
.
N > 2R (N ) 2R N ,
2R ,
N<2R. N DMA.
R 2 .
.

345

19861, 19861, 19861, 19861QI, 198614

29.4.4

DMA. :
;
, .
()
.
chnl_priority_set.
0 ,
. 404 DMA
.
404 DMA

0
1
2
30
31
0
1
2
30
31

()
()
()
()
()
()
()
()

DMA
DMA. 127
.
! .
127
.
.

.
.
.
DMA.

346

19861, 19861, 19861, 19861QI, 198614

29.4.5 DMA
cycle_ctrl , DMA.
.
405 DMA
cycle_ctrl
3b000
3b001
3b010
3b011
3b100
3b101
3b110
3b111


DMA
-
-







cycle_ctrl ,
channel_cfg . .
DMA 2R DMA.
,
,
2R DMA . , R,
,
.
DMA:
;
;
-;
-;
;
.

DMA
DMA.


. , ,
, DMA :
1. 2R . 0,
3.
2. :
,
;

( ), 1.
3. dma_done[C] 1 HCLK.
DMA.

347

19861, 19861, 19861, 19861QI, 198614


-
,
DMA.


.

.
, DMA :
1. 2R .
0, 3.
2. :
,
;

( ), 1.
3. dma_done[C] 1 HCLK.
DMA.
-
DMA,
, DMA,
. DMA
,
.
128 .

348

19861, 19861, 19861, 19861QI, 198614


. ,
R
cycle_ctrl=b011, 2 = 4, N=6

B. ,
R
cycle_ctrl=b011, 2 = 4, N=12

C. ,
R
cycle_ctrl=b011, 2 = 2, N=2

D. ,
R
cycle_ctrl=b011, 2 = 4, N=5

E. ,
R
cycle_ctrl=b011, 2 = 4, N=7

.
, cycle_ctrl=b000

128 -


.

.

, ,
.
4 DMA.
.
,
.
2 DMA.
dma_done[C] 1
HCLK

349

19861, 19861, 19861, 19861QI, 198614


,
.

:

4 DMA.
.

.
4 DMA.
.

.
4 DMA.
dma_done[C] 1
HCLK .

D.

:

2 DMA.
dma_done[C] 1
HCLK .

E.

D:
D
4 DMA.
.

.
DMA.
dma_done[C] 1
HCLK .

E:
E
4 DMA.
.

.
3 DMA.
dma_done[C] 1
HCLK
.

,
. - , ,
D cycle_ctrl b000, DMA
.
DMA, -,

DMA cycle_ctrl 3b001.

350

19861, 19861, 19861, 19861QI, 198614



, , 4
DMA, .
DMA, .
4 DMA, .
DMA, ,
:

;
.
N

cycle_ctrl 3b000.
dma_done[C] ,
DMA .

. 406
channel_cfg, , ,
.
406 Channel_cfg

31, 30
29, 28
27, 26
25, 24
1714
3
20

2321
2018
134


dst_inc
2b10


dst_size
2b10

src_inc
2b10


src_size
2b10

R_power
4b0010
4
DMA
next_useburst
1b0

0
cycle_ctrl
3b100




dst_prot_ctrl
HPROT

src_prot_ctrl
HPROT

n_minus_1
N*

N DMA, N
4

* R_power 2,
N 4. N/4 ,
.
129
.

351

19861, 19861, 19861, 19861QI, 198614


:
1. A, B, C
D: cycle_ctrl=3b100, 2R=4, N=16.
2. ,
.

129 DMA

:
1.

cycle_ctrl 3b100. 4 ,
2R 4. 4 N 16.
2. A, B, C, D
, src_data_end_ptr.
3. DMA.

dma_req[] .
:

352

19861, 19861, 19861, 19861QI, 198614


,
4 DMA.
.
,
.

.
.
, B
4 DMA.
B.
,
.
B
B.
.
, C
4 DMA.
C.
,
.
C
C.
.
, D
4 DMA.
D.
cycle_ctrl 3b000
, .
,
.
D
D, DMA.
dma_done[C] 1
HCLK .

, , 4
DMA, .
DMA,
dma_active[C] 0.
,
DMA,
.
, ,
, ,
4 DMA, .
DMA,
dma_active[C] 0.
DMA,
, :

;
.

353

19861, 19861, 19861, 19861QI, 198614


N
,
cycle_ctrl 3b000.
dma_done[C] ,
DMA .

. 407
channel_cfg, , ,
.
407 Channel_cfg

31, 30
29, 28
27, 26
25, 24
1714
20

2321
2018
134


dst_inc
2b10


dst_size
2b10

src_inc
2b10


src_size
2b10

R_power
4b0010
4
DMA
cycle_ctrl
3b110




dst_prot_ctrl
HPROT

src_prot_ctrl
HPROT

n_minus_1
N*

N DMA, N
4
next_useburst
1,
chnl_useburst_set[C] 1

* R_power 2,
N 4. N/4 ,
.
130
.
:
1. A, B, C
D: cycle_ctrl=3b110, 2R=4, N=16.
2. ,
.

354

19861, 19861, 19861, 19861QI, 198614

130 DMA


:
1.

cycle_ctrl 3b110. 4 ,
2R 4. 4 N 16.
2. A, B, C, D
, src_data_end_ptr.
3. DMA.

dma_req[]. :

355

19861, 19861, 19861, 19861QI, 198614


,
, 4 DMA.
.

.
.
, B .
4 DMA.
B.
B
B.
3 .
.
, C .
4 DMA.
C.
C
C.
.
, ,
, :
, D .
4 DMA.
D.
cycle_ctrl 3b000
, .
D
D, DMA.
dma_done[C] 1
HCLK .

AHB ,
:
, ;
dma_err 1.
dma_err
, .
:
chnl_enable_set
;
dma_done[], .
, ,
, dma_done[];
,
1, , dma_done[].
, dma_done[],
, .

356

19861, 19861, 19861, 19861QI, 198614

29.5

. :
,
;
,
.
131
, 32
.

131 32- ,

1 .
10
, 0000,
0400, 0800, 000.

357

19861, 19861, 19861, 19861QI, 198614



ctrl_base_ptr.
:
;
, .
408 ,
,
, .
408 ,

1
2
3-4
5-8
9-16
17-32

[9]

[8]

A
[4]

[7]

A
[3]
[3]

[6]

[5]

[4]

A
[2]
[2]
[2]

A
[1]
[1]
[1]
[1]

A
[0]
[0]
[0]
[0]
[0]

[3:0]

0x0
0x4
08

:
= 0 ;
= 1 .
[x:0] DMA.
Address[3:0] :
00
;
04
;
08
;
0 .
,
.

, alt_ctrl_base_ptr .
132 3
DMA .

358

19861, 19861, 19861, 19861QI, 198614

132 DMA,
( Destination end pointer
; Source end pointer ; Control
)
128 .
6
,
0X00, 0X80.

359

19861, 19861, 19861, 19861QI, 198614


409
, DMA,
.
409
-

DMA
1
2
3-4
5-8

9-16
17-32



0xXXXXXX00, 0xXXXXXX20, 0xXXXXXX40, 0xXXXXXX60,
0xXXXXXXC0, 0xXXXXXXE0
0xXXXXXX00, 0xXXXXXX40, 0xXXXXXX80, 0xXXXXXXC0
0xXXXXXX00, 0xXXXXXX80
0xXXXXX000, 0xXXXXX100, 0xXXXXX200, 0xXXXXX300,
0xXXXXX600, 0xXXXXX700,
0xXXXXX800, 0xXXXXX900, 0xXXXXXA00, 0xXXXXXB00,
0xXXXXXE00, 0xXXXXXF00,
0xXXXXX000, 0xXXXXX200, 0xXXXXX400, 0xXXXXX600,
0xXXXXXC00, 0xXXXXXE00
0xXXXXX000, 0xXXXXX400, 0xXXXXX800, 0xXXXXXC00

0xXXXXXX80, 0xXXXXXXA0,

0xXXXXX400, 0xXXXXX500,
0xXXXXXC00, 0xXXXXXD00,
0xXXXXX800, 0xXXXXXA00,


.
32-
DMA:
;
;
;
.

src_data_end_ptr
. 410
.
410 src_data_end_ptr

310

src_data_end_ptr

DMA,
. 2R
DMA.
.

360

19861, 19861, 19861, 19861QI, 198614



dst_data_end_ptr
. 411
.
411 dst_data_end_ptr

310

dst_data_end_ptr

DMA,
. 2R
DMA.
.

channel_cfg
DMA. 412 .
412 channel_cfg

31...30
R/W

29...28
R/W

27...26
R/W

25...24
R/W

23...21
R/W

10
dst_inc

10
dst_size

10
src_inc

10
src__size

dst_prot_crtl

20...18
R/W

17...14
R/W

13...4
R/W

3
R/W

2...0
R/W

Src_prot_ctrl

0010
R_power

n_minus_1

0
next_useburst

100
cycle_ctrl

413 channel_cfg

3130

dst_src

2928

dst_size

=
2b00 = ;
2b01 = (16- );
2b10 = (32- );
2b11 = .
dst_data_end_ptr.
=
2b00 = ;
2b01 = ;
2b10 = ;
2b11 = .
dst_data_end_ptr.
=
2b00 = ;
2b01 = ;
2b10 = ;
2b11 = .
dst_data_end_ptr.


src_size.

361

19861, 19861, 19861, 19861QI, 198614

2726

src_inc

2524

src_size

2321

dst_prot_ctrl

2018

src_prot_ctrl

1714

R_power

=
2b00 = ;
2b01 = (16- );
2b10 = (32- );
2b11 = .
src_data_end_ptr.
=
2b00 = ;
2b01 = ;
2b10 = ;
2b11 = .
src_data_end_ptr.
=
2b00 = ;
2b01 = ;
2b10 = ;
2b11 = .
src_data_end_ptr.

2b00 = ;
2b01 = (16- );
2b10 = (32- );
2b11 = .

HPROT[3:1],

.
[23] HPROT[3]:
0 = HPROT[3] 0 ;
1 = HPROT[3] 1 .
[22] HPROT[2]:
0 = HPROT[2] 0 ;
1 = HPROT[2] 1 .
[21] HPROT[1]:
0 = HPROT[1]

;
1
=
HPROT[1]

.
HPROT[3:1],
.
[20] HPROT[3]:
0 = HPROT[3] 0 ;
1 = HPROT[3] 1 .
[19] HPROT[2]:
0 = HPROT[2] 0 ;
1 = HPROT[2] 1 .
[18] HPROT[1]:
0 = HPROT[1]

;
1 = HPROT[1]

.
DMA
.
:
4b0000 -
DMA;
4b0001 2 DMA;
4b0010 4 DMA;
4b0011 8 DMA;
4b0100 16 DMA;
4b0101 32 DMA;
4b0110 64 DMA;
4b0111 128 DMA;

362

19861, 19861, 19861, 19861QI, 198614

134

20

n_minus_1

next_useburst

cycle_ctrl

4b1000 256 DMA;


4b1001 512 DMA;
4b1010 4b1111 1024
DMA. ,
,
DMA 1024
DMA
DMA,
DMA. ,
DMA.
10- 1
DMA. :
10b0000000000 = 1 DMA;
10b0000000001 = 2 DMA;
10b0000000010 = 3 DMA;
10b0000000011 = 4 DMA;
10b0000000100 = 5 DMA;
10b0000000101 = 6 DMA;
.
10b1111111111 = 1024 DMA.
,
.
DMA
DMA
, chnl_useburst_set[C]
1,
,
DMA,
.
DMA,
,
chnl_useburst_set[C]
0, DMA ,
R
2 . next_useburst ,

chnl_useburst_set[C].
DMA
,
,

next_useburst:
0 chnl_useburst_set[C].
chnl_useburst_set[C] 0,
DMA
,
dma_req[] dma_sreq[],
DMA
.
1 chnl_useburst_set[C]
1. DMA

,
dma_req[], DMA
.
DMA:
3b000 C . ,
;
3b001 .
DMA,
;
3b010 -.


. ,

363

19861, 19861, 19861, 19861QI, 198614


DMA;
3b011 -. DMA

.
DMA,
; DMA,
.

DMA,

.
DMA,
,

cycle_ctrl
3b001 3b010;
3b100
.
.


3b100;
3b101
.
.

3b101;
3b110
. C
.

3b110;
3b111
. C
.

3b111.

DMA 2R DMA
channel_cfg . 2R N
channel_cfg .
dst_size, src_size.
, src_size
,
n_minus_1, dst_size, src_size.
N ,
cycle_ctrl 3b000, channel_cfg .
DMA.

364

19861, 19861, 19861, 19861QI, 198614



DMA,
n_minus_1 , src_inc,
.
DMA,
n_minus_1 , dst_inc,

.
src_inc dst_inc
:
src_inc=b00 and dst_inc=b00

= src_data_end_ptr n_minus_1
= dst_data_end_ptr n_minus_1.

Src_inc=b01 and dst_inc=b01

= src_data_end_ptr (n_minus_1<<1)
= dst_data_end_ptr (n_minus_1<<1).

Src_inc=b01 and dst_inc=b10

= src_data_end_ptr (n_minus_1<<2)
= dst_data_end_ptr (n_minus_1<<2).

Src_inc=b11 and dst_inc=b11

= src_data_end_ptr
= dst_data_end_ptr.

414 DMA 6 .
414 DMA 6
channel_cfg DMA
src_size=2b10, dst_inc=2b10, n_minus_1=3b101, cycle_ctrl=1

*
DMA

0x2AC
5
014
0x2AC
4
010
0x2AC
3
0
0x2AC
2
08
0x2AC
1
04
0x2AC
0
00
channel_cfg DMA
src_size=2b10, dst_inc=2b10, n_minus_1=0, cycle_ctrl=0

0298
029
02A0
02A4
02A8
02A

* ,
dst_inc.
415 DMA 12
.

365

19861, 19861, 19861, 19861QI, 198614


415 DMA 12
channel_cfg DMA
src_size=2b00, dst_inc=2b01, n_minus_1=4b1011, cycle_ctrl=1, R_power=2b11

*
DMA

0x57
11
016
0x57
10
014
0x57
9
012
0x 57
8
010
0x 57
7
0E
0x57
6
0C
0x57
5
0A
0x57
4
08
R
channel_cfg 2 DMA
src_size=2b00, dst_inc=2b01, n_minus_1=3b011, cycle_ctrl=1, R_power=2b11
0x 57
3
06
DMA
0x 57
2
04
0x57
1
02
0x57
0
00
channel_cfg DMA
src_size=2b00, dst_inc=2b01, n_minus_1=0, cycle_ctrl=0**, R_power=2b11

05D1
05D3
05D5
05D7
05D9
05DB
05DD
05DF
05E1
05E3
05E5
05E7

* ,
, dst_inc.
** DMA channel_cfg ,
0 cycle_ctrl.

366

19861, 19861, 19861, 19861QI, 198614

29.6 DMA

.
:
;
.
:

,
;


, , ;

0, , ;
, ,
.
, .
416


status
0x000
RO
0x-nn0000* DMA
DMA
cfg
0x004
WO

ctrl_base_ptr
0x008
R/W 0x00000000


alt_ctrl_base_ptr
0x00C
RO 0x000000nn**


waitonreq_status
0x010
RO 0x00000000

chnl_sw_request
0x014
WO


chnl_useburst_set
0x018
R/W 0x00000000


chnl_useburst_clr
0x01C
WO

chnl_req_mask_set
0x020
R/W 0x00000000


chnl_req_mask_clr
0x024
WO

chnl_enable_set
0x028
R/W 0x00000000

chnl_enable_clr
0x02C
WO

chnl_pri_alt_set
0x030
R/W 0x00000000 /

chnl_pri_alt_clr
0x034
WO
/


chnl_priority_set
0x038
R/W 0x00000000

chnl_priority_clr
0x03C
WO
0x040-0x048

0x04C
R/W 0x00000000
err_clr
0x050-0xDFC

367

19861, 19861, 19861, 19861QI, 198614


* DMA,
, .
** DMA,
.

29.6.1 DMA STATUS


.
. ,
.
417 DMA

31...28
RO
0
test_status

27...21
U
0
-

20...16
RO
0
chnls_minus1

15...8
U
0
-

7...4
RO
0
state

3...1
U
0
-

0
RO
0
master_enable

418 dma_status

3128

test_status

2721
2016

chnls_minus1

158
74

state

31
0

master_enable

:
4b0000 =
;
4b0001 =
;
4b0010 4b1111 =

DMA 1.
:
5b00000 = 1 DMA;
5b00001 = 2 DMA;
5b00010 = 3 DMA;

5b11111 = 32 DMA

.
:
4b0000 = ;
4b0001 = ;
4b0010 = ;
4b0011 = ;
4b0100 = ;
4b0101 = ;
4b0110 = DMA;
4b0111 = ;
4b1000 = ;
4b1001 = ;
4b1010 =
;
4b1011 4b1111 =

:
0 = ;
1 =

368

19861, 19861, 19861, 19861QI, 198614

29.6.2 DMA CFG


.
.
419 DMA

31...8
U
0
-

7...5
WO
0
chnl_prot_ctrl

4...1
U
0
-

0
WO
0
master_enable

420 dma_cfg

318
75


chnl_prot_ctrl

41
0

master_enable

,

, 0.
HPROT[3:1]
AHB-Lite:
7 HPROT[3],
;
6 HPROT[2],
;
5 HPROT[1],
.
[n] = 1,
HPROT 1. [n] = 0,
HPROT c 0.
. 0.
:
0 ;
1 .

29.6.3
CTRL_BASE_PTR
.
.

.
, ,
DMA, ,
. ,
,
.
, .
421

31...10
R/W
0
ctrl_base_ptr

9...0
U
0
-

369

19861, 19861, 19861, 19861QI, 198614


422 ctrl_base_ptr

3110

ctrl_base_ptr

90

,


. .
. 0

29.6.4
ALT_CTRL_BASE_PTR
.
.
, .
.
423

31... 0
RO
0
Alt_ctrl_base_ptr

424 alt_ctrl_base_ptr

310

alt_ctrl_base_ptr

29.6.5
WAITONREQ_STATUS
.
dma_waitonreq[]. ,
.

31
RO
0

......
......
......

2
RO
0

1
RO
0

0
RO
0

......

dma_waitonreg_stat
us
for dma_waitnreg [2]

dma_waitonreg_stat
us
for dma_waitnreg [1]

dma_waitonreg_stat
us
for dma_waitnreg [0]

dma_waitonreg_stat
us
for dma_waitnreg
[31]

425

370

19861, 19861, 19861, 19861QI, 198614


426 dma_waitonreq_status

310

dma_waitonreq_status

,


DMA.
:
[C] = 1 , dma_waitonreq[C]
1;
[C] = 0 , dma_waitonreq[C]
0.

29.6.6
CHNL_SW_REQUEST
.
DMA.

31
WO
0

......
......
......

2
WO
0

1
WO
0

0
WO
0

......

chnl_sw_reque
st
for channel [2]

chnl_sw_reque
st
for channel [1]

chnl_sw_reque
st
for channel [0]

chnl_sw_reque
st
for channel [31]

427

428 chnl_sw_request

310


chnl_sw_request

,


DMA
DMA.
:
[C] = 0 ,
DMA ;
[C] =1 ,
DMA .

, , DMA
.

371

19861, 19861, 19861, 19861QI, 198614

29.6.7 CHNL_USEBURST_SET
.
dma_sreq[]
dma_req[].

31
R/W
0

......
......
......

2
R/W
0

1
R/W
0

0
R/W
0

......

chnl_useburst_set
for channel [2]

chnl_useburst_set
for channel [1]

chnl_useburst_set
for channel [0]

chnl_useburst_set
for channel [31]

429

430 chnl_useburst_set

310


chnl_useburst_set

,


DMA dma_sreq[]
.
:
[C] = 0 , DMA
DMA ,
dma_sreq[]

dma_req[].

R
2 .
[C] = 1 , DMA
DMA ,
R
dma_req[]. 2 .
:
[C] = 0 .
chnl_useburst_clr
0;
[C] = 1
DMA,
R
dma_sreq[]. 2 .

.

2R , ,
(N) 2R, chnl_useburst_set
0. , dma_sreq[] dma_req[].
channel_cfg N , 2R,
chnl_useburst_set ,
dma_req[].
,
next_useburst channel_cfg,
chnl_useburst_set [C] 1 DMA,
.

372

19861, 19861, 19861, 19861QI, 198614

29.6.8 CHNL_USEBURST_CLR
.
dma_sreq[].

31
WO
0

......
......
......

2
WO
0

1
WO
0

0
WO
0

......

chnl_useburst_clr
for channel [2]

chnl_useburst_clr
for channel [1]

chnl_useburst_clr
for channel [0]

chnl_useburst_clr
for channel [31]

431

432 chnl_useburst_clr

310

chnl_useburst_clr


DMA
dma_sreq[].
:
[C] = 0 .

chnl_useburst_set

dma_sreq[];
[C] = 1
DMA, dma_sreq[].

.

373

19861, 19861, 19861, 19861QI, 198614

29.6.9
CHNL_REQ_MASK_SET
.
DMA dma_sreq[] dma_req[].
dma_sreq[] dma_req[]
.

31
R/W
0

......
......
......

2
R/W
0

1
R/W
0

0
R/W
0

......

chnl_reg_mask_set
for dma_reg [2] and
dma_sreg [2]

chnl_reg_mask_set
for dma_reg [1] and
dma_sreg [1]

chnl_reg_mask_set
for dma_reg [0] and
dma_sreg [0]

chnl_reg_mask_set
for dma_reg [31] and
dma_sreg [31]

433

434 chnl_req_mask_set

310


chnl_req_mask_set

dma_sreq[]
dma_req[] DMA
.
:
[C] = 0 , DMA
DMA ;
[C] = 1 , DMA
DMA .
:
[C] = 0 .

chnl_req_mask_clr

;
[C] = 1
DMA, dma_sreq[] dma_req[].

.

374

19861, 19861, 19861, 19861QI, 198614

29.6.10
CHNL_REQ_MASK_CLR
.
DMA dma_sreq[] dma_req[].

......

2
WO
0

1
WO
0

0
WO
0
chnl_reg_mask_clr
for dma_reg [0]
and dma_sreg [0]

......
......
......

chnl_reg_mask_clr
for dma_reg [1]
and dma_sreg [1]

31
WO
0

chnl_reg_mask_clr
for dma_reg [2]
and dma_sreg [2]

chnl_reg_mask_clr
for dma_reg [31] and
dma_sreg [31]

435

436 chnl_req_mask_clr

310

chnl_req_mask_clr


dma_sreq[] dma_req[]
DMA .
:
[C] = 0 .

chnl_req_mask_set

;
[C] = 1
DMA, dma_sreq[] dma_req[].

375

19861, 19861, 19861, 19861QI, 198614

29.6.11 CHNL_ENABLE_SET
. DMA.
DMA.

......

2
R/W
0

1
R/W
0

0
R/W
0
chnl_enable_set
for channel [0]

......
......
......

chnl_enable_set
for channel [1]

31
R/W
0

chnl_enable_set
for channel [2]

chnl_enable_set
for channel [31]

437

438 chnl_enable_set

310

chnl_enable_set

DMA
.
:
[C] = 0 , DMA ;
[C] = 1 , DMA
.
:
[C] = 0 .

chnl_enable_clr

;
[C] = 1 DMA .

376

19861, 19861, 19861, 19861QI, 198614

29.6.12 CHNL_ENABLE_CLR
.
DMA.
439
0
WO
0
chnl_enable_clr
for channel 0

1
WO
0
chnl_enable_clr
for channel 1

......

2
WO
0
chnl_enable_clr
for channel 2

......
......
......

31
WO
0
chnl_enable_clr
for channel 31

440 chnl_enable_clr

310

chnl_enable_clr


DMA.
:
[C] = 0 .
chnl_enable_set
;
[C] = 1 DMA .

.

DMA,

:
- DMA;
- channel_cfg cycle_ctrl
3b000;
- AHB-Lite.

377

19861, 19861, 19861, 19861QI, 198614

29.6.13 /
CHNL_PRI_ALT_SET
.
DMA .
DMA (
DMA).

31
R/W
0

......
......
......

2
R/W
0

1
R/W
0

0
R/W
0

......

chnl_pri_alt_set
for channel [2]

chnl_pri_alt_set
for channel [1]

chnl_pri_alt_set
for channel [0]

chnl_pri_alt_set
for channel [31]

441 /

442 chnl_pri_alt_set

310


chnl_pri_alt_set


DMA,
.
:
[C] = 0 , DMA
;
[C] = 1 , DMA
.
:
[C] = 0 .
chnl_pri_alt_clr [C] 0;
[C] = 1
DMA .

.

chnl_pri_alt_set[C] :
- 4- DMA
DMA

;
- DMA
DMA
-;
- DMA

DMA :
- -;
-

;
-
;

378

19861, 19861, 19861, 19861QI, 198614

29.6.14 /
CHNL_PRI_ALT_CLR
.
DMA .

31
WO
0

......
......
......

2
WO
0

1
WO
0

0
WO
0

......

chnl_pri_alt_clr
for channel [2]

chnl_pri_alt_clr
for channel [1]

chnl_pri_alt_clr
for channel [0]

chnl_pri_alt_clr
for channel [31]

443 /

444 chnl_pri_alt_clr

310

chnl_pri_alt_clr



DMA.
:
[C] = 0 .

chnl_pri_alt_set
;
[C] = 1
DMA .

.
:

chnl_pri_alt_clr[C] :
- 4- DMA

DMA

;
- DMA

DMA -;
- DMA

DMA :
- -
-

379

19861, 19861, 19861, 19861QI, 198614

29.6.15 CHNL_PRIORITY_SET
.
DMA.
DMA.

......

2
R/W
0

1
R/W
0

0
R/W
0
chnl_priority_set
for channel [0]

......
......
......

chnl_priority_set for
channel [1]

31
R/W
0

chnl_priority_set for
channel [2]

chnl_priorit_set for
channel [31]

445

446 chnl_priority_set

310

chnl_priority_set

DMA,
DMA.
:
[C] = 0 , DMA
;
[C] = 1 , DMA
.
:
[C] = 0 .
chnl_priority_clr
C ;
[C] = 1 DMA
.

380

19861, 19861, 19861, 19861QI, 198614

29.6.16 CHNL_PRIORITY_CLR
.
DMA .
31
WO
0

......
......
......

2
WO
0

1
WO
0

0
WO
0

......

chnl_priority_clr
for channel [2]

chnl_priority_clr
for channel [1]

chnl_priority_clr
for channel [0]

chnl_priorit_clr for
channel [31]

447

448 chnl_priority_clr

310

chnl_priority_clr


DMA .
:
[C] = 0 .
chnl_priority_set
C .
[C] = 1 DMA
.

.

381

19861, 19861, 19861, 19861QI, 198614

29.6.17 ERR_CLR
.
dma_err 0. dma_err.
449

311
U
0
-

0
R/W
0
err_clr

450 err_clr

311
0

chnl_priority_set

. 0
0,
() dma_err.
:
[C] = 0 , dma_err
0;
[C] = 1 , dma_err
1.
:
[C] =0 . dma_err
;
[C] =1 () dma_err
0.

err_set, dma_err
1.
dma_err
AHBLite, ,

(
dma_err)

().

382

19861, 19861, 19861, 19861QI, 198614

Ethernet

30

2 :
Ethernet/IEEE802.3
;

Ethernet/IEEE802.3.

ADDR
DATA
nCS[1:0]
nWE

SRAM

TX

nOE

BUS

MII
TX
FIFO

TX_D
TX_EN

TPOP

TX_CLK

RDY

TX_ERR
BUFF
HADDR
BUS

HDATAW

TPON

CRS
COL
PHY
Transceiver

HDATAR
HSIZE[2:0]
HSEL[1:0]
HWRITE

RX_D

AHB

RX

HTRANS

BUS

HREADY

MII
RX
FIFO

...

TPIP

RX_CLK
RX_ERR

HREADYOUT

RX_DV

TPIN

MDIO
MDC
MDIO

PADDR
PDATAW
PDATAR
PSEL
PENABLE
PWRITE

AHB

REGs

PREADY
BUS

...

3216

BMODE[1:0]
EN
MCLK
SW_RESET
HW_RESET

133 Ethernet
- .
HD_EN G_CFG (1 - ).
PAUSE (
PAUSE_EN G_CFG), (
ColWnd G_CFG). (
BUFF_MODE G_CFG).
(BUFF_MODE=2b00),
(BUFF_MODE=201) FIFO (BUFF_MODE=210).
.
(head_R)
(tail_X) .

. FIFO
, 00000,
00004.

383

19861, 19861, 19861, 19861QI, 198614

30.1
()
MAC.
X_CFG:
( EN);
( BE);
( MSB1st);
, EVNT[1] (
EVNT_MODE);
PAD- (
PAD_EN);
( PRE_EN), SFD
;
, CRC
(CRC_EN);
( IPG_EN);
( RtryCnt).
.
3 (
):

;
.
- ,
.
(
) :
, - .
,
tail_X (,
).
MAC
.
,
EVNT_MODE X_CFG.

30.2
,
. (
head_X tail_X) (
EN X_CFG 1). ,
head_X .
,

.
, ,
.

384

19861, 19861, 19861, 19861QI, 198614

30.3
()
MAC.
R_CFG:
( EN);
( BE);
( MSB1st);
, EVNT[0] (
EVNT_MODE);
:
(SF_EN);
(LF_EN);
(CF_EN);
(EF_EN);
MAC-:
MAC- (UCA_EN);
MAC- (BCA_EN);
MAC- (MCA_EN);
MAC- (AC_EN).

.
2 (
):
;
.

( ),
, .
,
head_R.
MAC
.
,
EVNT_MODE R_CFG.

30.4

R_CFG ( EN 1),
. ,
,
,
, . ,
MAC-,
, ..
, .

30.5
BUFF_MODE G_CFG
(G_CFG.BUFF_MODE = 2b00).
.

385

19861, 19861, 19861, 19861QI, 198614

30.6
1
BUFF_MODE G_CFG (G_CFG.BUFF_MODE=2b01).

.

.

.
..

30.7 FIFO
FIFO
. 2
BUFF_MODE G_CFG (G_CFG.BUFF_MODE = 2b10).
/ ,
0x0000 0x0004 .

DBG_XF_EN DBG_RF_EN G_CFG
(
). ,

.

30.8
MAC 2 :
(EVNT[1]) (EVNT[0]).
DMA-
. EVNT .
:
;
/ ;
/ ;
/ .

/ .

.
/ / ,
.

30.9
,
,
Ethernet-.
,
(IFR), (IMR). . 1

386

19861, 19861, 19861, 19861QI, 198614


(IMR) , 0
.
:
MDIO ;
;
.
MDIO
MDIO .
,
.
,
.
. ,
RCLR_EN G_CFGl 1, 1
IFR.

30.10
IEEE 802.3/Ethernet
.
DTRM_EN G_CFGl 1.
( HD_EN = 1 G_CFGl
).
,
JitterWnd ( = JitterWnd + 1),
BAG ( = BAG + 1).

PSC

( = PSC + 1).

30.11

().
.
.

30.12
.
DBG_MODE G_CFGh.

DBG_EN = 1 .
3 :
FreeRun (G_CFGh.DBG_MODE = 2b0X).
;
Halt (G_CFGh.DBG_MODE = 2b10).
;
Stop (G_CFGh.DBG_MODE = 2b11).
/ .

387

19861, 19861, 19861, 19861QI, 198614

30.13
451 Ethernet

0x38000000
0x30000000

( )
0x00

0x02
0x02
0x04
0x06
0x08
0x08
0x0A
0x0C
0x0E
0x10

0x12

0x14
0x16
0x18
0x1A
0x1
0x1E
0x20
0x22
0x24
0x26
0x28

0x2A

0x2C

0x2E

0x30

Ethernet
Ethernet

Ethernet
Ethernet


Delimiter
RW, 0x800

( /
)
MAC-Address
-
MAC_T
RW, 0x78AB
* -
MAC_M
RW, 0x3456
-
MAC_H
RW, 0x0012
-
HASH
HASH-
HASH0
RW, 0x0000
HASH-
HASH1
RW, 0x0000
HASH-
HASH2
RW, 0x0000
HASH-
HASH3
RW, 0x8000
HASH-
IPG
RW, 0x0060


( )
PSC
RW, 0x0031

BAG JitterWnd
(1 50 )
BAG
RW, 0x0063

(100 50 )
JitterWnd
RW, 0x0004

(5 50 )
R_CFG
RW, 0x0507

X_CFG
RW, 0x01FA

G_CFGl
RW, 0x4880
,

G_CFGh
RW, 0x3000
,

IMR
RW, 0x0000

IFR
RW, 0x0000

MDIO_CTRL
RW, 0x0000
MDIO MII
MDIO_DATA
RW, 0x0000
MDIO MII
R_Head
RW, 0x0000

( )
X_Tail
RW, 0x0800

( )
R_Tail
R, 0x0000

( )
X_Head
R, 0x0800

( )
STAT
R, 0x0303

* MSB.

388

19861, 19861, 19861, 19861QI, 198614

30.13.1
452
3116
U

150
Length[15:0]
R/W

453

3116
150


Length[15:0]

30.13.2
454
3123
U

22
UR
R/W

21
LC
R/W

20
RL
R/W

19

18
17
RCOUNT
R/W

16

150
U

455

3123
22


UR

21

LC

20

RL

1916
150

RCOUNT[3:0]
-


1 ;
0 .
Late collision
1 Late collision ;
0 Late collision .

1 ;
0
;

389

19861, 19861, 19861, 19861QI, 198614

30.13.3
456
3127
U

26
UCA
R/W

25
BCA
R/W

24
MCA
R/W

19
SF_ERR
R/W

18
LF_ERR
R/W

17
CF_ERR
R/W

16
PF_ERR
R/W

23
22
SMB_ERR CRC_ERR
R/W
R/W

21
DN_ERR
R/W

20
LEN_ERR
R/W

150

Length[7:0]
R/W

457

3127
26


UCA

25

BCA

24

MCA

23

SMB_ERR

22

CRC_ERR

21

DN_ERR

20

LEN_ERR

19

SF_ERR

18

LF_ERR

17

CF_ERR

16

PF_ERR

150

Length[15:0]

(MAC-
)
1 MAC- MAC-
Ethernet-;
0 MAC- MAC-
Ethernet-.
(MAC = FF_FF_FF)
1 ;
0 .
(MAC HASH)
1 , HASH;
0 HASH .
nibbles
1
0
CRC
1 CRC- CRC;
0 CRC- CRC .
8
1 8
0 8

13,14
1
0
64
1
0
1518
1
0
( MAC
13,14 )
1
0
PAUSE
1 PAUSE
0
, CRC

390

19861, 19861, 19861, 19861QI, 198614

30.13.4 G_CFGh
458 G_CFGh
31
30
DEG_mode
R/W,+0
R/W,+0

29

28

DBG_XF_EN DBG_RF_EN

R/W,+1

R/W,+1

2719
-

18
DLB
R/W,+0

17
RRST
R/W,+0

16
XRST
R/W,+0

30.13.5 G_CFGl
459 G_CFGI
15
-

14
1312
RCLR_EN BUFF_MODE
R/W,+0
R/W,+0

11
EXT_EN
R/W,+1

10
HD_EN
R/W,+0

9
8
DTRM_EN PAUSE_EN
R/W,+0
R/W,+0

70
ColWnd
R/W,+0

460 G_CFGl

3130


DBG_mode

29

DBG_XF_EN

28

DBG_RF_EN

2719
18

DLB

17

RRST

16

XRST

15
14

RCLR_EN

1312

BUFF_MODE

11

EXT_EN

10

HD_EN

,

.
2b00 FreeRun;
2b10 Halt;
2b11 Stop.
FIFO
.
0 ;
1 .
FIFO
.
0 ;
1 .

.
0 ;
1 .
.
0 ;
1 .
.
0 ;
1 .

(IFR)
0 ;
1 .
.
2b00 ;
2b 01 ;
2b 10 FIFO;
2b 11 ( ).

slotTime Extension (
length ,
).
0 ;
1 .
.
0 ;
1 .

391

19861, 19861, 19861, 19861QI, 198614


9

DTRM_EN

PAUSE_EN

70

ColWnd[7:0]

.
0
1
PAUSE.
0 ;
1 .
.
,
.
( 4)

30.13.6 X_CFG
461 X_CFG
15
EN
R/W,+1

14
U

13
BE
R/W,+0

12
MSB1st
R/W,+0

11
U

7
PAD_EN
R/W,+0

6
PRE_EN
R/W,+0

5
CRC_EN
R/W,+0

4
IPG_EN
R/W,+0

10

8
EVNT_MODE
R/W,+5
0
RtryCnt
R/W,+0

462 X_CFG

15


EN

14
13

BE

12

MSB1st

11
108

EVNT_MODE[2:0]

PAD_EN

PRE_EN

CRC_EN

IPG_EN

30

RtryCnt[3:0]

,

.
0 ;
1 .

.
0 LitteleEndian;
1 BigEndian.
.
0 LSB;
1 MSB.

EVNT[1].
3b000 XFIFO ;
3b001 XFIFO ;
3b010 XFIFO ;
3b011 XFIFO ;
3b100 XFIFO ;
3b101 ;
3b110 ;
3b111 .
PAD-.
0 ;
1 .
.
0 ;
1 .
CRC.
0 ;
1 .
.
0 ;
1 .
-

392

19861, 19861, 19861, 19861QI, 198614

30.13.7 R_CFG
463 R_CFG
15
EN
R/W,+1

14
-

13
BE
R/W,+0

12
MSB1st
R/W,+0

11
-

10

7
SF_EN
R/W,+0

6
LF_EN
R/W,+0

5
CF_EN
R/W,+0

4
EF_EN
R/W,+0

3
AC_EN
R/W,+0

2
UCA_EN
R/W,+0

8
EVNT_MODE
R/W,+5
1
BCA_EN
R/W,+0

0
MCA_EN
R/W,+0

464 R_CFG

15


EN

14
13

BE

12

MSB1st

11
108

EVNT_MODE[2:0]

SF_EN

LF_EN

CF_EN

EF_EN

AC_EN

UCA_EN

BCA_EN

MCA_EN

,

.
0 ;
1 .

.
0 LitteleEndian;
1 BigEndian.
.
0 LSB;
1 MSB.

EVNT[1].
3b000 RFIFO ;
3b001 RFIFO ;
3b010 RFIFO ;
3b011 RFIFO ;
3b100 RFIFO ;
3b101 ;
3b110 ;
3b111 .
.
0 ;
1 .
.
0 ;
1 .
.
0 ;
1 .
.
0 ;
1 .
MAC-.
0 ;
1 .
MAC-,
MAC_Address.
0 ;
1 .
MAC-.
0 ;
1 .
MAC- HAS.
0 ;
1 .

393

19861, 19861, 19861, 19861QI, 198614

30.13.8 IMR/IFR
465 IMR/IFR
15
MII_RDY

14
MDIO_INT

13
-

12
CRS_LOS
T
R/W,+0

R,+0

R,+0

7
SF

6
LF

5
CF

R/W,+0

R/W,+0

R/W,+0

11
LC

10
UNDF

9
XF_ERR

8
XF_OK

R/W,+0

R/W,+0

R/W,+0

R/W,+0

2
OVF

1
MISSED_
F
R/W,+0

0
RF_OK

4
3
CRC_ERR SMB_ERR
R/W,+0

R/W,+0

R/W,+0

R/W,+0

466 IMR/IFR

15


MII_RDY

14
13
12

MDIO_INT

11
10
9
8
7
6
5
4

LC
UNDF
XF_ERR
XF_OK
SF
LF
CF
CRC_ERR

3
2
1

SMB_ERR
OVF
MISSED_F

RF_OK

CRS_LOST

,

MDIO

MDIO



LateCollision






CRC
CRC


-

394

19861, 19861, 19861, 19861QI, 198614

30.13.9 STAT
467 STAT
15

14
-

13

12
X_FULL
R,+0

11
X_AFULL
R,+0

10
X_HALF
R,+0

9
X_AEMPY
R,+0

8
X_EMPY
R,+0

6
RCOUNT

4
R_FULL
R,+0

3
R_AFULL
R,+0

2
R_HALF
R,+0

1
R_AEMPY
R,+0

0
R_EMPY
R,+0

468 STAT

1513
12


X_FULL

11

X_AFULL

10

X_HALF

X_AEMPTY

X_EMPTY

75

R_COUNT

R_FULL

R_AFULL

R_HALF

R_AEMPTY

R_EMPTY

1
0
1
0
1
0
1
0
1
0
- ,
0..6 -
7 - >=7
.
R_COUNT
STAT.
1
0
1
0
1
0
1
0
1
0

395

19861, 19861, 19861, 19861QI, 198614

30.13.10

MDIO_CTRL
469 MDIO_CTRL

15
RDY
R/W,+0

14
PRE_EN
R/W,+0

13
OP
R/W,+0

128
PHY_A
R/W,+0

75
DIV
R/W,+0

40
RG_A
R/W,+0

470 MDIO_CTRL

15


RDY

14

PRE_EN

13

OP

128
75

PHY_A[4:0]
DIV

40

RG_A

,

/ MDIO

MDIO_CTRL

MDIO.
.
1 (32 1);
0 .
.
1 ;
0 .
PHY
MDIO

MDC= ETH_CLK / [(DIV+1)*16]


PHY

396

19861, 19861, 19861, 19861QI, 198614

30.14 PHY
PHY Ethernet/IEEE 802.3.
:
10Base-T FD (full duplex);
10Base-T HD (half duplex);
100Base-T FD (full duplex);
100Base-T HD (half duplex);
100Base-FX.
(AutoNegotioation)

.

134 PHY
PHY
. PHY 25
100 3 .

397

19861, 19861, 19861, 19861QI, 198614

135

PHY_CTRL
PHY_STAT .
PHY_CTRL ,
.
PHY_STAT PHY.
16
PHY .

30.14.1
471 PHY

0x30000000

Ethernet

Ethernet

( )

0x34

PHY_Control

PHY

0x36

PHY_Status

PHY

398

19861, 19861, 19861, 19861QI, 198614

30.14.2 PHY_Control
472 PHY_Control
1511
PHYADD
R/W

10
MDC
R/W

9
MDIO_SEL
R/W

8
MDI
R/W

7
FX_EN
R/W

64
-

31
MODE
R/W

0
nRST
R/W

473 PHY_Control

1511


PHYADD[4:0]

10

MDC

MDIO_SEL

MDI

FX_EN

64
31

MODE[2:0]

nRST

,
.
PHY, MII

MII PHY
( MII)
MII
.
1 MII;
0 MII ,
MAC.
MII PHY
( MII)
PHY 100BaseFX.
1 100BaseFX;
0 100BaseFX .

PHY.
3b000 10BaseT HD ;
3b001 10BaseT FD ;
3b010 100BaseT HD ;
3b011 100BaseT FD ;
3b100 100BaseT HD c ;
3b101 ;
3b110 ;
3b111 .
PHY.
0 PHY ;
1 PHY .

399

19861, 19861, 19861, 19861QI, 198614

30.14.3 PHY_Status
474 PHY_Status
1511
-

10
MDINT
RO

9
MDO
RO

8
FX_VALID
RO

76
COL
RO

5
CRS
RO

4
READY
RO

30
LED[3:0]
RO

475 PHY_Status

1511
10


MDINT

MDO

FX_VALID

7...6

COL

CRS

READY

LED3

LED2

LED1

LED0

,
.

PHY.
1 PHY;
0 PHY
( ).
MII PHY
( MII)
.
1 FX;
0 FX .
.
1 ;
0 .
.
1 ;
0 .
PHY.
1 PHY
/;
0 PHY .
PHY.
0 full-duplex;
1 half-duplex.
Carrier sense.
0 Carrier sense (CRS);
1 Carrier sense (CRS).
Link .
0 Link ;
1 Link .
.
0 100 ;
1 10 .

PHY
MDIO_CTRL MDIO_DATA MAC.
PHY.
476 PHY

0
1
2
3
4
5
6
18
29
30
31



PHY 1

PHY 2






PHY

400

19861, 19861, 19861, 19861QI, 198614

30.14.4 (0)
477 (0)

15

Reset

14

Loopback

13

Speed Select

12

11

AutoNegotiation
Enable
Power Down

10

Isolate

Restart AutoNegotiate

Duplex Mode

Collision Test

60

Reserved

PHY.
1 .
.


.
PHY.
1 ;
0 .
.
1 100Mbps;
0 10Mbps.
,
AutoNegotiation (0.12 = 1).
.
1 ;
0 .

.
1 ;
0 .
MII
PHY.
1 PHY MII
0
.
1 ;
0 .
.
PHY.
1 ;
0 .
,
AutoNegotiation (0.12 = 1).
Collision
Test.
1 COL test;
0 COL test .

RW/SC

RW

RW

PHY_CTRL

RW

PHY_CTRL

RW

RW

PHY_CTRL

RW/SC

RW

PHY_CTRL

RW

RO

401

19861, 19861, 19861, 19861QI, 198614

30.14.5 (1)
478 (1)

15

100Base-T4

14

100Base-TX
Full Duplex

13

100Base-TX
Half Duplex

12

10Base-T Full
Duplex

11

10Base-T Half
Duplex

106
5

Reserved
Auto-Negotiate
Complete
Remote Fault

4
3
2

Auto-Negotiate
Ability
Link Status

Jabber Detect

Extended
Capabilities

1 100Base-T4,
0 100Base-T4
1
100Mbps,
0 100Mbps

1 100Mbps,
0 100Mbps

1
10Mbps,
0 10Mbps

1 10Mbps,
0 10Mbps

1
0
1 remote fault
0 remote fault
1
0
1
0
1 jabber
0 jabber
1
0

RO

RO

RO

RO

RO

RO
RO

0
0

RO/LH

RO

RO/LL

RO/LH

RO

30.14.6 PHY (2, 3)


479 PHY (2, 3)

150

PHY ID Number

32- PHY

RW

402

19861, 19861, 19861, 19861QI, 198614

30.14.7 (4)
480 (4)

15

Next Page

14
13

Reserved
Remote Fault

12
1110

Reserved
Pause
Operation

100Base-T4

100Base-TX
Full Duplex

100Base-TX

10Base-T Full
Duplex

10Base-T

40

Selector Field

1 next page ,
0 next page
1 remote fault,
0 remote fault
00 PAUSE
01 PAUSE
10 PAUSE
11
PAUSE
1 100Base-T4,
0 100Base-T4 .
1 100Base-T
,
0 100Base-T

1 100Base-T,
0 100Base-T
1 10Base-T
,
0 10Base-T

1 10Base-T,
0 10Base-T
[00001] IEEE 802.3

RO

RO
RW

0
0

R/W
R/W

0
00

RO

RW

PHY_CTRL

RW

RW

PHY_CTRL

RW

PHY_CTRL

RW

00001

403

19861, 19861, 19861, 19861QI, 198614

30.14.8 (5)
481 (5)

15

Next Page

14

Acknowledge

13

Remote Fault

12, 11
10

Reserved
Pause
Operation
100Base-T4

9
8

100Base-TX
Full Duplex

100Base-TX

10Base-T Full
Duplex

10Base-T

40

Selector Field

1 next page ,
0 next page
1 link
0 link
1 remote fault,
0 remote fault
1 PAUSE
0 PAUSE
1 100Base-T4,
0 100Base-T4 .
1 100Base-T
,
0 100Base-T

1 100Base-T,
0 100Base-T
1 10Base-T
,
0 10Base-T

1 10Base-T,
0 10Base-T
[00001] IEEE 802.3

RO

RO

RO

RO
RO

0
0

RO

RO

RO

RO

RO

RO

00001

30.14.9 (6)
482 (6)

155
4

Reserved
Parallel
Detection Fault

Link Partner
Next Page Able
Next Page Able
Page Received

2
1
0

Link Partner
AutoNegotiation Able

1 parallel detection
logic
0
1 next page
0 next page
next page
1
0
1 link partner has auto-negotiation ability 0
link partner does not have auto-negotiation
ability

RO
RO/LH

0
0

RO

RO
RO/LH

0
0

RO

404

19861, 19861, 19861, 19861QI, 198614

30.14.10

(18)
483 (18)

1514

MIIMODE

13

CLKSELFREQ

12

DSPBP

11

SQBP

10

FXMODE

PLLBP

ADCBP

75

MODE

40

PHYADD

30.14.11

MII:
00 (MII)

0 (25 MHz)
DSP.

SQUELCH.

RW,
NASR
RO,
NASR
RW,
NASR
RW,
NASR
RW,
NASR

100Base-FX.
(MODE)
011 (100Base-TX
FD) 010 (100Base-TX FD).
PLL.
RW,
NASR
.
RW,
NASR
PHY.
RW,
NASR
PHY Address.
RW,

NASR
MII,
.

0
0
0
0
PHY_CTRL

0
0
PHY_CTRL
0

(29)
484 (29)

158
7

Reserved
INT7

INT6

INT5

INT4

INT3

INT2

INT1

Reserved

Ignore on read.
1 ENERGYON
0
1
0
1 Remote Fault Detected
0
1
0
1

0
1 Parallel Detection Fault
0
1
0

RO/LH
RO/LH

0
0

RO/LH

RO/LH

RO/LH

RO/LH

RO/LH

RO/LH

RO/LH

405

19861, 19861, 19861, 19861QI, 198614

30.14.12

(30)
485 (30)

158
70

30.14.13

Reserved
Mask Bits

1
0

RO
RW

0
0

PHY (31)
486 PHY (31)

15, 14
13
12

Reserved

117
6

Reserved
enable 4B5B

5
42

Reserved
Speed Indication

1
0

Autodone

:
0

1
0
/.
1 /
4B5B.
HCDSPEED:
[001] 10Mbps HD
[101] 10Mbps FD
[010] 100Base-TX HD
[110] 100Base-TX FD

Reserved
Scramble Disable 0
1

RW
RO
RO

0
0
0

RW
RW

0
1

RW
RO

0
0

RW
RW

0
0

406

19861, 19861, 19861, 19861QI, 198614

31

(NVIC)
.
Handler.

.

:
.

, ;
,
. 0 -
EPSR . 0
Hard Fault
;
NVIC
(late-arriving)
;
4
;
Handler Thread;
C/C++
ARM Architecture Procedure Call Standard (AAPCS);
.

407

19861, 19861, 19861, 19861QI, 198614

31.1
. ,
.
, .
. , AHB .
, .
.
, .

, 00.
, , .
, , .
487

RESET

-3 ()

NMI

-2

Hard Fault

-1

4-10
11

SVCall

12-13
14

PendSV

15

SysTick

IRQ

16-47




.

Thread
.
:


;


,
SVC


.


.

408

19861, 19861, 19861, 19861QI, 198614

31.2
,
.
488

(Late-arriving)


, ,
. ,
.

, .
.
. ,
. ITCM,
DTCM AHB-Lite :
, ;
TCM.
AHB-Lite ITCM
ITCM.
,
Thread .

,
.
,
.

,

.
,
.
,
.

,
.

31.3
NVIC .
0 3 IP_N
. 0 ,
3 . , 1 IRQ[0]
0 IRQ[31], IRQ[31] IRQ[0].
NMI Hard
Fault. , .
,
,
. , IRQ[0] IRQ[1] 1, IRQ[0]
IRQ[1].
,
. ,
, .

409

19861, 19861, 19861, 19861QI, 198614

31.4
.
.
Thread , SP_process SP_main.
.
Handler .
,
, .
Thread ,
SP_process SP_main
Active Stack Pointer CONTROL .
,
Handler, SP_main,
Handler.
EXC_RETURN ,
. EXC_RETURN R14
,
. ,
, EXC_RETURN .
SP_main
. MSR MRS .

410

19861, 19861, 19861, 19861QI, 198614

31.5
,
8 :
xPSR;
;
(LR);
R12;
R3;
R2;
R1;
R0.
SP 8 . 136
,
.

SP
xPSR

LR
R12
R2
R3
R1
R0

SP
136 ,

8
. EXC_RETURN LR
, C/C++
.
, .
489

SP_main

LR
PC

xPSR, , LR, R12, R3, R2, R1 R0 .


:
(00)+( *4).
8 .
SP_main .
SP_main .
LR EXC_RETURN
.
PC .
,
.
.

411

19861, 19861, 19861, 19861QI, 198614

31.6
PC EXC_RETURN,
LR .
,
.
,
, Thread.
, .
490

SP

CONTROL[1] EXC_RETURN.
R0, R1, R2, R3, R12, LR, PC xPSR
EXC_RETURN. xPSR[5:0]
, ,
.
EXC_RETURN , .

,
Handler PC 0xFXXXXXXX:
POP, PC;
BX .
, , PC,
EXC_RETURN.

EXC_RETURN[3:0].
491 ,
EXC_RETURN[3:0]
4bXXX0
4b0001

4b0011
4b01X1
4b1001

4b1101

4b1X11

Handler.
.

SP_Main.

Thread.
SP_Main.

SP_Main.
Thread.
Process.

SP_Process.

EXC_RETURN PC Thread
, , ,
. XN
( ), Hard Fault.
EXC_RETURN[28:4]
.

412

19861, 19861, 19861, 19861QI, 198614

31.7 (late-arriving)

,
:
;
, ,
.

.
, . ,
,
.

, ,
.
, .

31.8
492 ,
.
492 , ,

,

.
,
, ,
. ,

.

, .

.
(
),
.
,
,
.

.
.

413

19861, 19861, 19861, 19861QI, 198614

31.9
, Thread.
Hard Fault , Handler.
493

Thread


Fault handler

494

a
ISR NMI

Hard Fault

SVC







SVC

Thread

a
b
495

Thread

NMI
SVC

PendSV
SysTick

Hard Fault

SVC

, thread


SVCall


,
SVCall.
, SVC Hard
Fault.



b
NMI

a
b Hard Fault NMI Hard
Fault, lock-up.

414

19861, 19861, 19861, 19861QI, 198614

31.10 Lock-up
lock-up,
. ,
SVC .
lock-up -1 -2. NMI
lock-up, -1.
lock-up.
IRQ0 IRQ31
496

IRQ0

MIL-STD-1553B2

IRQ1
IRQ2

MIL-STD-1553B1
USB

IRQ3

CAN1

IRQ4
IRQ5

CAN2
DMA

IRQ6
IRQ7
IRQ8
IRQ9
IRQ10
IRQ11
IRQ12
IRQ13

UART1
UART2
SSP1
BUSY
ARINC429R1ARINC429R8
POWER
WWDG
Timer4

IRQ14
IRQ15
IRQ16
IRQ17

Timer1
Timer2
Timer3
ADC

IRQ18

Ethernet

IRQ19
IRQ20

SSP3
SSP2



52070-2003. 2. VALMESS, ERR,
RFLAGN, IDLE.
. 1
USB Host

HostSOFSent HostConnEvent HostResume
HostTransDone.

USB
Slave


SlaveNAKSent SlaveSOFRXed SlaveResetEvent
SlaveResume SlaveTransDone.
CAN.
GLB_INT_EN

RX_INT_EN[31:0] RX_INT[31:0]
TX_INT_EN[31:0] X_INT[31:0]
ERR_INT_EN (ACKERR FRAMEERR CRCERR
BSERR BITERR)
ERR_OVER_INT_EN
REC > CAN_ERR_MAX
TEC > CAN_ERR_MAX.

DMA
DMA_ERR DMA_DONE.
DMA
Error signaling DMA.
UARTINTR
UARTINTR
SSPINTR
NAND
ARINC429. DR, ERROR, FF, HF.
POWER Detecor
WWDG

TIM_STATUS TIM_IE.


EOCIF_1 AWOIF_1 EOCIF_2 AWOIF_2.

Ehternet.
SSPINTR
SSPINTR

415

19861, 19861, 19861, 19861QI, 198614


IRQ21

ARINC429T1

IRQ22
IRQ23
IRQ24
IRQ25IRQ26
IRQ27
IRQ28

ARINC429T2
ARINC429T3
ARINC429T4

BACKUP
1

IRQ29

IRQ30

IRQ31

18977-79.
FFT, HFT, TX_R.

BKP .
EXT_INT1
PC[5]
EXT_INT2
PC[6]
EXT_INT3
PC[7]
EXT_INT4
PC[8]

416

19861, 19861, 19861, 19861QI, 198614

32

NVIC

NVIC (Nested Vectored Interrupt Controller) ,


. NVIC ,

.
NVIC .
.
NVIC little-endian.
, endian . DAP
little-endian.

32.1 NVIC
NVIC. :
NVIC;
NVIC.
497

ISER

R/W

0xE000E100

0x00000000

ICER

R/W

0xE000E180

0x00000000

ISPR

R/W

0xE000E200

0x00000000

ICPR

R/W

0xE000E280

0x00000000

IPR0

R/W

0xE000E400

0x00000000

IPR1

R/W

0xE000E404

0x00000000

IPR2

R/W

0xE000E408

0x00000000

IPR3

R/W

0xE000E40C

0x00000000

IPR4

R/W

0xE000E410

0x00000000

IPR5

R/W

0xE000E414

0x00000000

IPR6

R/W

0xE000E418

0x00000000

IPR7

R/W

0xE000E41C

0x00000000


0

1

2

3

4

5

6

7

417

19861, 19861, 19861, 19861QI, 198614

32.2
,
. 32-
. .
,
. ,
,
. , ,
.
.

. .
: 0E000E100
: /
: 0x00000000
498

310

SETENA

.
:
1 ;
0 .
:
1 ;
0 .
SETENA .
.
SETENA.

32.3
,
. 32-
. .
: 0E000E180
: /
: 0x00000000

, .
499

310

CLRENA

.
:
1 ;
0 .
:
1 ;
0 .
CLRENA .
.
CLRENA.

418

19861, 19861, 19861, 19861QI, 198614

32.4


,
.
32- .

.
.

.

, .
: 0E000E200
: /
: 0x00000000
500

310

SETPEND

:
1 ;
0 .
:
1 ;
0 .

32.5

,
.
32- .

.

, .
: 0E000E280
: /
: 0x00000000
501

310

CLRPEND

:
1 ;
0 .
:
1 ;
0 .

419

19861, 19861, 19861, 19861QI, 198614

32.6
0 3
. , 3 .
[7:6] .
: 0E000E400- 0E000E41
: /
: 0x00000000
502
E000E400
E000E404
E000E408
E000E40C
E000E410
E000E414
E000E418
E000E41C

31 30
IP_3
IP_7
IP_11
IP_15
IP_19
IP_23
IP_27
IP_31

29

24

23 22
IP_2
IP_6
IP_10
IP_14
IP_18
IP_22
IP_26
IP_30

21

16

15 14
IP_1
IP_5
IP_9
IP_13
IP_17
IP_21
IP_25
IP_29

13

7 6
IP_0
IP_4
IP_8
IP_12
IP_16
IP_20
IP_24
IP_28

503

76

IP_n

32.7
: .
,
(ISR) . , ,
.
,
.
, ,
,
. FIFO , ,
ISR,
. ,
, .
, ,
, NVIC .
ISR,
.
, , ,
. ,
, ,
. ISR , .
, ISR , NVIC
.

.

420

19861, 19861, 19861, 19861QI, 198614

32.8
ISR ,
, .
ISPR ICPR.
, , ,
ISR.
, , ,
ISPR ICPR ,
.
,
ISR ISPR ICPR.
ICPR , ,
, .

32.9
.
, ICER.
ICPR,
.
, 1
ICPR. , ICPR
, .

421

19861, 19861, 19861, 19861QI, 198614

33

(SCB System control block)


.
.
504


(ACTLR)


SysTick (CTRL)

SysTick (LOAD)
SysTick
(VAL)

SysTick (CALIB)
CPUID

(ICSR)

(AIRCR)

(CCR)

2 (SHP2)

3 (SHP3)

(SHCSR)

R/W

0xE000E008

R/W

0xE000E010

28
,

ITCMLAEN
[3].
3 .
0x00000004

R/W

0xE000E014

0x00000000

R/W

RO

0xE000E018

0x00000000

0xE000E01C

0x80000000

RO
a

0xE000ED00
0xE000ED04

0x411CC210
0x00000000

0xE000ED0C

R/W

0xE000ED14

0xFA050000
d
0xFA058000
0x00000208

R/W

0xE000ED1C

0x00000000

R/W

0xE000ED20

0x00000000

R/W

0xE000ED24

0x00000000

a .
B .
C little-endian
d big-endian
SCB .
.

33.1 (ACTLR)

ITCM.
: 0E000E008
: /
: 28 , ITCMLAEN
[3], .

422

19861, 19861, 19861, 19861QI, 198614


505 (ACTLR)

315
4
3

ITCMUAEN
ITCMLAEN

20


ITCM

ITCM

ITCMLAEN,
0x00000000 0x0001FFFF (128 - )
ITCM. ITCMLAEN ,
AHB-Lite 1 .
ITCMUAEN,
0x10000000-0x1000FFFF ITCM.
ITCMUAEN , AHB-Lite.

33.2 SysTick (CTRL)


: 0E000E010
: /
: 0x00000004
506 SysTick (CTRL)

3117
16

COUNTFLAG

15.3
2

CLKSOURCE

TCKINT

ENABLE

1,
.
.

:
1 .
, SysTick
HCLK.
:
0 ,
;
1 ,
.

COUNTFLAG,
.
:
1 . ,
Reload
. ,
COUNTFLAG , ,
TCKINT,
(SysTick_Handler) .
Reload
;
0 .

423

19861, 19861, 19861, 19861QI, 198614

33.3 SysTick (LOAD)


,
SysTick, . Reload
0x00000001-0x00FFFFFF. 0 ,
, COUNTFLAG CTRL
1 0.
Reload :
N
, RELOAD N-1. ,
100 , RELOAD
99.
N
, N. ,
400 , RELOAD 400.
: 0E000E014
: /
: 0x00000000
507 SysTick (LOAD)

3124
230

Reload

, SysTick,
.

33.4 SysTick (VAL)


SysTick.
: 0E000E018
: /
: 0x00000000
508 SysTick (VAL)

3124
230

Current

.

COUNTFLAG CTRL.

424

19861, 19861, 19861, 19861QI, 198614

33.5 SysTick (CALIB)



, .
: 0E000E01
:
: 0x80000000
509 SysTick (CALIB)

31

NOREF

30

SKEW

2924
230

TENMS

. ,
.
.
10 , TENMS.

. ,
.

33.6 CPUID
:
ID ;
;
.
: 0E000ED00
:
: 0x411CC210
510 CPUID

31...24

IMPLEMENTER

23...20

VARIANT

196
5...4

Constant
PARTNO

30

REVISION

:
041 ARM.
:
00 r0p0 r0p1;
0x1 r1p0.
0xC.
:
0xC21.
:
00 r0p0 r1p0;
0x1 r0p1.

425

19861, 19861, 19861, 19861QI, 198614

33.7 (ICSR)
:
NMI;
PendSV;
SysTick;
;
,
;
.
: 0E000ED04
:
: 0x00000000
511 (ICSR)

31

NMIPENDSET


R/W

30, 29
28

PENDSVSET

R/W

27

PENDSVCLR

WO

26

PENDSTSET

R/W

25

PENDSTCLR

WO

24

:
1 NMI;
0 .
NMIPENDSET
NMI. NMI ,
,
, ,
-2.

NMI.


PendSV.
:
0 ;
1 PendSV
.
:
0 PendSV ;
1 PendSV .
1 PENDSVSET
PendSV
.

PendSV.
:
0 ;
1
PendSV.

SysTick.
:
0 ;
1 SysTick
.
:
0 SysTick ;
1 .

SysTick.
:
0 ;
1
SysTick.

426

19861, 19861, 19861, 19861QI, 198614


23

ISRPREEMPT

22

ISRPENDING

RO

RO

2118
1712

VECTPENDING

RO

11...6
50

b
VECTACTIVE

RO

.
, ,
,
. C_MASKINTS

,
:
1

;
0
.
,
.
0
;
1 .

C ,
, ,
.
0 ;
5b
.

PRIMASK.

C .
0 Thread ;
b
6bXXXXXX
.

;
b [5:0] IPSR.

427

19861, 19861, 19861, 19861QI, 198614

33.8
(AIRCR)
:
(endianness)
;

;
.
: 0E000ED0
:
: 0xFA050000 little-endian
0xFA058000 big-endian
512 (AIRCR)

31...16

VECTKEY

WO

ENDIANNESS

RO

SYSRESETREQ

WO

VECTCLRACTIVE

WO

15

14.3
2

.
0x05FA,

.

.
0 (little-endian);
1 (big-endian).


SYSRESETREQ
.

. C_HALT
DHCSR
.
.


.
:
- ;
- DAP
.
:
-
;
- Thread;
- IPSR .

428

19861, 19861, 19861, 19861QI, 198614

33.9 (CCR)

Hard Fault .
: 0E000ED14
:
: 0x00000208
513 (CCR)

31...10
9

STKALIGN

84
3

UNALIGN_TRP

20

.
8
. SP

.

,
Hard Fault.
1.

33.10
,
, .

:
SVCall;
SysTick;
PendSV.
PendSV SVCall . SysTick
SysTick.

33.11 2 (SHP2)
: 0E000ED1
: /
: 0x00000000
514 2 (SHP2)

3130
290

PRI_11
-

11, SVCall

429

19861, 19861, 19861, 19861QI, 198614

33.12 3 (SHP3)
: 0E000ED20
: /
: 0x00000000
515 3 (SHP3)

3130
2924
2322
210

PRI_15
PRI_14
-

15, SysTick

14, PendSV

33.13
(SHCSR)

SVCall.
: 0E000ED24
: /
: 0x00000000
516 (SHCSR)

3116
15

14...0

SVCALLPENDED

1, SVCall .
:
1
SVCall;
0
SVCall.

430

19861, 19861, 19861, 19861QI, 198614

34

34.1
517

0x4006_8000

0x00
004

IWDG

IWDG

IWDG_KR[15:0]
IWDG_PR[2:0]

0x08

IWDG_PRL[11:0]

0x0C

IWDG_SR[1:0]


0x4006_0000

0x00
004
0x08

WWDG

WWDG

WWDG_CR[7:0]
WWDG_CFR[9:0]
WWDG_SR[0]

34.1.1 IWDG_KR
518 IWDG_KR

3116
U
-

150
W
0
KEY[15:0]

519 IWDG_KR

3116
15...0

( , 0x0000).
KEY[15:0]

0xAAAA,
,
.
0x5555
IWDG_PR IWDG_RLR.
0xCCCC
( ,
).

431

19861, 19861, 19861, 19861QI, 198614

34.1.2 IWDG_PR
520 IWDG_PR

31.3
U
-

2
R/W
0
PR2

1
R/W
0
PR1

0
R/W
0
PR0

521 IWDG_PR

31...3
2...0

PR[2:0]
.
3b000 4;
3b001 8;
3b010 16;
3b011 32;
3b100 64;
3b101 128;
3b110 256;
3b111 256.
,
PVU=0 IWDG_SR. IWDG
LSI .

34.1.3 IWDG_PRL
522 IWDG_PRL

31...12
U
-

110
R/W
1
RLR[11:0]

523 IWDG_PRL

31...1
2
11...0

PRL[11:0]

.

IWDG_KR.
,
0xAAAA IWDG_KR.
, .

. ,
RVU=0 IWDG_SR.

432

19861, 19861, 19861, 19861QI, 198614

34.1.4 IWDG_SR
524 IWDG_SR

312
U
-

1
R
0
RVU

0
R
0
PVU

525 IWDG_SR

31.2
1

RVU

PVU

.
,

IWDG_PRL. ,
.
IWDG_PRL. ,
.
.
,

IWDG_PR. ,
.
, .

34.1.5 WWDG_CR
526 WWDG_CR

31...8
U
-

7
R/S
0
WDGA

6
R/W
1
T6

5
R/W
1
T5

4
R/W
1
T4

3
R/W
1
T3

2
R/W
1
T2

1
R/W
1
T1

0
R/W
1
T0

527 WWDG_CR

31...8
7

6..0


WDGA

T[6:0]

.

. WDGA=1,
.
1 ;
0 .
(
).
,
4096*2*WGTB PCLK
APB.

433

19861, 19861, 19861, 19861QI, 198614

34.1.6 WWDG_CFR
528 WWDG_CFR

3110
U
-

4
R/W
1
W4

9
R/S
0
EWI

8
R/W
0
WDGTB1
3
R/W
1
W3

7
R/W
0
WDGTB0
2
R/W
1
W2

6
R/W
1
W6
1
R/W
1
W1

5
R/W
1
W5
0
R/W
1
W0

529 WWDG_CFR

31...10
9


EWI

8..7

WGTB[1:0]

6..0

W[6:0]

.
,
0x40.
.
.
2b00 (PCLK / 4096) /1;
2b01 (PCLK / 4096) /2;
2b10 (PCLK / 4096) /4;
2b11 (PCLK / 4096) /8.
.
,
T[6:0]
0x40 0x7F.
T > W, RESET.
T = 0x3F,
.

34.1.7 WWDG_SR
530 WWDG_SR

311
U
-

0
R/C
0
EWIF

531 WWDG_CFR

31...1
0

EWIF
.
,
0x40.
. .
, EWI=0.

434

19861, 19861, 19861, 19861QI, 198614

35

,
,
,

,
, ,
( )
: PA, PB, PC, PD, PE, PF, RESET,
WAKEUP, DN, DP
: OSC_IN
BYPASS=1
, ,
: PD (7-15), PE (0-2, 6-7), DN, DP
: PA, PB, PC, PD (0-6), PE (3-5,
8-15), PF, RESET, WAKEUP
: OSC_IN
BYPASS=1
, ,
( )
: PA, PB, PC, PD, PE, PF, DN,
DP
, ,
: PA, PB, PC, PD, PE (0-5,
8-15), PF, DN, DP
: PE 6, 7

,

,

HSE,
: BYPASS=0
: BYPASS=1

LSE,
: BYPASS=0
: BYPASS=1

PLL,

532 -

UCC

3,0

3,6

4,0

UCCA

3,0

3,6

4,0

UCCB

1,8

3,6

4,0

0,8

0,3

0,8

0,3

2,0

UCC

UCC +0,3

2,0

5,25

5,3

2,0

UCC

UCC +0,3

10

10

10

fC

144

f_ADC

14

16

144

32

33

1 000

16

UIL

UIH

IOL

IOH

fC_HSE

fC_LSE

f_PLL

435

19861, 19861, 19861, 19861QI, 198614



UREF(DAC)

2,4

UCCA

RLOAD

10

CLOAD

100

UADC1_REF-

UCCA-2,4

UCC +0,3

UADC0_REF+

2,4

UCCA

UCC +0,3

UREF(ADC)

2,4

UCCA

UAIN(ADC)

UADC1_REF-

UADC0_REF+

0,3

UCC +0,3

CL

30

25

10
1



, ,
: REFD0, REFD1
,
,


,

,

, ,
UREF(ADC)= UADC0_REF+ UADC1_REF 2) ,
, ,
: PA, PB, PC, PD, PE, PF
, ,
: =25
: =85
: =125

tGS

1 ,
U 0,2 .
2

UADC1_REF-= GNDA UADC0_REF+ = UA, UREF(DAC) = UA


3 .

436

19861, 19861, 19861, 19861QI, 198614

36

,
UOL

0,4

UOH

2,4

1,8

2,1

,

,
, ,
: PA, PB, PC, PD (0-6), PE (3-5, 8-15), PF,
RESET, WAKEUP, ITCMLAEN, JTAGEN, TCK, TDI,
TMS, TRST
: U=UCCA=3,6 , UI= 5,25
, ,
: OSC_IN
: U= UCCA= 3,6 , UI= 0
, ,
: PA, PB, PC, PD, PE, PF, DN, DP,
RESET, WAKEUP, ITCMLAEN, JTAGEN, TCK, TDI,
TMS, TRST
: U=UCCA=3,6 , UI= 5,25
, ,
: OSC_IN
: U=UCCA=3,6 , UI= 3,6
,

UBOR

25,
125,
60
25,
125,
60
25,
125,
60

IILL1

25,
125,
60

IILL2

25,
125,
60

IILH1

25,
125,
60

IILH2

40

40

ICCS

15

IOCC

300

fO_LSI

10

60

fO_HSI

10

fO_PLL

144

,
LSI RC-,
HSI RC-,
PLL,

,
,

533

25,
125,
60
25,
125
60
25,
125,
60
25,
125,
60
25,
125,
60
25,
125,
60

437

ENADC

12

EDLADC

EILADC

EOFFADC

EGAINADC 1

, %


ENDAC

12

EDLDAC

EILDAC

EOFFDAC

40

40

, %

EGAINDAC 2

,
UO_DAC min

0,08

UO_DAC max

UREF(DAC)0,08

,
,

19861, 19861, 19861, 19861QI, 198614

25,
125,
60
25,
125,
60
25,
125
60
25,
125,
60
25,
125,
60
25,
125,
60
25,
125,
60
25,
125,
60
25,
125,
60
25,
125,
60
25,
125,
60
25,
125,
60

438

19861, 19861, 19861, 19861QI, 198614

37

LDO, ,
: IOL= 80
/ , ,
: OSC_IN
: HSE BYPASS=1

, ,
: UCC = 3,6 B, Cl = 100 , Rl = 10
, ,
: U = 2,4 B
,
,
, ,


,
,

,

,
,
: fadc=14 , UCCA=3,6
,
PHY Ethernet
/ ,
,

,


, ,
: 100 /

, ,
: 10 /

\ , , :
100 /

UO_LDO


1,62

1,98

r
f

3,5

tSU(DAC)

5,2

tON_DA

10

IDAC1_UREF

500

IDAC2_UREF

500

IOCCDAC

tA_ADC

4fC_ADC

tAO_ADC

28fC_ADC

IADC0_VREF+

50

IADC0_VREF- 50

25,
125,
60

IOCCADC

fC_ADCMIN

10

NN_RF(PHY)

28

EDLDAC(PHY) 1,6

,
,

534

1,6

EILDAC(PHY)

UOD(PHY)

0,8

UOD1(PHY)

4,4

5,6

tPLH_R(PHY)
tPHL_R(PHY)

25,
125,

439


, ,
|tPLH_R tPHL_R|
tSKEW_R(PHY)

: 100 /
, ,
CYR(PHY)

: 100 /

f_PLL(PHY)
PLL,
124,875
: 100 /

f_PLL1(PHY)
PLL,
19,99
: 10 /
PLL,
_PLL(PHY)

: 100 /
PLL,
_PLL1(PHY) 3,5
: 10 /
EXRES1,
UO(PHY)
1,14

,
,

19861, 19861, 19861, 19861QI, 198614

60
0,5
0,5
125,125

20,01
1,4
3,5
1,34

440

19861, 19861, 19861, 19861QI, 198614

38

137
: fC= 144

138

441

19861, 19861, 19861, 19861QI, 198614

139 (
)

140
3,0

442

19861, 19861, 19861, 19861QI, 198614

141
3,0

443

19861, 19861, 19861, 19861QI, 198614

3,4 - 0,8

0,2 - 0,07

39

50,0 0,5

32 0,625 = 20,0
0,625
67

99

66

132

34

132 0,35-0,07
T/2 0,063

0,625
32 0,625 = 20

100

1
11,0 0,2

33
28,0 0,26

142 4229.132-3

444

19861, 19861, 19861, 19861QI, 198614

143 LQFP144

144 7.01 7,71 () ma


:
1. 85 105 ();
2. , , .

445

19861, 19861, 19861, 19861QI, 198614

40

19861

19861

4229.132-3

60 125

19861

19861

4229.132-3

60 125

19861

19861

4229.132-3

0 70

19861QI

MDR32F1QI

LQFP144

40 85


, .
() .
198614,
.
.

446

19861, 19861, 19861, 19861QI, 198614

1
2
3
4
5

23.12.2011
13.09.2012
12.10.2012
01.11.2012
13.03.2013

1.0.0
1.1.0
1.1.1
1.2.0
1.3.0

26.03.2013

1.3.1

29.03.2013

1.4.0

8
9

30.05.2013
24.07.2013

1.4.1
1.5.1

10

26.09.2013

1.6.1

11

07.10.2013

1.7.1

12

28.10.2013

1.8.1

13

13.12.2013

1.9.1

14

23.12.2013

1.10.1

15
16

15.01.2014
21.01.2014

1.11.1
1.11.2

17

23.01.2014

1.12.2

18

31.01.2014

1.13.3

19

04.03.2014

1.13.4

20

26.03.2014

1.14.1

21

27.03.2014

1.14.2

22

15.04.2014

1.15.0

23

24.04.2014

2.0.0





4
.


2
120

124
2 3. 286 300
17
( Tstb 1).
446, 454, 455, 460,
464, 468, 470, 478.
.

CONTROL8 CONTROL9


16.
24 .117

31(DA) 325, 326, 344
2, JTAG
1

.
8.
521


LQFP144NT20 19861QI;
.85 0
24,
25



11.
Flash-


UART


18, 19
132
449
138, 254, 265
411, 415, 416,
418, 420, 423,
424, 425, 428
281, 282

44, 117

278, 279, 284,


20
17
1, 17-25, 30, 465,
466
455

1, 2, 118
118
1, 466

48-50

321

447

19861, 19861, 19861, 19861QI, 198614


24

07.05.2014

2.0.1

25

10.06.2014

2.1.0

26

07.07.2014

2.2.0

27

12.08.2014

2.3.0

29

29.08.2014

2.4.0

30

08.12.2014

2.5.0

31

11.12.2014

2.6.0

32

29.01.2015

2.7.0

33

19.02.2015

2.8.1


19861

LQFP144

.54.

. Flash

332, 333.
28, 29
2
236
.
.
11, 12,
13

NAND 122.

.
JTAGEN
1.
97, 99, 101, 103,
105, 107, 109, 111.


.


1
185
411
48
283
211

122
115117
11
109-112
2

448